{"schemaVersion":"museum-api-v1","datasetVersion":"2026-10-04","rights":{"compilation":"VLSI Museum-owned editorial and compilation contributions are licensed under CC BY 4.0. This grant does not cover third-party source material.","compilationLicense":{"name":"Creative Commons Attribution 4.0 International","url":"https://creativecommons.org/licenses/by/4.0/","scope":"VLSI Museum-owned editorial and compilation contributions only","attribution":"VLSI Museum — https://museum.vlsi.kr/data; cite the dataset version and indicate changes","effectiveDate":"2026-10-04"},"termsUrl":"https://museum.vlsi.kr/data#reuse-terms","sourceMaterials":"Retain each original source license; no license is granted for third-party material","images":"Image files are excluded; original credits and reuse terms remain on record pages"},"objects":[{"id":"cw-953f5c5af8120036","name":"Broadwell","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2014,"process":"14 nm","aliases":["Intel microarchitectures broadwell (client)"],"fields":[{"key":"Architecture name","value":"Broadwell","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October, 2014","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell U","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell H","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DT","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EX","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell E","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / core name 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 7","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"core name 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Haswell","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Skylake (client)","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Skylake (server)","unit":"","sourceId":"chipswiki-544-r1122","location":"Intel/microarchitectures/broadwell (client) · revision 1122 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2022-01-06. Not an independent measurement.","entityId":"cw-953f5c5af8120036","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","sourceDate":"2022-01-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-544-r1122"],"url":"https://museum.vlsi.kr/objects/cw-953f5c5af8120036"},{"id":"cw-9547cce43c6ad0e0","name":"Am486DX2-80V8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-80v8t"],"fields":[{"key":"Model name","value":"Am486DX2-80V8T","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-80V8T","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-80V8T","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":80,"unit":"MHz","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8560-r26756","location":"Amd/am486/am486dx2-80v8t · revision 26756 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9547cce43c6ad0e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8560-r26756"],"url":"https://museum.vlsi.kr/objects/cw-9547cce43c6ad0e0"},{"id":"cw-954ec00f236aa03b","name":"Xeon E5-1603 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-1000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-1603 v4"],"fields":[{"key":"Model name","value":"Xeon E5-1603 v4","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-1603 v4","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002395400","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-1000","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2PG","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP Workstation","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2.5 MiB","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7750-r25132","location":"Intel/xeon e5/e5-1603 v4 · revision 25132 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-954ec00f236aa03b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7750-r25132"],"url":"https://museum.vlsi.kr/objects/cw-954ec00f236aa03b"},{"id":"cw-955405b834015514","name":"AMD-K6-III/333AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Desktop","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii amd-k6-iii-333afr"],"fields":[{"key":"Model name","value":"AMD-K6-III/333AFR","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/333AFR","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/333AFR","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 13, 1999","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 13, 1999","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Desktop","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8304-r25993","location":"Amd/k6-iii/amd-k6-iii-333afr · revision 25993 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-955405b834015514","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8304-r25993"],"url":"https://museum.vlsi.kr/objects/cw-955405b834015514"},{"id":"cw-95777e7d3633b377","name":"Helio P60 (MT6771)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2018,"architecture":"Cortex-A73","process":"12 nm","aliases":["Mediatek helio mt6771"],"fields":[{"key":"Model name","value":"MT6771 V/C","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P60","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6771","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 2018","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 2018","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.41,"unit":"GiB/s","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G72","unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":800,"unit":"MHz","sourceId":"chipswiki-91-r97049","location":"Mediatek/helio/mt6771 · revision 97049 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-95777e7d3633b377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-91-r97049"],"url":"https://museum.vlsi.kr/objects/cw-95777e7d3633b377"},{"id":"cw-95b1dec1f6e74a20","name":"Xeon E5-2679 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2679 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2679 v4","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2679 v4","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002647800","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2K5","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5,"unit":"MiB","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x256 KiB","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":50,"unit":"MiB","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x2.5 MiB","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7730-r25105","location":"Intel/xeon e5/e5-2679 v4 · revision 25105 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95b1dec1f6e74a20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7730-r25105"],"url":"https://museum.vlsi.kr/objects/cw-95b1dec1f6e74a20"},{"id":"cw-95c5f90b7b02efc4","name":"Gen7.5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2013,"process":"22 nm","aliases":["Intel microarchitectures gen7.5"],"fields":[{"key":"Architecture name","value":"Gen7.5","unit":"","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"June 4, 2013","unit":"","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen7","unit":"","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen8","unit":"","sourceId":"chipswiki-15965-r52700","location":"Intel/microarchitectures/gen7.5 · revision 52700 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-95c5f90b7b02efc4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15965-r52700"],"url":"https://museum.vlsi.kr/objects/cw-95c5f90b7b02efc4"},{"id":"cw-95d66d177859cba2","name":"Snapdragon 712","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2019,"architecture":"Cortex-A75","process":"10 nm","aliases":["Qualcomm snapdragon 700 712"],"fields":[{"key":"Model name","value":"Snapdragon 712","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM712","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 6, 2019","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 6, 2019","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 700","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2300,"unit":"MHz","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 360 Gold","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 360 Silver","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","alternatives":[{"value":"8 Tn","sourceId":"chipswiki-950-r2686","reason":"Qualcomm/snapdragon 700/712 · revision 2686 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 616","unit":"","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":550,"unit":"MHz","sourceId":"chipswiki-950-r2686","location":"Qualcomm/snapdragon 700/712 · revision 2686 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-14. Not an independent measurement.","entityId":"cw-95d66d177859cba2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","sourceDate":"2020-09-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-950-r2686"],"url":"https://museum.vlsi.kr/objects/cw-95d66d177859cba2"},{"id":"cw-95df709ce5c3e513","name":"Core i7-2655LE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2655le"],"fields":[{"key":"Model name","value":"Core i7-2655LE","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2655LE","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700849508","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR078","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7890-r25394","location":"Intel/core i7/i7-2655le · revision 25394 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-95df709ce5c3e513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7890-r25394","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-95df709ce5c3e513"},{"id":"cw-960f38c71cecf8dc","name":"A6","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2012,"architecture":"Swift","process":"32 nm","aliases":["Apple ax a6"],"fields":[{"key":"Model name","value":"A6","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 12, 2012","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 21, 2012","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Swift","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Swift","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":97,"unit":"mm²","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-810-r2070","location":"Apple/ax/a6 · revision 2070 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-960f38c71cecf8dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-810-r2070"],"url":"https://museum.vlsi.kr/objects/cw-960f38c71cecf8dc"},{"id":"cw-969fa066de73ba3b","name":"Xeon D-2191","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2191"],"fields":[{"key":"Model name","value":"Xeon D-2191","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2191","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":86,"unit":"W","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":71.53,"unit":"GiB/s","sourceId":"chipswiki-7160-r22599","location":"Intel/xeon d/d-2191 · revision 22599 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-969fa066de73ba3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7160-r22599","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-969fa066de73ba3b"},{"id":"cw-96a5a48f89ac18fe","name":"Core i7-7Y75","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7Y","year":2016,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7y75"],"fields":[{"key":"Model name","value":"Core i7-7Y75","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7Y75","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739526","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZT","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2VK","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR33X","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7Y","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-4978-r16100","location":"Intel/core i7/i7-7y75 · revision 16100 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-96a5a48f89ac18fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4978-r16100"],"url":"https://museum.vlsi.kr/objects/cw-96a5a48f89ac18fe"},{"id":"cw-96b80160d83cc466","name":"Skylark","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AppliedMicro","year":2018,"process":"16 nm","aliases":["Apm microarchitectures skylark"],"fields":[{"key":"Architecture name","value":"Skylark","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":32,"unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Shadowcat","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Quicksilver","unit":"","sourceId":"chipswiki-4776-r15405","location":"Apm/microarchitectures/skylark · revision 15405 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-96b80160d83cc466","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4776-r15405"],"url":"https://museum.vlsi.kr/objects/cw-96b80160d83cc466"},{"id":"cw-96d10d208fa6c41d","name":"Xeon E5-4667 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4667 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4667 v4","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4667 v4","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002064600","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SF","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4.5,"unit":"MiB","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x256 KiB","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":45,"unit":"MiB","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x2.5 MiB","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7709-r25080","location":"Intel/xeon e5/e5-4667 v4 · revision 25080 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-96d10d208fa6c41d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7709-r25080"],"url":"https://museum.vlsi.kr/objects/cw-96d10d208fa6c41d"},{"id":"cw-96e34b33ba25c0b3","name":"Ryzen 5 2500X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 2500x"],"fields":[{"key":"Model name","value":"Ryzen 5 2500X","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2500X","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4895-r15756","location":"Amd/ryzen 5/2500x · revision 15756 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-96e34b33ba25c0b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4895-r15756","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-96e34b33ba25c0b3"},{"id":"cw-96f2fc107eb0b881","name":"Xeon Platinum 8160","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8160"],"fields":[{"key":"Model name","value":"Xeon Platinum 8160","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8160,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806738160","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405600","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B0","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-218-r445","location":"Intel/xeon platinum/8160 · revision 445 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-24. Not an independent measurement.","entityId":"cw-96f2fc107eb0b881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","sourceDate":"2022-08-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-218-r445"],"url":"https://museum.vlsi.kr/objects/cw-96f2fc107eb0b881"},{"id":"cw-96ffa7e781c61237","name":"Ryzen 7 PRO 3700U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 pro 3700u"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 3700U","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3700U","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM370BC4T4MFG","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 10","unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":10,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-2183-r7371","location":"Amd/ryzen 7/pro 3700u · revision 7371 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-96ffa7e781c61237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2183-r7371"],"url":"https://museum.vlsi.kr/objects/cw-96ffa7e781c61237"},{"id":"cw-9729788569b2cc7a","name":"Rocket Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2021,"process":"14 nm","aliases":["Intel microarchitectures rocket lake"],"fields":[{"key":"Architecture name","value":"Rocket Lake","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"March 16, 2021","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cypress Cove","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Comet Lake","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alder Lake","unit":"","sourceId":"chipswiki-567-r1198","location":"Intel/microarchitectures/rocket lake · revision 1198 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-20. Not an independent measurement.","entityId":"cw-9729788569b2cc7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","sourceDate":"2021-11-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-567-r1198"],"url":"https://museum.vlsi.kr/objects/cw-9729788569b2cc7a"},{"id":"cw-9745bad82195c287","name":"Saphira","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Qualcomm","year":null,"aliases":["Qualcomm microarchitectures saphira"],"fields":[{"key":"Architecture name","value":"Saphira","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.4","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"duplex","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"duplex","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":5,"unit":"MiB","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"block","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"block","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Falkor","unit":"","sourceId":"chipswiki-1696-r5908","location":"Qualcomm/microarchitectures/saphira · revision 5908 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-9745bad82195c287","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1696-r5908"],"url":"https://museum.vlsi.kr/objects/cw-9745bad82195c287"},{"id":"cw-974dee53ec17ec73","name":"Helio P10 (MT6755)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2016,"architecture":"Cortex-A53","process":"28 nm","aliases":["Mediatek helio mt6755"],"fields":[{"key":"Model name","value":"Helio P10","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P10","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6755","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6755","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 1, 2015","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2016","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2000,"unit":"MHz","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1200,"unit":"MHz","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":6.95,"unit":"GiB/s","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T860","unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":700,"unit":"MHz","sourceId":"chipswiki-982-r2784","location":"Mediatek/helio/mt6755 · revision 2784 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-15. Not an independent measurement.","entityId":"cw-974dee53ec17ec73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","sourceDate":"2020-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-982-r2784"],"url":"https://museum.vlsi.kr/objects/cw-974dee53ec17ec73"},{"id":"cw-9758d5101db7e16f","name":"Am186ER–50KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–50ki\\w"],"fields":[{"key":"Model name","value":"Am186ER–50KI\\W","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–50KI\\W","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–50KI\\W","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 31, 1998","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14635-r44696","location":"Amd/am186ex/am186er–50ki\\w · revision 44696 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-9758d5101db7e16f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14635-r44696"],"url":"https://museum.vlsi.kr/objects/cw-9758d5101db7e16f"},{"id":"cw-977ab67a66e72173","name":"Am186CC-25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CC","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cc-25kc\\w"],"fields":[{"key":"Model name","value":"Am186CC-25KC\\W","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CC-25KC\\W","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CC-25KC\\W","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CC","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14691-r44752","location":"Amd/am186cx/am186cc-25kc\\w · revision 44752 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-977ab67a66e72173","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14691-r44752"],"url":"https://museum.vlsi.kr/objects/cw-977ab67a66e72173"},{"id":"cw-97901223327f64f0","name":"EPYC 7502P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7502p"],"fields":[{"key":"Model name","value":"EPYC 7502P","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7502P","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000045","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000045WOF","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-863-r2246","location":"Amd/epyc/7502p · revision 2246 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-97901223327f64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-863-r2246"],"url":"https://museum.vlsi.kr/objects/cw-97901223327f64f0"},{"id":"cw-97a4bf7b2fbbed0b","name":"C80286-12","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"C80286","year":1984,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 c80286-12"],"fields":[{"key":"Model name","value":"C80286-12","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C80286-12","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C80286","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":12.5,"unit":"MHz","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8605-r26803","location":"Amd/am286/c80286-12 · revision 26803 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97a4bf7b2fbbed0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8605-r26803"],"url":"https://museum.vlsi.kr/objects/cw-97a4bf7b2fbbed0b"},{"id":"cw-97e8a697edad87ed","name":"N80L286-10","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80L286","year":1989,"architecture":"80286","aliases":["Amd am286 n80l286-10"],"fields":[{"key":"Model name","value":"N80L286-10","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80L286-10","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N80L286-10","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80L286","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8590-r26788","location":"Amd/am286/n80l286-10 · revision 26788 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97e8a697edad87ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8590-r26788"],"url":"https://museum.vlsi.kr/objects/cw-97e8a697edad87ed"},{"id":"cw-97f3e50135f5b1d6","name":"AMD-K6-IIIE+/550ACR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iiie+-550acr"],"fields":[{"key":"Model name","value":"AMD-K6-IIIE+/550ACR","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/550ACR","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/550ACR","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8311-r26001","location":"Amd/k6-iii+/amd-k6-iiie+-550acr · revision 26001 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-97f3e50135f5b1d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8311-r26001"],"url":"https://museum.vlsi.kr/objects/cw-97f3e50135f5b1d6"},{"id":"cw-9851c57c386cd9ed","name":"Samuel 2","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"VIA Technologies","year":null,"process":"0.15 µm","aliases":["Via technologies microarchitectures samuel 2"],"fields":[{"key":"Architecture name","value":"Samuel 2","unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"VIA Technologies","unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.15,"unit":"µm","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":12,"unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Samuel","unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Ezra","unit":"","sourceId":"chipswiki-7381-r23867","location":"Via technologies/microarchitectures/samuel 2 · revision 23867 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-9851c57c386cd9ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7381-r23867"],"url":"https://museum.vlsi.kr/objects/cw-9851c57c386cd9ed"},{"id":"cw-9854a5681441bd33","name":"SABRE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","year":null,"architecture":"LEON3","process":"65 nm","aliases":["Movidius sabre"],"fields":[{"key":"Model name","value":"SABRE","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SABRE","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6975-r21791","location":"Movidius/sabre · revision 21791 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-9854a5681441bd33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6975-r21791"],"url":"https://museum.vlsi.kr/objects/cw-9854a5681441bd33"},{"id":"cw-985e6da69ace38a9","name":"Alchemy Au1000-500MCC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1000-500mcc"],"fields":[{"key":"Model name","value":"Alchemy Au1000-500MCC","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1000-500MCC","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1000-500MCC","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2000","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 2001","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"DA","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HA","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HB","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HC","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HD","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.500 GB/s","unit":"","sourceId":"chipswiki-485-r969","location":"Alchemy/au1000-500mcc · revision 969 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-985e6da69ace38a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-485-r969"],"url":"https://museum.vlsi.kr/objects/cw-985e6da69ace38a9"},{"id":"cw-988054ede137a6c4","name":"AMD-K6-IIIE+/400ICR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iiie+-400icr"],"fields":[{"key":"Model name","value":"AMD-K6-IIIE+/400ICR","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/400ICR","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/400ICR","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1009-r2860","location":"Amd/k6-iii+/amd-k6-iiie+-400icr · revision 2860 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OBGA-349","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":349,"unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.47,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-988054ede137a6c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1009-r2860","chipswiki-31127-r91599"],"url":"https://museum.vlsi.kr/objects/cw-988054ede137a6c4"},{"id":"cw-98a35fc93c224b95","name":"Am186ED–20VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–20vc\\w"],"fields":[{"key":"Model name","value":"Am186ED–20VC\\W","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–20VC\\W","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–20VC\\W","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14670-r44731","location":"Amd/am186ex/am186ed–20vc\\w · revision 44731 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98a35fc93c224b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14670-r44731"],"url":"https://museum.vlsi.kr/objects/cw-98a35fc93c224b95"},{"id":"cw-98afe414408ac8f8","name":"80186-6/BUC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 80186-6-buc"],"fields":[{"key":"Model name","value":"80186-6/BUC","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"80186-6/BUC","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80186-6/BUC","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8660-r26859","location":"Amd/am186/80186-6-buc · revision 26859 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98afe414408ac8f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8660-r26859"],"url":"https://museum.vlsi.kr/objects/cw-98afe414408ac8f8"},{"id":"cw-98c41fc036bd6b7f","name":"Ryzen 7 PRO 3700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 pro 3700"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 3700","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3700","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000073","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Matisse","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x16 MiB","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-1548-r5055","location":"Amd/ryzen 7/pro 3700 · revision 5055 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-98c41fc036bd6b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1548-r5055","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-98c41fc036bd6b7f"},{"id":"cw-98cd96be1b4a5d1b","name":"Core i7-2629M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2629m"],"fields":[{"key":"Model name","value":"Core i7-2629M","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2629M","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700851111S","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04D","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7896-r25400","location":"Intel/core i7/i7-2629m · revision 25400 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98cd96be1b4a5d1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7896-r25400","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-98cd96be1b4a5d1b"},{"id":"cw-98d0e6ad84d91067","name":"Ryzen 5 PRO 2400G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 pro 2400g"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 2400G","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2400G","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD240BC5M4MFB","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon RX Vega 11","unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1250,"unit":"MHz","sourceId":"chipswiki-3144-r10449","location":"Amd/ryzen 5/pro 2400g · revision 10449 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","sourceDate":"2019-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-07. Not an independent measurement.","entityId":"cw-98d0e6ad84d91067","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3144-r10449","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-98d0e6ad84d91067"},{"id":"cw-98f64a9602b475a9","name":"Am186CH-40KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CU","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186ch-40ki\\w"],"fields":[{"key":"Model name","value":"Am186CU-40KI\\W","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CU-40KI\\W","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CU-40KI\\W","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CU","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14683-r44744","location":"Amd/am186cx/am186ch-40ki\\w · revision 44744 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-98f64a9602b475a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14683-r44744"],"url":"https://museum.vlsi.kr/objects/cw-98f64a9602b475a9"},{"id":"cw-98f81553b310f522","name":"Xeon E7-8837","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-8800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-8837"],"fields":[{"key":"Model name","value":"Xeon E7-8837","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8837","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615006750AB","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8800","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3N","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x3 MiB","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7695-r25065","location":"Intel/xeon e7/e7-8837 · revision 25065 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-98f81553b310f522","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7695-r25065","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-98f81553b310f522"},{"id":"cw-990513f2bf879558","name":"AMD-K6-III/450AFX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Desktop","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii amd-k6-iii-450afx"],"fields":[{"key":"Model name","value":"AMD-K6-III/450AFX","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/450AFX","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/450AFX","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 13, 1999","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 13, 1999","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Desktop","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8301-r25990","location":"Amd/k6-iii/amd-k6-iii-450afx · revision 25990 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-990513f2bf879558","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8301-r25990"],"url":"https://museum.vlsi.kr/objects/cw-990513f2bf879558"},{"id":"cw-9910bc7aa5058366","name":"Atom C3830","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3830"],"fields":[{"key":"Model name","value":"Atom C3830","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3830","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639101","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR386","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":21,"unit":"W","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":672,"unit":"KiB","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":288,"unit":"KiB","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x24 KiB","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-1859-r6393","location":"Intel/atom/c3830 · revision 6393 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9910bc7aa5058366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1859-r6393","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-9910bc7aa5058366"},{"id":"cw-995d5c26be925dbf","name":"Xeon E7-2860","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-2800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-2860"],"fields":[{"key":"Model name","value":"Xeon E7-2860","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-2860","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615005781AB","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-2800","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3H","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.56,"unit":"MiB","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.4 MiB","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7704-r25074","location":"Intel/xeon e7/e7-2860 · revision 25074 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-995d5c26be925dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7704-r25074","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-995d5c26be925dbf"},{"id":"cw-99673f64bd76cd43","name":"Comet Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"14 nm","aliases":["Intel microarchitectures comet lake"],"fields":[{"key":"Architecture name","value":"Comet Lake","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Comet Lake U","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Comet Lake S","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Coffee Lake","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"predecessor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Rocket Lake","unit":"","sourceId":"chipswiki-202-r414","location":"Intel/microarchitectures/comet lake · revision 414 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-99673f64bd76cd43","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-202-r414"],"url":"https://museum.vlsi.kr/objects/cw-99673f64bd76cd43"},{"id":"cw-99d6aeb34d0c39a9","name":"Embedded G-Series T24L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t24l"],"fields":[{"key":"Model name","value":"Embedded G-Series T24L","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T24L","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET24LFQB12GVE","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 1, 2011","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1 × 512 KiB","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-425-r897","location":"Amd/embedded/t24l · revision 897 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-99d6aeb34d0c39a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-425-r897","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-99d6aeb34d0c39a9"},{"id":"cw-99f3c7f3bc1117f8","name":"Atom C3508","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3508"],"fields":[{"key":"Model name","value":"Atom C3508","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3508","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076503693501","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3JX","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":11.25,"unit":"W","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":224,"unit":"KiB","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.82,"unit":"GiB/s","sourceId":"chipswiki-1865-r6401","location":"Intel/atom/c3508 · revision 6401 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-99f3c7f3bc1117f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1865-r6401","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-99f3c7f3bc1117f8"},{"id":"cw-99f86e52b3bef0cf","name":"Helio P23 (MT6763V/MT6763T)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2017,"architecture":"Cortex-A53","process":"16 nm","aliases":["Mediatek helio mt6763t"],"fields":[{"key":"Model name","value":"Helio P23","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P23","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6763V/MT6763T","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2017","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 28, 2017","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1650,"unit":"MHz","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"14.93 GB/s (13.90 GiB/s)","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G71","unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":770,"unit":"MHz","sourceId":"chipswiki-43-r96983","location":"Mediatek/helio/mt6763t · revision 96983 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-99f86e52b3bef0cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-43-r96983"],"url":"https://museum.vlsi.kr/objects/cw-99f86e52b3bef0cf"},{"id":"cw-9a2c166a35f27136","name":"Core i3-7020U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7020u"],"fields":[{"key":"Model name","value":"Intel Core i3-7020U","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7020U","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067703282620","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067703037315","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LD","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3N6","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 10, 2018","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 10, 2018","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7000","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6362-r19754","location":"Intel/core i3/i3-7020u · revision 19754 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","sourceDate":"2018-04-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-20. Not an independent measurement.","entityId":"cw-9a2c166a35f27136","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6362-r19754","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-9a2c166a35f27136"},{"id":"cw-9a5a9ec6b500a06d","name":"Ryzen 3 PRO 3300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 3 pro 3300u"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 3300U","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3300U","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM330BC4T4MFG","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2186-r7377","location":"Amd/ryzen 3/pro 3300u · revision 7377 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-9a5a9ec6b500a06d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2186-r7377"],"url":"https://museum.vlsi.kr/objects/cw-9a5a9ec6b500a06d"},{"id":"cw-9a7766137e2e39cf","name":"Core i5-2487M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2487m"],"fields":[{"key":"Model name","value":"Core i5-2487M","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2487M","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701140900","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0D1","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7957-r25505","location":"Intel/core i5/i5-2487m · revision 25505 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9a7766137e2e39cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7957-r25505","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-9a7766137e2e39cf"},{"id":"cw-9a832c3255beec82","name":"Core i3-8120","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8120"],"fields":[{"key":"Model name","value":"Core i3-8120","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8120","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5558-r17978","location":"Intel/core i3/i3-8120 · revision 17978 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-9a832c3255beec82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5558-r17978"],"url":"https://museum.vlsi.kr/objects/cw-9a832c3255beec82"},{"id":"cw-9a8e3fe716e953ec","name":"Xeon W-2150B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2150b"],"fields":[{"key":"Model name","value":"Xeon W-2150B","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2150B","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2017","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 21, 2017","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-203-r416","location":"Intel/xeon w/w-2150b · revision 416 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-13. Not an independent measurement.","entityId":"cw-9a8e3fe716e953ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","sourceDate":"2022-09-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-203-r416"],"url":"https://museum.vlsi.kr/objects/cw-9a8e3fe716e953ec"},{"id":"cw-9ad33362bf6ee5c3","name":"Core M 5Y10a","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2014,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y10a"],"fields":[{"key":"Model name","value":"Core M 5Y10a","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y10a","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065801988602","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 2, 2014","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2,"unit":"GHz","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR218","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"E0","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1300000000,"unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":82,"unit":"mm²","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1234","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"MiB","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7816-r25265","location":"Intel/core m/5y10a · revision 25265 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ad33362bf6ee5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7816-r25265"],"url":"https://museum.vlsi.kr/objects/cw-9ad33362bf6ee5c3"},{"id":"cw-9ae04306517edc05","name":"Godson-2B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2003,"architecture":"GS464","process":"180 nm","aliases":["Loongson godson 2 2b"],"fields":[{"key":"Model name","value":"Godson-2B","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMICS","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2B","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MZD110","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2003,"unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 17, 2003","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7685-r24980","location":"Loongson/godson 2/2b · revision 24980 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9ae04306517edc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7685-r24980"],"url":"https://museum.vlsi.kr/objects/cw-9ae04306517edc05"},{"id":"cw-9ae2a3ea782c38db","name":"Exynos 3470","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 3","year":2014,"architecture":"Cortex-A7","process":"28 nm","aliases":["Samsung exynos 3470"],"fields":[{"key":"Model name","value":"Exynos 3470","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3470,"unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 1, 2014","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 1, 2014","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 3","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6839-r21313","location":"Samsung/exynos/3470 · revision 21313 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-30. Not an independent measurement.","entityId":"cw-9ae2a3ea782c38db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","sourceDate":"2018-03-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6839-r21313"],"url":"https://museum.vlsi.kr/objects/cw-9ae2a3ea782c38db"},{"id":"cw-9af2c715fd249232","name":"Core i7-740QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2010,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7 i7-740qm"],"fields":[{"key":"Model name","value":"Intel Core i7-740QM","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-740QM","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BY80607005259AA","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80607I7740QM","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1733.33,"unit":"MHz","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2933.33,"unit":"MHz","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBQG","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Clarksfield","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":30,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":774000000,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":296,"unit":"mm²","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","alternatives":[{"value":"16 GiB","sourceId":"chipswiki-1579-r5228","reason":"Intel/core i7/i7-740qm · revision 5228 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Core voltage","value":1.075,"unit":"V","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988A","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G1","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-1579-r5228","location":"Intel/core i7/i7-740qm · revision 5228 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-9af2c715fd249232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1579-r5228"],"url":"https://museum.vlsi.kr/objects/cw-9af2c715fd249232"},{"id":"cw-9af4b1c25576e9eb","name":"CN3005-400 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3005-400bg350-cp"],"fields":[{"key":"Model name","value":"Cavium CN3005-400 CP","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3005-400 CP","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3005-400BG350-CP","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-350","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,017 MiB/s","unit":"","sourceId":"chipswiki-8279-r25939","location":"Cavium/octeon/cn3005-400bg350-cp · revision 25939 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9af4b1c25576e9eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8279-r25939"],"url":"https://museum.vlsi.kr/objects/cw-9af4b1c25576e9eb"},{"id":"cw-9b28af85ec5d99c8","name":"ID8086B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"ID8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 id8086b"],"fields":[{"key":"Model name","value":"AMD ID8086B","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"ID8086B","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"ID8086B","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"ID8086","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8509-r26702","location":"Amd/am8086/id8086b · revision 26702 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b28af85ec5d99c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8509-r26702"],"url":"https://museum.vlsi.kr/objects/cw-9b28af85ec5d99c8"},{"id":"cw-9b43d9cf47c29548","name":"Alchemy Au1550-333MBI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-333mbi"],"fields":[{"key":"Model name","value":"Alchemy Au1550-333MBI","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-333MBI","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-333MBIAA","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1350 mW","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-464-r945","location":"Alchemy/au1550-333mbi · revision 945 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-9b43d9cf47c29548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-464-r945"],"url":"https://museum.vlsi.kr/objects/cw-9b43d9cf47c29548"},{"id":"cw-9b558ead84d04a98","name":"Core i7-6920HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6920hq"],"fields":[{"key":"Model name","value":"Core i7-6920HQ","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6920HQ","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202194719","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FT","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 27, 2015","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3971-r12658","location":"Intel/core i7/i7-6920hq · revision 12658 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-9b558ead84d04a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3971-r12658","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-9b558ead84d04a98"},{"id":"cw-9b675174b5e14966","name":"K6-2/475ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-475ack"],"fields":[{"key":"Model name","value":"K6-2/475ACK","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/475ACK","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/475ACK","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":475,"unit":"MHz","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8342-r26037","location":"Amd/k6-2/k6-2-475ack · revision 26037 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b675174b5e14966","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8342-r26037"],"url":"https://museum.vlsi.kr/objects/cw-9b675174b5e14966"},{"id":"cw-9b735c5308fa50e6","name":"N80C286-16","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80C286","year":1990,"architecture":"80286","process":"800 nm","aliases":["Amd am286 n80c286-16"],"fields":[{"key":"Model name","value":"N80C286-16","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80C286-16","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N80C286-16","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1990,"unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80C286","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":16,"unit":"MHz","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"16 MT/s","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":165,"unit":"°C","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8593-r26791","location":"Amd/am286/n80c286-16 · revision 26791 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9b735c5308fa50e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8593-r26791"],"url":"https://museum.vlsi.kr/objects/cw-9b735c5308fa50e6"},{"id":"cw-9bcd8436b08b4dff","name":"Xeon Gold 6244","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6244"],"fields":[{"key":"Model name","value":"Xeon Gold 6244","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6244,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194202","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF8Z","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1481-r4929","location":"Intel/xeon gold/6244 · revision 4929 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9bcd8436b08b4dff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1481-r4929"],"url":"https://museum.vlsi.kr/objects/cw-9bcd8436b08b4dff"},{"id":"cw-9bce5b39c521f37c","name":"J80186-3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 j80186-3"],"fields":[{"key":"Model name","value":"J80186-3","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J80186-3","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J80186-3","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J80186-3B","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8638-r26837","location":"Amd/am186/j80186-3 · revision 26837 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9bce5b39c521f37c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8638-r26837"],"url":"https://museum.vlsi.kr/objects/cw-9bce5b39c521f37c"},{"id":"cw-9bd99478f14c8022","name":"Xeon W-3265","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3265"],"fields":[{"key":"Model name","value":"Xeon W-3265","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3265","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504153002","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFE","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1644-r5686","location":"Intel/xeon w/w-3265 · revision 5686 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-31. Not an independent measurement.","entityId":"cw-9bd99478f14c8022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","sourceDate":"2019-10-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1644-r5686"],"url":"https://museum.vlsi.kr/objects/cw-9bd99478f14c8022"},{"id":"cw-9be918cc03fb7b22","name":"Xeon Gold 6126T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6126t"],"fields":[{"key":"Model name","value":"Xeon Gold 6126T","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6126T","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593100","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J9","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1515-r4967","location":"Intel/xeon gold/6126t · revision 4967 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9be918cc03fb7b22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1515-r4967"],"url":"https://museum.vlsi.kr/objects/cw-9be918cc03fb7b22"},{"id":"cw-9c02a7f78b6c4cfc","name":"Celeron G4930","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel celeron g4930"],"fields":[{"key":"Model name","value":"Celeron G4930","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4930","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403378114","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YN","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2853-r9577","location":"Intel/celeron/g4930 · revision 9577 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-9c02a7f78b6c4cfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2853-r9577"],"url":"https://museum.vlsi.kr/objects/cw-9c02a7f78b6c4cfc"},{"id":"cw-9c14b2887bbc78ee","name":"4004","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"MCS","year":1971,"architecture":"4004","process":"10 µm","aliases":["Intel mcs-4 4004"],"fields":[{"key":"Model name","value":4004,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4004,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"C4004","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D4004","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P4004","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 15, 1971","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December, 1971","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MCS-4","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MCS","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":500,"unit":"kHz","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":740,"unit":"kHz","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":4004,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":4004,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":4001,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"µm","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2250,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"pMOS","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":12,"unit":"mm²","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":15,"unit":"V","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-16","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-563-r1193","location":"Intel/mcs-4/4004 · revision 1193 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-22. Not an independent measurement.","entityId":"cw-9c14b2887bbc78ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","sourceDate":"2021-11-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-563-r1193"],"url":"https://museum.vlsi.kr/objects/cw-9c14b2887bbc78ee"},{"id":"cw-9c25b422796046d7","name":"Core i3-6100T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6100t"],"fields":[{"key":"Model name","value":"Core i3-6100T","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6100T","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927102","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662I36100T","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662I36100T","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HE","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7985-r25562","location":"Intel/core i3/i3-6100t · revision 25562 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c25b422796046d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7985-r25562","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-9c25b422796046d7"},{"id":"cw-9c2ef111e8fa7f1c","name":"K6-2/550AFX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":2000,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-550afx"],"fields":[{"key":"Model name","value":"K6-2/550AFX","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/550AFX","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/550AFX","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2000","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 22, 2000","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":549.99,"unit":"MHz","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8333-r26028","location":"Amd/k6-2/k6-2-550afx · revision 26028 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c2ef111e8fa7f1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8333-r26028"],"url":"https://museum.vlsi.kr/objects/cw-9c2ef111e8fa7f1c"},{"id":"cw-9c68fff1fca47a4d","name":"Xeon Platinum 8160F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8160f"],"fields":[{"key":"Model name","value":"Xeon Platinum 8160F","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8160F","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593600","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KG","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2560-r8827","location":"Intel/xeon platinum/8160f · revision 8827 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-9c68fff1fca47a4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2560-r8827"],"url":"https://museum.vlsi.kr/objects/cw-9c68fff1fca47a4d"},{"id":"cw-9c94dc4cd1acfbd4","name":"Athlon MP 2600+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2003,"architecture":"K7","process":"130 nm","aliases":["Amd athlon mp amsn2600dkt3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2600+","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2600+","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2600DKT3C","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 4, 2003","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 4, 2003","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133,"unit":"MHz","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":85,"unit":"mm²","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.65,"unit":"V","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8447-r26640","location":"Amd/athlon mp/amsn2600dkt3c · revision 26640 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9c94dc4cd1acfbd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8447-r26640","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-9c94dc4cd1acfbd4"},{"id":"cw-9c96cae533adeeb7","name":"EPYC 7352","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7352"],"fields":[{"key":"Model name","value":"EPYC 7352","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7352,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000077","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000077WOF","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-858-r2238","location":"Amd/epyc/7352 · revision 2238 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-9c96cae533adeeb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-858-r2238"],"url":"https://museum.vlsi.kr/objects/cw-9c96cae533adeeb7"},{"id":"cw-9cb517523569a49b","name":"CN3110-300 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-300bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3110-300 NSP","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-300 NSP","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-300BG868-NSP","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8267-r25927","location":"Cavium/octeon/cn3110-300bg868-nsp · revision 25927 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9cb517523569a49b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8267-r25927","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-9cb517523569a49b"},{"id":"cw-9d1df968d7be614e","name":"KaiXian KX-U6880","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KX-6000","year":null,"architecture":"LuJiaZui","process":"16 nm","aliases":["Zhaoxin kaixian kx-u6880"],"fields":[{"key":"Model name","value":"KaiXian KX-U6880","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KX-U6880","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KX-U6880","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2018","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaiXian","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KX-6000","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LuJiaZui","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4515-r14675","location":"Zhaoxin/kaixian/kx-u6880 · revision 14675 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-9d1df968d7be614e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4515-r14675"],"url":"https://museum.vlsi.kr/objects/cw-9d1df968d7be614e"},{"id":"cw-9d2b7ffa4174cd72","name":"Duron 850 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm0850avs1b"],"fields":[{"key":"Model name","value":"Duron 850","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 850","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0850AVS1B","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 14, 2001","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 14, 2001","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":850,"unit":"MHz","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8415-r26123","location":"Amd/duron/dhm0850avs1b · revision 26123 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9d2b7ffa4174cd72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8415-r26123"],"url":"https://museum.vlsi.kr/objects/cw-9d2b7ffa4174cd72"},{"id":"cw-9d2fe4e0be690525","name":"Gaudi","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Habana","year":2019,"process":"16 nm","aliases":["Habana microarchitectures gaudi"],"fields":[{"key":"Architecture name","value":"Gaudi","unit":"","sourceId":"chipswiki-1035-r2940","location":"Habana/microarchitectures/gaudi · revision 2940 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-16. Not an independent measurement.","entityId":"cw-9d2fe4e0be690525","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgaudi&oldid=2940","sourceDate":"2020-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Habana","unit":"","sourceId":"chipswiki-1035-r2940","location":"Habana/microarchitectures/gaudi · revision 2940 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-16. Not an independent measurement.","entityId":"cw-9d2fe4e0be690525","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgaudi&oldid=2940","sourceDate":"2020-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1035-r2940","location":"Habana/microarchitectures/gaudi · revision 2940 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-16. Not an independent measurement.","entityId":"cw-9d2fe4e0be690525","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgaudi&oldid=2940","sourceDate":"2020-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-1035-r2940","location":"Habana/microarchitectures/gaudi · revision 2940 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-16. Not an independent measurement.","entityId":"cw-9d2fe4e0be690525","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgaudi&oldid=2940","sourceDate":"2020-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1035-r2940","location":"Habana/microarchitectures/gaudi · revision 2940 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-16. Not an independent measurement.","entityId":"cw-9d2fe4e0be690525","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgaudi&oldid=2940","sourceDate":"2020-07-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1035-r2940"],"url":"https://museum.vlsi.kr/objects/cw-9d2fe4e0be690525"},{"id":"cw-9d379ddef43d6f33","name":"Exynos 5250","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 5","year":2011,"architecture":"Cortex-A15","process":"32 nm","aliases":["Samsung exynos 5250"],"fields":[{"key":"Model name","value":"Exynos 5250","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5250,"unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 30, 2011","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 30, 2011","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 5","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6852-r21350","location":"Samsung/exynos/5250 · revision 21350 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-9d379ddef43d6f33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6852-r21350"],"url":"https://museum.vlsi.kr/objects/cw-9d379ddef43d6f33"},{"id":"cw-9d845f59e2832f4e","name":"Ryzen 5 2500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 2500u"],"fields":[{"key":"Model name","value":"Ryzen 5 2500U","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2500U","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 26, 2017","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 26, 2017","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-900-r2384","location":"Amd/ryzen 5/2500u · revision 2384 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","sourceDate":"2020-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-28. Not an independent measurement.","entityId":"cw-9d845f59e2832f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-900-r2384","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-9d845f59e2832f4e"},{"id":"cw-9da4c2daf96a71bf","name":"Ryzen 7 4700U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4700u"],"fields":[{"key":"Model name","value":"Ryzen 7 4700U","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4700U","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000083","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-694-r1689","location":"Amd/ryzen 7/4700u · revision 1689 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9da4c2daf96a71bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-694-r1689"],"url":"https://museum.vlsi.kr/objects/cw-9da4c2daf96a71bf"},{"id":"cw-9db2747c3e3446e2","name":"MSM6250A","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":null,"architecture":"ARM9","process":"90 nm","aliases":["Qualcomm msm6xxx msm6250a"],"fields":[{"key":"Model name","value":"Qualcomm MSM6250A","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6250A","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1858-r6392","location":"Qualcomm/msm6xxx/msm6250a · revision 6392 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-9db2747c3e3446e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1858-r6392"],"url":"https://museum.vlsi.kr/objects/cw-9db2747c3e3446e2"},{"id":"cw-9db376d820a9f551","name":"Xeon Gold 6132","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6132"],"fields":[{"key":"Model name","value":"Xeon Gold 6132","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6132,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303592500","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J3","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1510-r4962","location":"Intel/xeon gold/6132 · revision 4962 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-9db376d820a9f551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1510-r4962"],"url":"https://museum.vlsi.kr/objects/cw-9db376d820a9f551"},{"id":"cw-9e5c40207c99569d","name":"Xeon D-2187NT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2187nt"],"fields":[{"key":"Model name","value":"Xeon D-2187NT","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2187NT","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303534005","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZM","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":110,"unit":"W","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7147-r22561","location":"Intel/xeon d/d-2187nt · revision 22561 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-9e5c40207c99569d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7147-r22561","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-9e5c40207c99569d"},{"id":"cw-9e5f93dbb491764b","name":"Vector Engine Type 10B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NEC","series":"Type 10","year":2018,"architecture":"SX-Aurora","process":"16 nm","aliases":["Nec vector engine type 10b"],"fields":[{"key":"Model name","value":"VE Type 10B","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Type 10B","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Oct 26, 2017","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2018,"unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vector Engine","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Type 10","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SX-Aurora TSUBASA","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":493.68,"unit":"mm²","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":48,"unit":"GiB","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-1600","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":48,"unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,229 GB/s","unit":"","sourceId":"chipswiki-1594-r5332","location":"Nec/vector engine/type 10b · revision 5332 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-9e5f93dbb491764b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1594-r5332"],"url":"https://museum.vlsi.kr/objects/cw-9e5f93dbb491764b"},{"id":"cw-9e677171471910a8","name":"i486SL-25","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SL","year":1992,"architecture":"80486","process":"800 nm","aliases":["Intel 80486 486sl-25"],"fields":[{"key":"Model name","value":"Intel i486SL-25","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SL-25","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SL-25","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 9, 1992","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SL","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX709","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX741","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX745","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX804","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX806","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SL","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1400000,"unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8083-r25734","location":"Intel/80486/486sl-25 · revision 25734 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e677171471910a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8083-r25734"],"url":"https://museum.vlsi.kr/objects/cw-9e677171471910a8"},{"id":"cw-9e7ba41c50215b7a","name":"K6-2/400AFQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400afq"],"fields":[{"key":"Model name","value":"K6-2/400AFQ","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AFQ","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AFQ","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8354-r26049","location":"Amd/k6-2/k6-2-400afq · revision 26049 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9e7ba41c50215b7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8354-r26049"],"url":"https://museum.vlsi.kr/objects/cw-9e7ba41c50215b7a"},{"id":"cw-9e9ce1361864837e","name":"Ryzen 5 PRO 4650GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 pro 4650ge"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 4650GE","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4650GE","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000153","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000153MPK","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-518-r1051","location":"Amd/ryzen 5/pro 4650ge · revision 1051 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-23. Not an independent measurement.","entityId":"cw-9e9ce1361864837e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","sourceDate":"2022-01-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-518-r1051"],"url":"https://museum.vlsi.kr/objects/cw-9e9ce1361864837e"},{"id":"cw-9eb1adc4c49df846","name":"Core i7-7567U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7567u"],"fields":[{"key":"Model name","value":"Core i7-7567U","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7567U","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR367","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7500","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-7829-r25317","reason":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics 650","unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7829-r25317","location":"Intel/core i7/i7-7567u · revision 25317 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9eb1adc4c49df846","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7829-r25317","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-9eb1adc4c49df846"},{"id":"cw-9eb6f9f430b9633d","name":"EyeQ3","kind":"sku","entityType":"product-model","subtype":"sku","company":"Mobileye","year":2014,"process":"40 nm","aliases":["Mobileye eyeq eyeq3"],"fields":[{"key":"Model name","value":"EyeQ3","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Mobileye","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 04, 2011","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 26, 2014","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EyeQ","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.5,"unit":"W","sourceId":"chipswiki-2939-r9839","location":"Mobileye/eyeq/eyeq3 · revision 9839 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-9eb6f9f430b9633d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2939-r9839"],"url":"https://museum.vlsi.kr/objects/cw-9eb6f9f430b9633d"},{"id":"cw-9f13da8ae7267eaf","name":"Xeon E-2286M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2286m"],"fields":[{"key":"Model name","value":"Xeon E-2286M","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2286M","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068404068710","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFCZ","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":5000,"unit":"MHz","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake HR","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":174,"unit":"mm²","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1250,"unit":"MHz","sourceId":"chipswiki-2402-r8025","location":"Intel/xeon e/e-2286m · revision 8025 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-9f13da8ae7267eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2402-r8025"],"url":"https://museum.vlsi.kr/objects/cw-9f13da8ae7267eaf"},{"id":"cw-9f492b535dae8221","name":"FSD Chip","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Tesla (car company)","year":2019,"architecture":"Cortex-A72","process":"14 nm","aliases":["Tesla (car company) fsd chip"],"fields":[{"key":"Model name","value":"FSD Chip","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Tesla (car company)","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 22, 2019","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 10, 2019","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.0-A","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A72","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":6000000000,"unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":260,"unit":"mm²","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":36,"unit":"W","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-597-r1394","location":"Tesla (car company)/fsd chip · revision 1394 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-27. Not an independent measurement.","entityId":"cw-9f492b535dae8221","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","sourceDate":"2021-09-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-597-r1394"],"url":"https://museum.vlsi.kr/objects/cw-9f492b535dae8221"},{"id":"cw-9f6d572827544fa5","name":"Snapdragon 460","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2020,"architecture":"Cortex-A73","process":"11 nm","aliases":["Qualcomm snapdragon 400 460"],"fields":[{"key":"Model name","value":"Snapdragon 450","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Qualcomm","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Snapdragon 460","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SM4250","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 20, 2020","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 20, 2020","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 400","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 240 Gold","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 240 Silver","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":11,"unit":"nm","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-933","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 610","unit":"","sourceId":"chipswiki-682-r1673","location":"Qualcomm/snapdragon 400/460 · revision 1673 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-05. Not an independent measurement.","entityId":"cw-9f6d572827544fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","sourceDate":"2021-06-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-682-r1673"],"url":"https://museum.vlsi.kr/objects/cw-9f6d572827544fa5"},{"id":"cw-9f805cd766a5bf83","name":"Core i3-8020T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8020t"],"fields":[{"key":"Model name","value":"Core i3-8020T","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8020T","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6425-r20052","location":"Intel/core i3/i3-8020t · revision 20052 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-9f805cd766a5bf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6425-r20052"],"url":"https://museum.vlsi.kr/objects/cw-9f805cd766a5bf83"},{"id":"cw-9fa83ffd2cdea8a7","name":"Sophon BM1686","kind":"sku","entityType":"product-model","subtype":"sku","company":"Bitmain","year":2019,"process":"12 nm","aliases":["Bitmain sophon bm1686"],"fields":[{"key":"Model name","value":"Sophon BM1686","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Bitmain","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"BM1686","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2018","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2019","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Sophon","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5066-r16475","location":"Bitmain/sophon/bm1686 · revision 16475 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1599","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1599,"unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":33,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":33,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.18,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-9fa83ffd2cdea8a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5066-r16475","chipswiki-31370-r92158"],"url":"https://museum.vlsi.kr/objects/cw-9fa83ffd2cdea8a7"},{"id":"cw-a013b27b9a6d52f6","name":"TMX1795","kind":"sku","entityType":"product-model","subtype":"cpu","company":"TI","year":null,"aliases":["Ti tmx1795"],"fields":[{"key":"Model name","value":"TI TMX1795","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"TI","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TI","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"TMX1795NS","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Terminal","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 7, 1971","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3100,"unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"Schottky TTL","unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":8008,"unit":"","sourceId":"chipswiki-7636-r24893","location":"Ti/tmx1795 · revision 24893 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a013b27b9a6d52f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7636-r24893"],"url":"https://museum.vlsi.kr/objects/cw-a013b27b9a6d52f6"},{"id":"cw-a0379a4f3c71c5ae","name":"Ryzen 3 PRO 5450U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 3 pro 5450u"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 5450U","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5450U","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000291","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2021","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2021","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-711-r1717","location":"Amd/ryzen 3/pro 5450u · revision 1717 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a0379a4f3c71c5ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-711-r1717"],"url":"https://museum.vlsi.kr/objects/cw-a0379a4f3c71c5ae"},{"id":"cw-a04a240fc9d69cf4","name":"Duron 800 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhg0800avs1b"],"fields":[{"key":"Model name","value":"Duron 800","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 800","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHG0800AVS1B","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2001,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2001,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8419-r26127","location":"Amd/duron/dhg0800avs1b · revision 26127 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a04a240fc9d69cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8419-r26127"],"url":"https://museum.vlsi.kr/objects/cw-a04a240fc9d69cf4"},{"id":"cw-a063f4d62c2d41dd","name":"Am186ER–25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–25kc\\w"],"fields":[{"key":"Model name","value":"Am186ER–25KC\\W","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–25KC\\W","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–25KC\\W","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14648-r44709","location":"Amd/am186ex/am186er–25kc\\w · revision 44709 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a063f4d62c2d41dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14648-r44709"],"url":"https://museum.vlsi.kr/objects/cw-a063f4d62c2d41dd"},{"id":"cw-a0a13d5da28239c6","name":"Steamroller","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2014,"process":"28 nm","aliases":["Amd microarchitectures steamroller"],"fields":[{"key":"Architecture name","value":"Steamroller","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January 14, 2014","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Pilediver","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Excavator","unit":"","sourceId":"chipswiki-7326-r23574","location":"Amd/microarchitectures/steamroller · revision 23574 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-21. Not an independent measurement.","entityId":"cw-a0a13d5da28239c6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","sourceDate":"2018-01-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7326-r23574"],"url":"https://museum.vlsi.kr/objects/cw-a0a13d5da28239c6"},{"id":"cw-a0bf38fc4c1fa8cd","name":"PPS-4/2 (11660)","kind":"sku","entityType":"product-model","subtype":"sku","company":"Rockwell International","year":1975,"architecture":"PPS-4","process":"10 μm","aliases":["Rockwell international pps-4 11660"],"fields":[{"key":"Model name","value":"Rockwell PPS-4/2","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Rockwell International","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Rockwell International","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PPS-4/2","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":11660,"unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 1975","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PPS-4","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":198.864,"unit":"kHz","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"PPS-4","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10 μm","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"KiB","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"600 mW","unit":"","sourceId":"chipswiki-7641-r24900","location":"Rockwell international/pps-4/11660 · revision 24900 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a0bf38fc4c1fa8cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7641-r24900"],"url":"https://museum.vlsi.kr/objects/cw-a0bf38fc4c1fa8cd"},{"id":"cw-a0c20ca42eb170a5","name":"Core i5-6198DU","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6198du"],"fields":[{"key":"Model name","value":"Intel Core i5-6198DU","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6198DU","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201930412","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2NR","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 27, 2015","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 27, 2015","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-3958-r12645","location":"Intel/core i5/i5-6198du · revision 12645 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a0c20ca42eb170a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3958-r12645","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-a0c20ca42eb170a5"},{"id":"cw-a0cccb9a66e6209b","name":"Helio X10 T (MT6795T)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2015,"architecture":"Cortex-A53","process":"28 nm","aliases":["Mediatek helio mt6795t"],"fields":[{"key":"Model name","value":"MediaTek Helio X10 T","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X10 T","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6795T","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6795T","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 15, 2014","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 27, 2015","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"MWPOP-1108","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"MWPOP","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR G6200","unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":700,"unit":"MHz","sourceId":"chipswiki-4995-r16200","location":"Mediatek/helio/mt6795t · revision 16200 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-22. Not an independent measurement.","entityId":"cw-a0cccb9a66e6209b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","sourceDate":"2018-08-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4995-r16200"],"url":"https://museum.vlsi.kr/objects/cw-a0cccb9a66e6209b"},{"id":"cw-a0e0eb6a3bad16db","name":"Ryzen 3 PRO 5350GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 3 pro 5350ge"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 5350GE","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5350GE","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000259","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2021","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-611-r1433","location":"Amd/ryzen 3/pro 5350ge · revision 1433 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-a0e0eb6a3bad16db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-611-r1433"],"url":"https://museum.vlsi.kr/objects/cw-a0e0eb6a3bad16db"},{"id":"cw-a0f40d2c9243ed9e","name":"Ryzen 5 3600XT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 3600xt"],"fields":[{"key":"Model name","value":"Ryzen 5 3600XT","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3600XT","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000281BOX","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 16, 2020","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 7, 2020","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Matisse","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":95,"unit":"W","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x16 MiB","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-782-r1920","location":"Amd/ryzen 5/3600xt · revision 1920 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-a0f40d2c9243ed9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-782-r1920","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-a0f40d2c9243ed9e"},{"id":"cw-a13d739f4e764dd4","name":"Gen9.5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2016,"process":"14 nm","aliases":["Intel microarchitectures gen9.5"],"fields":[{"key":"Architecture name","value":"Gen9.5","unit":"","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 30, 2016","unit":"","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen9","unit":"","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen10","unit":"","sourceId":"chipswiki-1157-r3620","location":"Intel/microarchitectures/gen9.5 · revision 3620 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-08. Not an independent measurement.","entityId":"cw-a13d739f4e764dd4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","sourceDate":"2020-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1157-r3620"],"url":"https://museum.vlsi.kr/objects/cw-a13d739f4e764dd4"},{"id":"cw-a155c1c422d74d8f","name":"Duron 1000 (Morgan)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhd1000amt1b"],"fields":[{"key":"Model name","value":"Duron 1000","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1000","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD1000AMT1B","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 20, 2001","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 20, 2001","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":46.1,"unit":"W","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8428-r26136","location":"Amd/duron/dhd1000amt1b · revision 26136 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a155c1c422d74d8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8428-r26136"],"url":"https://museum.vlsi.kr/objects/cw-a155c1c422d74d8f"},{"id":"cw-a17c5d2e7140bf46","name":"Celeron 787","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"700","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 787"],"fields":[{"key":"Model name","value":"Celeron 787","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":787,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079501","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701345400","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EC","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0VJ","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2011","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2011","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":700,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6947-r21634","location":"Intel/celeron/787 · revision 21634 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a17c5d2e7140bf46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6947-r21634","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-a17c5d2e7140bf46"},{"id":"cw-a1872fb5bc4b06f7","name":"Atom x5-Z8330","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z8000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x5 x5-z8330"],"fields":[{"key":"Model name","value":"Intel Atom x5-Z8330","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-Z8330","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401836619","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z8000","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1440,"unit":"MHz","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1920,"unit":"MHz","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KU","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA592","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8044-r25677","location":"Intel/atom x5/x5-z8330 · revision 25677 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1872fb5bc4b06f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8044-r25677"],"url":"https://museum.vlsi.kr/objects/cw-a1872fb5bc4b06f7"},{"id":"cw-a18d8455e65b2935","name":"Xeon Bronze 3104","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon bronze 3104"],"fields":[{"key":"Model name","value":"Xeon Bronze 3104","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3104,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806733104","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303562000","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GM","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Bronze","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x1 MiB","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-1533-r4989","location":"Intel/xeon bronze/3104 · revision 4989 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a18d8455e65b2935","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1533-r4989"],"url":"https://museum.vlsi.kr/objects/cw-a18d8455e65b2935"},{"id":"cw-a1d7137b5e898458","name":"Core i3-2310M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2310m"],"fields":[{"key":"Model name","value":"Core i3-2310M","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2310M","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700999405","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700999605","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04R","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04S","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8017-r25598","location":"Intel/core i3/i3-2310m · revision 25598 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a1d7137b5e898458","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8017-r25598","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-a1d7137b5e898458"},{"id":"cw-a21d2305e5059364","name":"POWER10","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2021,"process":"7 nm","aliases":["Ibm microarchitectures power10"],"fields":[{"key":"Architecture name","value":"POWER10","unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2021,"unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER9","unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER11","unit":"","sourceId":"chipswiki-1126-r3350","location":"Ibm/microarchitectures/power10 · revision 3350 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-21. Not an independent measurement.","entityId":"cw-a21d2305e5059364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","sourceDate":"2020-05-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1126-r3350"],"url":"https://museum.vlsi.kr/objects/cw-a21d2305e5059364"},{"id":"cw-a231a894b06fc0f8","name":"Goya","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Habana","year":2018,"process":"16 nm","aliases":["Habana microarchitectures goya"],"fields":[{"key":"Architecture name","value":"Goya","unit":"","sourceId":"chipswiki-1535-r4995","location":"Habana/microarchitectures/goya · revision 4995 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-28. Not an independent measurement.","entityId":"cw-a231a894b06fc0f8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgoya&oldid=4995","sourceDate":"2019-12-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Habana","unit":"","sourceId":"chipswiki-1535-r4995","location":"Habana/microarchitectures/goya · revision 4995 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-28. Not an independent measurement.","entityId":"cw-a231a894b06fc0f8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgoya&oldid=4995","sourceDate":"2019-12-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1535-r4995","location":"Habana/microarchitectures/goya · revision 4995 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-28. Not an independent measurement.","entityId":"cw-a231a894b06fc0f8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgoya&oldid=4995","sourceDate":"2019-12-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-1535-r4995","location":"Habana/microarchitectures/goya · revision 4995 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-28. Not an independent measurement.","entityId":"cw-a231a894b06fc0f8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgoya&oldid=4995","sourceDate":"2019-12-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1535-r4995","location":"Habana/microarchitectures/goya · revision 4995 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-28. Not an independent measurement.","entityId":"cw-a231a894b06fc0f8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgoya&oldid=4995","sourceDate":"2019-12-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1535-r4995"],"url":"https://museum.vlsi.kr/objects/cw-a231a894b06fc0f8"},{"id":"cw-a23c79ce98b4db5d","name":"Ryzen 7 4980U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2021,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4980u"],"fields":[{"key":"Model name","value":"Ryzen 7 4980U","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4980U","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 13, 2021","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1950,"unit":"MHz","sourceId":"chipswiki-696-r1691","location":"Amd/ryzen 7/4980u · revision 1691 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-a23c79ce98b4db5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-696-r1691"],"url":"https://museum.vlsi.kr/objects/cw-a23c79ce98b4db5d"},{"id":"cw-a245714b87ee80d5","name":"Atom x3-C3405","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"C3000","year":2015,"architecture":"Silvermont","process":"28 nm","aliases":["Intel atom x3 x3-c3405"],"fields":[{"key":"Model name","value":"Atom x3-C3405","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x3-C3405","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2015","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2015","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x3","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C3000","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Silvermont","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SoFIA","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SoFIA","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8047-r25683","location":"Intel/atom x3/x3-c3405 · revision 25683 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a245714b87ee80d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8047-r25683"],"url":"https://museum.vlsi.kr/objects/cw-a245714b87ee80d5"},{"id":"cw-a2dd7c4e7466aebd","name":"Core i7-7500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7500","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-7500u"],"fields":[{"key":"Model name","value":"Core i7-7500U","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7500U","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067702739740","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR341","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZV","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7500","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-841-r2211","location":"Intel/core i7/i7-7500u · revision 2211 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","sourceDate":"2021-01-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-13. Not an independent measurement.","entityId":"cw-a2dd7c4e7466aebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-841-r2211","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-a2dd7c4e7466aebd"},{"id":"cw-a2e7ce47ad7bf400","name":"CN3630-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-500bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3630-500 SCP","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-500 SCP","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-500BG1521-SCP","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8233-r25892","location":"Cavium/octeon/cn3630-500bg1521-scp · revision 25892 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a2e7ce47ad7bf400","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8233-r25892","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-a2e7ce47ad7bf400"},{"id":"cw-a3109e0a39ad44bc","name":"Ryzen 5 5600U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 5600u"],"fields":[{"key":"Model name","value":"Ryzen 5 5600U","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5600U","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000287","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1800,"unit":"MHz","sourceId":"chipswiki-716-r1723","location":"Amd/ryzen 5/5600u · revision 1723 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-a3109e0a39ad44bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-716-r1723"],"url":"https://museum.vlsi.kr/objects/cw-a3109e0a39ad44bc"},{"id":"cw-a32626561ed3ac4f","name":"Ryzen Embedded V1780B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V1000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded v1780b"],"fields":[{"key":"Model name","value":"Ryzen Embedded V1780B","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V1780B","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1780C3T4MFB","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2018","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2018","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3350,"unit":"MHz","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-932-r2557","location":"Amd/ryzen embedded/v1780b · revision 2557 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-a32626561ed3ac4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-932-r2557"],"url":"https://museum.vlsi.kr/objects/cw-a32626561ed3ac4f"},{"id":"cw-a33f07fdbd01b2ee","name":"Core i5-8210Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Amber Lake","process":"14 nm","aliases":["Intel core i5 i5-8210y"],"fields":[{"key":"Model name","value":"Core i5-8210Y","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8210Y","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739889","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SREKQ","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 30, 2018","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 30, 2018","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Amber Lake","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Amber Lake","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Amber Lake Y","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":7,"unit":"W","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 617","unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-4491-r14592","location":"Intel/core i5/i5-8210y · revision 14592 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-a33f07fdbd01b2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4491-r14592"],"url":"https://museum.vlsi.kr/objects/cw-a33f07fdbd01b2ee"},{"id":"cw-a34617aa70284f0f","name":"Xeon Gold 6134","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6134"],"fields":[{"key":"Model name","value":"Xeon Gold 6134","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6134,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736134","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303330302","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AR","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1509-r4961","location":"Intel/xeon gold/6134 · revision 4961 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a34617aa70284f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1509-r4961"],"url":"https://museum.vlsi.kr/objects/cw-a34617aa70284f0f"},{"id":"cw-a3990d6c70041233","name":"R-Car H2","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"2nd Gen","year":2014,"architecture":"Cortex A15","process":"28 nm","aliases":["Renesas r-car h2"],"fields":[{"key":"Model name","value":"R-Car H2","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"H2","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A7790","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 25, 2013","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2014","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2nd Gen","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1500,"unit":"MHz","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1000,"unit":"MHz","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":780,"unit":"MHz","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex A15","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex A15","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex A7","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SH-4A","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":288,"unit":"KiB","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"9x32 KiB","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":288,"unit":"KiB","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"9x32 KiB","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR G6400","unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":1,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":550,"unit":"MHz","sourceId":"chipswiki-7650-r24911","location":"Renesas/r-car/h2 · revision 24911 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-831","unit":"","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":831,"unit":"","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":27,"unit":"mm","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":27,"unit":"mm","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a3990d6c70041233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7650-r24911","chipswiki-31425-r92293"],"url":"https://museum.vlsi.kr/objects/cw-a3990d6c70041233"},{"id":"cw-a3c224ddd4b5ef3a","name":"Core i3-8300T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8300t"],"fields":[{"key":"Model name","value":"Core i3-8300T","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8300T","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377212","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3Y1","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6453-r20193","location":"Intel/core i3/i3-8300t · revision 20193 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a3c224ddd4b5ef3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6453-r20193"],"url":"https://museum.vlsi.kr/objects/cw-a3c224ddd4b5ef3a"},{"id":"cw-a42028806b0a71eb","name":"Pentium B980","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) b980"],"fields":[{"key":"Model name","value":"Pentium B980","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B980","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700997802","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0J1","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7789-r25225","location":"Intel/pentium (2009)/b980 · revision 25225 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a42028806b0a71eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7789-r25225","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-a42028806b0a71eb"},{"id":"cw-a453023197b19f1d","name":"Xeon E-2288G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2288g"],"fields":[{"key":"Model name","value":"Xeon E-2288G","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2288G","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404224102","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFB3","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":5000,"unit":"MHz","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":174,"unit":"mm²","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":95,"unit":"W","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2404-r8034","location":"Intel/xeon e/e-2288g · revision 8034 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-a453023197b19f1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2404-r8034"],"url":"https://museum.vlsi.kr/objects/cw-a453023197b19f1d"},{"id":"cw-a45f046f0956fd27","name":"Core i7-8650U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-8650u"],"fields":[{"key":"Model name","value":"Core i7-8650U","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8650U","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067703281718","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3L8","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 21, 2017","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 21, 2017","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake R","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":123,"unit":"mm²","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-4367-r14119","location":"Intel/core i7/i7-8650u · revision 14119 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-a45f046f0956fd27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4367-r14119","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-a45f046f0956fd27"},{"id":"cw-a46042cf1dfb76f0","name":"VY86C060A","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1994,"architecture":"ARM6","process":"0.8 µm","aliases":["Vti vl86cx vy86c060a"],"fields":[{"key":"Model name","value":"VY86C060A","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C060A","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C060A","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM6","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM60","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.8,"unit":"µm","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":35530,"unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":5.89,"unit":"mm²","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3,"unit":"","sourceId":"chipswiki-7629-r24884","location":"Vti/vl86cx/vy86c060a · revision 24884 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-144","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":144,"unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a46042cf1dfb76f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7629-r24884","chipswiki-31401-r92231"],"url":"https://museum.vlsi.kr/objects/cw-a46042cf1dfb76f0"},{"id":"cw-a4615f7bbda2481d","name":"i486DX2-40","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX2","year":1992,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx2-40"],"fields":[{"key":"Model name","value":"Intel i486DX2-40","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX2-40","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-40","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SB80486DX2-40","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 3, 1992","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX2","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"20 MT/s","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX722","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8089-r25741","location":"Intel/80486/486dx2-40 · revision 25741 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4615f7bbda2481d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8089-r25741"],"url":"https://museum.vlsi.kr/objects/cw-a4615f7bbda2481d"},{"id":"cw-a466aa92238cc787","name":"POWER9 02CY296","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy296"],"fields":[{"key":"Model name","value":"02CY296","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY296","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY296","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.75,"unit":"GHz","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":88,"unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"11x512 KiB","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":110,"unit":"MiB","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"11x10 MiB","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3950-r12597","location":"Ibm/power/02cy296 · revision 12597 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a466aa92238cc787","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3950-r12597"],"url":"https://museum.vlsi.kr/objects/cw-a466aa92238cc787"},{"id":"cw-a49d7a5e28025084","name":"Xeon Platinum 8256","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8256"],"fields":[{"key":"Model name","value":"Xeon Platinum 8256","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8256,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194701","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806958256","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF94","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1464-r4911","location":"Intel/xeon platinum/8256 · revision 4911 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49d7a5e28025084","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1464-r4911"],"url":"https://museum.vlsi.kr/objects/cw-a49d7a5e28025084"},{"id":"cw-a49df14a1ab00a62","name":"Xeon Gold 5120","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5120"],"fields":[{"key":"Model name","value":"Xeon Gold 5120","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5120,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806735120","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303535900","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GD","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1525-r4977","location":"Intel/xeon gold/5120 · revision 4977 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a49df14a1ab00a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1525-r4977"],"url":"https://museum.vlsi.kr/objects/cw-a49df14a1ab00a62"},{"id":"cw-a4e233adcbae8d65","name":"CN3630-400 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-400bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3630-400 NSP","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-400 NSP","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-400BG1521-NSP","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8237-r25896","location":"Cavium/octeon/cn3630-400bg1521-nsp · revision 25896 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a4e233adcbae8d65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8237-r25896","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-a4e233adcbae8d65"},{"id":"cw-a5077d973d7bb9e6","name":"CN5740-1000 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-1000bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5740-1000 SP","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-1000 SP","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-1000BG1217-SP","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8185-r25844","location":"Cavium/octeon plus/cn5740-1000bg1217-sp · revision 25844 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5077d973d7bb9e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8185-r25844","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-a5077d973d7bb9e6"},{"id":"cw-a50be5b1f2eb2791","name":"Core i5-6287U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6287u"],"fields":[{"key":"Model name","value":"Core i5-6287U","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6287U","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202499001","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JJ","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 550","unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7927-r25467","location":"Intel/core i5/i5-6287u · revision 25467 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a50be5b1f2eb2791","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7927-r25467","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-a50be5b1f2eb2791"},{"id":"cw-a51b9a4bb20136f8","name":"CN3630-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3630-600 SCP","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-600 SCP","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-600BG1521-SCP","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8230-r25889","location":"Cavium/octeon/cn3630-600bg1521-scp · revision 25889 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a51b9a4bb20136f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8230-r25889","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-a51b9a4bb20136f8"},{"id":"cw-a53f913b19cb916c","name":"Alpha 21364","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"DEC","year":2002,"process":"0.18 µm","aliases":["Compaq microarchitectures alpha 21364"],"fields":[{"key":"Architecture name","value":"Alpha 21364","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"DEC","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January 20, 2002","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":7,"unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Alpha","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Alpha 21264","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alpha 21464","unit":"","sourceId":"chipswiki-15452-r48576","location":"Compaq/microarchitectures/alpha 21364 · revision 48576 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-15. Not an independent measurement.","entityId":"cw-a53f913b19cb916c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","sourceDate":"2017-06-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15452-r48576"],"url":"https://museum.vlsi.kr/objects/cw-a53f913b19cb916c"},{"id":"cw-a542955cd8f8b5d9","name":"Ryzen 7 PRO 2700X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 pro 2700x"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 2700X","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2700X","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD27BXBAM88AF","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4913-r15850","location":"Amd/ryzen 7/pro 2700x · revision 15850 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-a542955cd8f8b5d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4913-r15850","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-a542955cd8f8b5d9"},{"id":"cw-a5597d8d49c0ff43","name":"Core M 5Y51","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y51"],"fields":[{"key":"Model name","value":"Core M 5Y51","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y51","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802061802","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2014","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2015","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR23L","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"F0","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1300000000,"unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":82,"unit":"mm²","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1234","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"MiB","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7813-r25262","location":"Intel/core m/5y51 · revision 25262 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5597d8d49c0ff43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7813-r25262"],"url":"https://museum.vlsi.kr/objects/cw-a5597d8d49c0ff43"},{"id":"cw-a585a5d13f353fb9","name":"Core i5-7200U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7200","year":2016,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7200u"],"fields":[{"key":"Model name","value":"Core i5-7200U","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7200U","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067702739739","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR342","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZU","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7200","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400 & DDR4-2667","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / type 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 4","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"type 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-278-r563","location":"Intel/core i5/i5-7200u · revision 563 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","sourceDate":"2022-07-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-24. Not an independent measurement.","entityId":"cw-a585a5d13f353fb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-278-r563","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-a585a5d13f353fb9"},{"id":"cw-a591baff6a88d382","name":"Pentium Gold G4560","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G4500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium gold g4560"],"fields":[{"key":"Model name","value":"Pentium Gold G4560","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4560","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677G4560","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677G4560","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32Y","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G4500","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7586-r24645","location":"Intel/pentium gold/g4560 · revision 24645 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-a591baff6a88d382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7586-r24645"],"url":"https://museum.vlsi.kr/objects/cw-a591baff6a88d382"},{"id":"cw-a5a601e4fb23e77d","name":"Pentium Gold 4410Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium gold 4410y"],"fields":[{"key":"Model name","value":"Pentium Gold 4410Y","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4410Y","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702740013","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34B","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":850,"unit":"MHz","sourceId":"chipswiki-4976-r16098","location":"Intel/pentium gold/4410y · revision 16098 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-a5a601e4fb23e77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4976-r16098"],"url":"https://museum.vlsi.kr/objects/cw-a5a601e4fb23e77d"},{"id":"cw-a5b4c8ec48be74d5","name":"Am186EM–25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–25kc\\w"],"fields":[{"key":"Model name","value":"Am186EM–25KC\\W","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–25KC\\W","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–25KC\\W","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14655-r44716","location":"Amd/am186ex/am186em–25kc\\w · revision 44716 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a5b4c8ec48be74d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14655-r44716"],"url":"https://museum.vlsi.kr/objects/cw-a5b4c8ec48be74d5"},{"id":"cw-a5c9d4e0d84990c4","name":"CN3830-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3830-600 NSP","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-600 NSP","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-600BG1521-NSP","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8222-r25881","location":"Cavium/octeon/cn3830-600bg1521-nsp · revision 25881 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a5c9d4e0d84990c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8222-r25881","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-a5c9d4e0d84990c4"},{"id":"cw-a5cc262156ca5dc7","name":"PEZY-SC3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"PEZY","year":2019,"process":"7 nm","aliases":["Pezy pezy-scx pezy-sc3"],"fields":[{"key":"Model name","value":"PEZY-SC3","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"PEZY","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PEZY-SC3","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Supercomputer","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2016,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2019,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PEZY-SCx","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.333,"unit":"MHz","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":700,"unit":"mm²","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8192,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":65536,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.65,"unit":"V","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR4-3600","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":4,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":4,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":8,"unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":"11.18 TiB/s","unit":"","sourceId":"chipswiki-1822-r6121","location":"Pezy/pezy-scx/pezy-sc3 · revision 6121 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2019-09-28. Not an independent measurement.","entityId":"cw-a5cc262156ca5dc7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","sourceDate":"2019-09-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1822-r6121"],"url":"https://museum.vlsi.kr/objects/cw-a5cc262156ca5dc7"},{"id":"cw-a6326cc45344bbc8","name":"Ryzen 7 5800H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 5800h"],"fields":[{"key":"Model name","value":"Ryzen 7 5800H","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5800H","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000295","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"64GB on DDR4-3200","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"32GB on LPDDR4-4266","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-545-r1123","location":"Amd/ryzen 7/5800h · revision 1123 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-a6326cc45344bbc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-545-r1123"],"url":"https://museum.vlsi.kr/objects/cw-a6326cc45344bbc8"},{"id":"cw-a63b6a026efb62c7","name":"K6-2/400AFK-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400afk-66"],"fields":[{"key":"Model name","value":"K6-2/400AFK-66","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AFK-66","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AFK-66","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8355-r26050","location":"Amd/k6-2/k6-2-400afk-66 · revision 26050 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a63b6a026efb62c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8355-r26050"],"url":"https://museum.vlsi.kr/objects/cw-a63b6a026efb62c7"},{"id":"cw-a64f57807bf73e76","name":"Am186EDLV–20KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186edlv–20kc\\w"],"fields":[{"key":"Model name","value":"Am186EDLV–20KC\\W","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EDLV–20KC\\W","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EDLV–20KC\\W","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14676-r44737","location":"Amd/am186ex/am186edlv–20kc\\w · revision 44737 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-a64f57807bf73e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14676-r44737"],"url":"https://museum.vlsi.kr/objects/cw-a64f57807bf73e76"},{"id":"cw-a67cdf21d95e9206","name":"AMD-K6/PR2-200ALR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-pr2-200alr"],"fields":[{"key":"Model name","value":"AMD-K6/PR2-200ALR","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/PR2-200ALR","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/PR2-200ALR","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 1997","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 1997","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":199.99,"unit":"MHz","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8291-r25979","location":"Amd/k6/amd-k6-pr2-200alr · revision 25979 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a67cdf21d95e9206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8291-r25979"],"url":"https://museum.vlsi.kr/objects/cw-a67cdf21d95e9206"},{"id":"cw-a6983dfa28e662cd","name":"POWER9 02AA986","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02aa986"],"fields":[{"key":"Model name","value":"02AA986","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02AA986","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02AA986","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.9,"unit":"GHz","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":80,"unit":"MiB","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x10 MiB","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3945-r12587","location":"Ibm/power/02aa986 · revision 12587 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-a6983dfa28e662cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3945-r12587"],"url":"https://museum.vlsi.kr/objects/cw-a6983dfa28e662cd"},{"id":"cw-a6b96468cf0f695e","name":"Celeron B840","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b840"],"fields":[{"key":"Model name","value":"Celeron B840","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B840","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700998301","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EN","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2011","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2011","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6924-r21610","location":"Intel/celeron/b840 · revision 21610 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-a6b96468cf0f695e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6924-r21610","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-a6b96468cf0f695e"},{"id":"cw-a734054f523d2372","name":"Core i3-7100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7100"],"fields":[{"key":"Model name","value":"Core i3-7100","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7100","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677I37100","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677I37100","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35C","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3900,"unit":"MHz","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4502-r14632","location":"Intel/core i3/i3-7100 · revision 14632 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-a734054f523d2372","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4502-r14632"],"url":"https://museum.vlsi.kr/objects/cw-a734054f523d2372"},{"id":"cw-a749c3996860994d","name":"Am486DX4-75","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-75"],"fields":[{"key":"Model name","value":"Am486DX4-75","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-75","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-75","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 1994","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":75,"unit":"MHz","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8549-r26745","location":"Amd/am486/am486dx4-75 · revision 26745 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a749c3996860994d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8549-r26745"],"url":"https://museum.vlsi.kr/objects/cw-a749c3996860994d"},{"id":"cw-a75402e1df475731","name":"Hunter","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2023,"process":"7 nm","aliases":["Arm holdings microarchitectures hunter"],"fields":[{"key":"Architecture name","value":"Hunter","unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2023,"unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A715","unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Chaberton","unit":"","sourceId":"chipswiki-305-r619","location":"Arm holdings/microarchitectures/hunter · revision 619 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-a75402e1df475731","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-305-r619"],"url":"https://museum.vlsi.kr/objects/cw-a75402e1df475731"},{"id":"cw-a756d6ed8d628fda","name":"Xeon W-3235","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3235"],"fields":[{"key":"Model name","value":"Xeon W-3235","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3235","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504152802","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFC","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1707-r5941","location":"Intel/xeon w/w-3235 · revision 5941 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-a756d6ed8d628fda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1707-r5941"],"url":"https://museum.vlsi.kr/objects/cw-a756d6ed8d628fda"},{"id":"cw-a759cd25dc10c5c0","name":"UltraSPARC-I 200MHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Sun Microsystems","series":"UltraSPARC-I","year":1996,"architecture":"UltraSPARC-I","process":"0.5 µm","aliases":["Sun microsystems ultrasparc stp1030bga-200"],"fields":[{"key":"Model name","value":"UltraSPARC-I 200MHz","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Sun Microsystems","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Texas Instruments","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"UltraSPARC-I 200MHz","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"STP103OBGA-200","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1996,"unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"UltraSPARC","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":200,"unit":"MHz","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V9","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":5200000,"unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":310,"unit":"mm²","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7637-r24894","location":"Sun microsystems/ultrasparc/stp1030bga-200 · revision 24894 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-512","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":512,"unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a759cd25dc10c5c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7637-r24894","chipswiki-31351-r92104"],"url":"https://museum.vlsi.kr/objects/cw-a759cd25dc10c5c0"},{"id":"cw-a76c4a5f36a6d700","name":"Duron 850 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron d850aut1b"],"fields":[{"key":"Model name","value":"Duron 850","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 850","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D850AUT1B","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0850AUT1B","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2001","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 8, 2001","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":850,"unit":"MHz","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":37.4,"unit":"W","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8431-r26139","location":"Amd/duron/d850aut1b · revision 26139 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a76c4a5f36a6d700","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8431-r26139"],"url":"https://museum.vlsi.kr/objects/cw-a76c4a5f36a6d700"},{"id":"cw-a78d6f6076cb144d","name":"Nehemiah","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"VIA Technologies","year":null,"process":"0.13 µm","aliases":["Via technologies microarchitectures nehemiah"],"fields":[{"key":"Architecture name","value":"Nehemiah","unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"VIA Technologies","unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.13,"unit":"µm","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":16,"unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Ezra","unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Esther","unit":"","sourceId":"chipswiki-7379-r23865","location":"Via technologies/microarchitectures/nehemiah · revision 23865 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-a78d6f6076cb144d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7379-r23865"],"url":"https://museum.vlsi.kr/objects/cw-a78d6f6076cb144d"},{"id":"cw-a7ae6ec067abf15d","name":"AMD-K5-PR100ABQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"SSA/5","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr100abq"],"fields":[{"key":"Model name","value":"AMD-K5-PR100ABQ","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR100ABQ","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR100ABQ","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 17, 1996","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 17, 1996","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"SSA/5","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":99.99,"unit":"MHz","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SSA/5","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":0,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":161,"unit":"mm²","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8404-r26100","location":"Amd/k5/amd-k5-pr100abq · revision 26100 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7ae6ec067abf15d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8404-r26100"],"url":"https://museum.vlsi.kr/objects/cw-a7ae6ec067abf15d"},{"id":"cw-a7b37de21be6685b","name":"AM9080A-2CC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2cc"],"fields":[{"key":"Model name","value":"AMD AM9080A-2CC","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2CC","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2CC","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8483-r26676","location":"Amd/am9080/am9080a-2cc · revision 26676 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7b37de21be6685b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8483-r26676"],"url":"https://museum.vlsi.kr/objects/cw-a7b37de21be6685b"},{"id":"cw-a7b6ca7a3edcd4e1","name":"AMD-K6/266BCZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Mobile K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 266bcz"],"fields":[{"key":"Model name","value":"AMD-K6/266BCZ","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/266BCZ","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/266BCZ","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1014-r2865","location":"Amd/k6/amd-k6/266bcz · revision 2865 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":360,"unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.78,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-a7b6ca7a3edcd4e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1014-r2865","chipswiki-31128-r91600"],"url":"https://museum.vlsi.kr/objects/cw-a7b6ca7a3edcd4e1"},{"id":"cw-a7c3a4367ff9416e","name":"A80286-16","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"A80286","year":1987,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 a80286-16"],"fields":[{"key":"Model name","value":"A80286-16","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A80286-16","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1987","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A80286","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":16,"unit":"MHz","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"16 MT/s","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8609-r26807","location":"Amd/am286/a80286-16 · revision 26807 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a7c3a4367ff9416e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8609-r26807"],"url":"https://museum.vlsi.kr/objects/cw-a7c3a4367ff9416e"},{"id":"cw-a7f281e04b2fa673","name":"Core i7-6820HK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6820hk"],"fields":[{"key":"Model name","value":"Core i7-6820HK","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6820HK","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202194730","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FL","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3973-r12660","location":"Intel/core i7/i7-6820hk · revision 12660 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-a7f281e04b2fa673","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3973-r12660","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-a7f281e04b2fa673"},{"id":"cw-a80ba91350f265a9","name":"Am486DX4-120SV8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4S","year":1996,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-120sv8b"],"fields":[{"key":"Model name","value":"Am486DX4-120SV8B","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-120SV8B","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-120SV8B","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1995,"unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1996","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":120,"unit":"MHz","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8551-r26747","location":"Amd/am486/am486dx4-120sv8b · revision 26747 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a80ba91350f265a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8551-r26747"],"url":"https://museum.vlsi.kr/objects/cw-a80ba91350f265a9"},{"id":"cw-a8143d0dc4af0373","name":"Zen 3","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2020,"process":"7nm, 12nm","aliases":["Amd microarchitectures zen 3"],"fields":[{"key":"Architecture name","value":"Zen 3","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 8, 2020","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7nm, 12nm","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":64,"unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":19,"unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Zen 2","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Zen 4","unit":"","sourceId":"chipswiki-76-r97029","location":"Amd/microarchitectures/zen 3 · revision 97029 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. Not an independent measurement.","entityId":"cw-a8143d0dc4af0373","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-76-r97029"],"url":"https://museum.vlsi.kr/objects/cw-a8143d0dc4af0373"},{"id":"cw-a814d164748d6429","name":"Xeon Gold 5218B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5218b"],"fields":[{"key":"Model name","value":"Xeon Gold 5218B","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5218B","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504295701","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFDJ","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1524-r4976","location":"Intel/xeon gold/5218b · revision 4976 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a814d164748d6429","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1524-r4976"],"url":"https://museum.vlsi.kr/objects/cw-a814d164748d6429"},{"id":"cw-a815bc670ad57494","name":"N80286-16","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80286","year":1987,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 n80286-16"],"fields":[{"key":"Model name","value":"N80286-16","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80286-16","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1987","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80286","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":16,"unit":"MHz","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"16 MT/s","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8597-r26795","location":"Amd/am286/n80286-16 · revision 26795 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a815bc670ad57494","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8597-r26795"],"url":"https://museum.vlsi.kr/objects/cw-a815bc670ad57494"},{"id":"cw-a8261280e3259ed3","name":"Core i5-2415M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2415m"],"fields":[{"key":"Model name","value":"Core i5-2415M","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2415M","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085700","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR071","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-1442-r4880","location":"Intel/core i5/i5-2415m · revision 4880 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-a8261280e3259ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1442-r4880","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-a8261280e3259ed3"},{"id":"cw-a84aa73b43bcc20b","name":"Xeon D-1543N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2017,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1543n"],"fields":[{"key":"Model name","value":"Xeon D-1543N","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1543N","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068203255107","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KW","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2017","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3725-r11420","location":"Intel/xeon d/d-1543n · revision 11420 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-a84aa73b43bcc20b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3725-r11420"],"url":"https://museum.vlsi.kr/objects/cw-a84aa73b43bcc20b"},{"id":"cw-a8aef62c97e0004d","name":"Godson-2F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2008,"architecture":"GS464","process":"90 nm","aliases":["Loongson godson 2 2f"],"fields":[{"key":"Model name","value":"Godson-2F","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2F","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PLA80","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 31, 2007","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2008","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":51000000,"unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HFCBGA-452","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"HFCBGA","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-452","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-667","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":9.934,"unit":"GiB/s","sourceId":"chipswiki-7679-r24974","location":"Loongson/godson 2/2f · revision 24974 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a8aef62c97e0004d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7679-r24974"],"url":"https://museum.vlsi.kr/objects/cw-a8aef62c97e0004d"},{"id":"cw-a8ba9c6a1d03bc93","name":"Celeron G3930E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G3900E","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron g3930e"],"fields":[{"key":"Model name","value":"Celeron G3930E","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3930E","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067703318802","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38G","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G3900E","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6433-r20117","location":"Intel/celeron/g3930e · revision 20117 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-a8ba9c6a1d03bc93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6433-r20117"],"url":"https://museum.vlsi.kr/objects/cw-a8ba9c6a1d03bc93"},{"id":"cw-a8e13d7c0311f0fd","name":"EPYC 7402P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7402p"],"fields":[{"key":"Model name","value":"EPYC 7402P","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7402P","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000048","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000048WOF","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-860-r2240","location":"Amd/epyc/7402p · revision 2240 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-a8e13d7c0311f0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-860-r2240"],"url":"https://museum.vlsi.kr/objects/cw-a8e13d7c0311f0fd"},{"id":"cw-a8e140e12d41dac5","name":"Coffee Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2017,"process":"14 nm","aliases":["Intel microarchitectures coffee lake"],"fields":[{"key":"Architecture name","value":"Coffee Lake","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 5, 2017","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake U","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake E","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Kaby Lake","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Comet Lake","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Ice Lake","unit":"","sourceId":"chipswiki-895-r2347","location":"Intel/microarchitectures/coffee lake · revision 2347 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-a8e140e12d41dac5","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-895-r2347"],"url":"https://museum.vlsi.kr/objects/cw-a8e140e12d41dac5"},{"id":"cw-a91521a6478826b4","name":"X704-533","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Exponential Technology","year":null,"architecture":"X704","process":"500 nm","aliases":["Exponential technology x704 533"],"fields":[{"key":"Model name","value":"X704-533","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Exponential Technology","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Hitachi","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"X704-533","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 1997","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X704","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":533,"unit":"MHz","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"60x bus","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"X704","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"CHRP","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2700000,"unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"BiCMOS","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":150,"unit":"mm²","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.6,"unit":"V","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-359","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-359","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"KiB","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"KiB","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"KiB","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8109-r25768","location":"Exponential technology/x704/533 · revision 25768 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a91521a6478826b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8109-r25768"],"url":"https://museum.vlsi.kr/objects/cw-a91521a6478826b4"},{"id":"cw-a923805e27ff3f80","name":"Airmont","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2015,"process":"14 nm","aliases":["Intel microarchitectures airmont"],"fields":[{"key":"Architecture name","value":"Airmont","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2015,"unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"2 Cores","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"2 Cores","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Silvermont","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Goldmont","unit":"","sourceId":"chipswiki-8768-r27240","location":"Intel/microarchitectures/airmont · revision 27240 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a923805e27ff3f80","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8768-r27240"],"url":"https://museum.vlsi.kr/objects/cw-a923805e27ff3f80"},{"id":"cw-a93f29f53273ea35","name":"Duron 550 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d550aut1b"],"fields":[{"key":"Model name","value":"Duron 550","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 550","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D550AUT1B","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0550AUT1B","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25.4,"unit":"W","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8443-r26151","location":"Amd/duron/d550aut1b · revision 26151 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a93f29f53273ea35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8443-r26151"],"url":"https://museum.vlsi.kr/objects/cw-a93f29f53273ea35"},{"id":"cw-a98054a11ec0ee52","name":"Xeon Platinum 8160M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8160m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8160M","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8160M","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303406600","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B8","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2559-r8826","location":"Intel/xeon platinum/8160m · revision 8826 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-a98054a11ec0ee52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2559-r8826"],"url":"https://museum.vlsi.kr/objects/cw-a98054a11ec0ee52"},{"id":"cw-a9a09c665453601a","name":"Excavator","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2015,"process":"28 nm","aliases":["Amd microarchitectures excavator"],"fields":[{"key":"Architecture name","value":"Excavator","unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2015,"unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Steamroller","unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Zen","unit":"","sourceId":"chipswiki-5201-r17060","location":"Amd/microarchitectures/excavator · revision 17060 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-20. Not an independent measurement.","entityId":"cw-a9a09c665453601a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","sourceDate":"2018-07-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5201-r17060"],"url":"https://museum.vlsi.kr/objects/cw-a9a09c665453601a"},{"id":"cw-a9aca32a0d966c7c","name":"Core i5-430UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-400","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-430um"],"fields":[{"key":"Model name","value":"Intel Core i5-430UM","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-430UM","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006042AE","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2010","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2010","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-400","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1199.99,"unit":"MHz","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1733.33,"unit":"MHz","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBVS","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7943-r25490","location":"Intel/core i5/i5-430um · revision 25490 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9aca32a0d966c7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7943-r25490","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-a9aca32a0d966c7c"},{"id":"cw-a9b21dbe07aa0a15","name":"CN5840-800 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-800bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5840-800 NSP","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-800 NSP","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-800BG1521-NSP","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8142-r25801","location":"Cavium/octeon plus/cn5840-800bg1521-nsp · revision 25801 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9b21dbe07aa0a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8142-r25801","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-a9b21dbe07aa0a15"},{"id":"cw-a9bfadcf9f4a36f0","name":"AMD-SSA/5-90ABQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"SSA/5","year":1996,"architecture":"K5","process":"500 nm","aliases":["Amd k5 amd-ssa-5-90abq"],"fields":[{"key":"Model name","value":"AMD-SSA/5-90ABQ","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-SSA/5-90ABQ","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-SSA/5-90ABQ","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1996,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 27, 1996","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"SSA/5","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":90,"unit":"MHz","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"60 MT/s","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SSA/5","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":0,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":251,"unit":"mm²","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8390-r26086","location":"Amd/k5/amd-ssa-5-90abq · revision 26086 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9bfadcf9f4a36f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8390-r26086"],"url":"https://museum.vlsi.kr/objects/cw-a9bfadcf9f4a36f0"},{"id":"cw-a9cfc67fa5762ee3","name":"Chivano","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"90 nm","aliases":["Intel microarchitectures chivano"],"fields":[{"key":"Architecture name","value":"Chivano","unit":"","sourceId":"chipswiki-8761-r27223","location":"Intel/microarchitectures/chivano · revision 27223 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a9cfc67fa5762ee3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8761-r27223","location":"Intel/microarchitectures/chivano · revision 27223 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a9cfc67fa5762ee3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8761-r27223","location":"Intel/microarchitectures/chivano · revision 27223 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a9cfc67fa5762ee3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8761-r27223","location":"Intel/microarchitectures/chivano · revision 27223 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a9cfc67fa5762ee3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8761-r27223","location":"Intel/microarchitectures/chivano · revision 27223 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a9cfc67fa5762ee3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Montecito","unit":"","sourceId":"chipswiki-8761-r27223","location":"Intel/microarchitectures/chivano · revision 27223 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-a9cfc67fa5762ee3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8761-r27223"],"url":"https://museum.vlsi.kr/objects/cw-a9cfc67fa5762ee3"},{"id":"cw-a9d08d76fadd6d97","name":"Alchemy Au1500-333MBI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1500-333mbi"],"fields":[{"key":"Model name","value":"Alchemy Au1500-333MBI","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-333MBI","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1500-333MBI","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2001","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AB","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AC","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AD","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-481-r965","location":"Alchemy/au1500-333mbi · revision 965 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-a9d08d76fadd6d97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-481-r965"],"url":"https://museum.vlsi.kr/objects/cw-a9d08d76fadd6d97"},{"id":"cw-a9ecd32765eba862","name":"AMD-K6/PR2-166ALR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-pr2-166alr"],"fields":[{"key":"Model name","value":"AMD-K6/PR2-166ALR","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/PR2-166ALR","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/PR2-166ALR","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 1997","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 1997","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":166.66,"unit":"MHz","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8292-r25980","location":"Amd/k6/amd-k6-pr2-166alr · revision 25980 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-a9ecd32765eba862","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8292-r25980"],"url":"https://museum.vlsi.kr/objects/cw-a9ecd32765eba862"},{"id":"cw-aa19dd9185ca2f52","name":"Core i7-8670","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i7 i7-8670"],"fields":[{"key":"Model name","value":"Core i7-8670","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8670","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-4961-r16054","location":"Intel/core i7/i7-8670 · revision 16054 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-aa19dd9185ca2f52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4961-r16054"],"url":"https://museum.vlsi.kr/objects/cw-aa19dd9185ca2f52"},{"id":"cw-aa42704c877eb3a4","name":"Xeon Platinum 8276L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8276l"],"fields":[{"key":"Model name","value":"Xeon Platinum 8276L","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8276L","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504195301","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF97","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4.5 TiB","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1457-r4904","location":"Intel/xeon platinum/8276l · revision 4904 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-aa42704c877eb3a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1457-r4904"],"url":"https://museum.vlsi.kr/objects/cw-aa42704c877eb3a4"},{"id":"cw-aa47ea9fd8f43992","name":"MLU100","kind":"sku","entityType":"product-model","subtype":"sku","company":"Cambricon","year":2018,"aliases":["Cambricon mlu mlu100"],"fields":[{"key":"Model name","value":"MLU100","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cambricon","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MLU100","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 7, 2017","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 3, 2018","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MLU","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1300,"unit":"MHz","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MLUv100","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-3040-r10166","location":"Cambricon/mlu/mlu100 · revision 10166 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-21. Not an independent measurement.","entityId":"cw-aa47ea9fd8f43992","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3040-r10166"],"url":"https://museum.vlsi.kr/objects/cw-aa47ea9fd8f43992"},{"id":"cw-aa86e54448d7fdb8","name":"CN3630-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3630-600 EXP","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-600 EXP","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-600BG1521-EXP","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8232-r25891","location":"Cavium/octeon/cn3630-600bg1521-exp · revision 25891 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa86e54448d7fdb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8232-r25891","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-aa86e54448d7fdb8"},{"id":"cw-aa8e06a49051f59c","name":"Atom x3-C3130","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"C3000","year":2015,"architecture":"Silvermont","process":"28 nm","aliases":["Intel atom x3 x3-c3130"],"fields":[{"key":"Model name","value":"Atom x3-C3130","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x3-C3130","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x3","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C3000","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Silvermont","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SoFIA","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SoFIA","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1024,"unit":"MB","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8050-r25686","location":"Intel/atom x3/x3-c3130 · revision 25686 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aa8e06a49051f59c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8050-r25686"],"url":"https://museum.vlsi.kr/objects/cw-aa8e06a49051f59c"},{"id":"cw-aa9c2208c4ad9960","name":"Myriad 1 MA1101","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","series":"1","year":2010,"architecture":"LEON3","process":"65 nm","aliases":["Movidius myriad ma1101"],"fields":[{"key":"Model name","value":"Myriad 1 MA1101","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MA1101","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2009,"unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2010,"unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Myriad","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":1,"unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"TSMC","unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-6954-r21696","location":"Movidius/myriad/ma1101 · revision 21696 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-aa9c2208c4ad9960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6954-r21696"],"url":"https://museum.vlsi.kr/objects/cw-aa9c2208c4ad9960"},{"id":"cw-aad01db5881a382f","name":"Celeron J3160","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J3000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron j3160"],"fields":[{"key":"Model name","value":"Intel Celeron J3160","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J3160","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715935","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KS","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J3000","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2240,"unit":"MHz","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6859-r21412","location":"Intel/celeron/j3160 · revision 21412 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-aad01db5881a382f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6859-r21412"],"url":"https://museum.vlsi.kr/objects/cw-aad01db5881a382f"},{"id":"cw-ab18374542c6e4a5","name":"Xeon Bronze 3106","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon bronze 3106"],"fields":[{"key":"Model name","value":"Xeon Bronze 3106","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3106,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806733106","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303561900","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GL","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Bronze","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-1532-r4988","location":"Intel/xeon bronze/3106 · revision 4988 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ab18374542c6e4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1532-r4988"],"url":"https://museum.vlsi.kr/objects/cw-ab18374542c6e4a5"},{"id":"cw-ab1ac97efc59a236","name":"Core M3-8114Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M3-8000","year":null,"architecture":"Cannon Lake","process":"10 nm","aliases":["Intel core m m3-8114y"],"fields":[{"key":"Model name","value":"M3-8114Y","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M3-8114Y","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M3","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M3-8000","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cannon Lake","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cannon Lake Y","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics ?","unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1191-r3729","location":"Intel/core m/m3-8114y · revision 3729 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-17. Not an independent measurement.","entityId":"cw-ab1ac97efc59a236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","sourceDate":"2020-04-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1191-r3729"],"url":"https://museum.vlsi.kr/objects/cw-ab1ac97efc59a236"},{"id":"cw-ab6f4c4288e4ef5e","name":"CN3850-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3850-600 EXP","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-600 EXP","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3850-600BG1521-EXP","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8205-r25864","location":"Cavium/octeon/cn3850-600bg1521-exp · revision 25864 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ab6f4c4288e4ef5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8205-r25864","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-ab6f4c4288e4ef5e"},{"id":"cw-ab76980b25d34a64","name":"EPYC 7343","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7343"],"fields":[{"key":"Model name","value":"EPYC 7343","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7343,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000338","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000338WOF","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-730-r1751","location":"Amd/epyc/7343 · revision 1751 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-ab76980b25d34a64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-730-r1751"],"url":"https://museum.vlsi.kr/objects/cw-ab76980b25d34a64"},{"id":"cw-ab9a8c226590bccf","name":"Dimensity 1000L","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","year":2020,"architecture":"Cortex-A77","process":"7 nm","aliases":["Mediatek dimensity 1000l"],"fields":[{"key":"Model name","value":"Dimensity 1000L","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"1000L","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6885Z","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 26, 2019","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2020,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Dimensity","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2-A","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A77","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A77","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":29.87,"unit":"GiB/s","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G77","unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":9,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1100-r3258","location":"Mediatek/dimensity/1000l · revision 3258 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ab9a8c226590bccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1100-r3258"],"url":"https://museum.vlsi.kr/objects/cw-ab9a8c226590bccf"},{"id":"cw-aba3044cf61b3bba","name":"Alchemy Au1100-333MBF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-333mbf"],"fields":[{"key":"Model name","value":"Alchemy Au1100-333MBF","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-333MBF","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBFBA","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBFBC","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBFBD","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBFBE","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBFBF","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BA","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BC","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BD","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BE","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BF","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.22,"unit":"V","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-473-r954","location":"Alchemy/au1100-333mbf · revision 954 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-aba3044cf61b3bba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-473-r954"],"url":"https://museum.vlsi.kr/objects/cw-aba3044cf61b3bba"},{"id":"cw-abae1f1f4714f4a6","name":"Cell Broadband Engine Architecture","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":null,"process":"90 nm","aliases":["Ibm microarchitectures cbea"],"fields":[{"key":"Architecture name","value":"CBEA","unit":"","sourceId":"chipswiki-8752-r27150","location":"Ibm/microarchitectures/cbea · revision 27150 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-07. Not an independent measurement.","entityId":"cw-abae1f1f4714f4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fcbea&oldid=27150","sourceDate":"2017-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-8752-r27150","location":"Ibm/microarchitectures/cbea · revision 27150 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-07. Not an independent measurement.","entityId":"cw-abae1f1f4714f4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fcbea&oldid=27150","sourceDate":"2017-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8752-r27150","location":"Ibm/microarchitectures/cbea · revision 27150 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-07. Not an independent measurement.","entityId":"cw-abae1f1f4714f4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fcbea&oldid=27150","sourceDate":"2017-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8752-r27150","location":"Ibm/microarchitectures/cbea · revision 27150 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-07. Not an independent measurement.","entityId":"cw-abae1f1f4714f4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fcbea&oldid=27150","sourceDate":"2017-12-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8752-r27150"],"url":"https://museum.vlsi.kr/objects/cw-abae1f1f4714f4a6"},{"id":"cw-abc166af45bc9137","name":"K6-2/400AHX-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400ahx-66"],"fields":[{"key":"Model name","value":"K6-2/400AHX-66","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AHX-66","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AHX-66","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.4,"unit":"V","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8349-r26044","location":"Amd/k6-2/k6-2-400ahx-66 · revision 26044 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-abc166af45bc9137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8349-r26044"],"url":"https://museum.vlsi.kr/objects/cw-abc166af45bc9137"},{"id":"cw-ac0946237bbc7fa6","name":"Pentium J3710","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J3000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel pentium (2009) j3710"],"fields":[{"key":"Model name","value":"Intel Pentium J3710","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J3710","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715927","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KQ","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 10, 2016","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 10, 2016","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J3000","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2640,"unit":"MHz","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6.5,"unit":"W","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6860-r21413","location":"Intel/pentium (2009)/j3710 · revision 21413 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-ac0946237bbc7fa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6860-r21413"],"url":"https://museum.vlsi.kr/objects/cw-ac0946237bbc7fa6"},{"id":"cw-ac278e00f4adbc28","name":"Ryzen 5 4600GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 4600ge"],"fields":[{"key":"Model name","value":"Ryzen 5 4600GE","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4600GE","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000150","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-181-r351","location":"Amd/ryzen 5/4600ge · revision 351 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-29. Not an independent measurement.","entityId":"cw-ac278e00f4adbc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","sourceDate":"2022-09-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-181-r351"],"url":"https://museum.vlsi.kr/objects/cw-ac278e00f4adbc28"},{"id":"cw-ac4d41b3749876dd","name":"EPYC 7F52","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7f52"],"fields":[{"key":"Model name","value":"EPYC 7F52","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7F52","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000140","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000140WOF","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 14, 2020","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 14, 2020","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x16 MiB","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-1195-r3737","location":"Amd/epyc/7f52 · revision 3737 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-ac4d41b3749876dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1195-r3737"],"url":"https://museum.vlsi.kr/objects/cw-ac4d41b3749876dd"},{"id":"cw-ac56fdfeb7308bab","name":"ID8086-2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"ID8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 id8086-2"],"fields":[{"key":"Model name","value":"AMD ID8086-2","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"ID8086-2","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"ID8086-2","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"ID8086","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8511-r26704","location":"Amd/am8086/id8086-2 · revision 26704 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac56fdfeb7308bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8511-r26704"],"url":"https://museum.vlsi.kr/objects/cw-ac56fdfeb7308bab"},{"id":"cw-ac6652e045fb065c","name":"Atom C3958","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3958"],"fields":[{"key":"Model name","value":"Atom C3958","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3958","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502444202","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR381","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":31,"unit":"W","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x24 KiB","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1863-r6399","location":"Intel/atom/c3958 · revision 6399 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-ac6652e045fb065c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1863-r6399","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-ac6652e045fb065c"},{"id":"cw-ac80d1f2861f8e16","name":"CN5840-1000 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-1000bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5840-1000 NSP","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-1000 NSP","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-1000BG1521-NSP","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8148-r25807","location":"Cavium/octeon plus/cn5840-1000bg1521-nsp · revision 25807 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ac80d1f2861f8e16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8148-r25807","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-ac80d1f2861f8e16"},{"id":"cw-acc88f7183c80835","name":"Core i7-6970HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6970hq"],"fields":[{"key":"Model name","value":"Core i7-6970HQ","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6970HQ","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QW","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics 580","unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7833-r25323","location":"Intel/core i7/i7-6970hq · revision 25323 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acc88f7183c80835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7833-r25323","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-acc88f7183c80835"},{"id":"cw-acd640f16f538cbe","name":"Core i7-4850EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4850eq"],"fields":[{"key":"Model name","value":"Intel Core i7-4850EQ","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4850EQ","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701528402","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 20, 2014","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 20, 2014","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR17X","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7868-r25371","location":"Intel/core i7/i7-4850eq · revision 25371 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acd640f16f538cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7868-r25371","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-acd640f16f538cbe"},{"id":"cw-acef8431b79fe589","name":"CN5840-1000 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-1000bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5840-1000 SCP","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-1000 SCP","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-1000BG1521-SCP","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8147-r25806","location":"Cavium/octeon plus/cn5840-1000bg1521-scp · revision 25806 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-acef8431b79fe589","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8147-r25806","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-acef8431b79fe589"},{"id":"cw-acf080ae2f5781bd","name":"Kunpeng 920-6426","kind":"sku","entityType":"product-model","subtype":"cpu","company":"HiSilicon","series":"920","year":2019,"architecture":"TaiShan v110","aliases":["Hisilicon kunpeng 920-6426"],"fields":[{"key":"Model name","value":"Kunpeng 920-6426","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"920-6426","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2018","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2019","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Hi16xx","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":920,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"TaiShan v110","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"TaiShan v110","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":20000000000,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":195,"unit":"W","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":4,"unit":"MiB","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x64 KiB","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":4,"unit":"MiB","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x64 KiB","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64x512 KiB","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"64x1 MiB","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-1291-r4315","location":"Hisilicon/kunpeng/920-6426 · revision 4315 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-acf080ae2f5781bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1291-r4315"],"url":"https://museum.vlsi.kr/objects/cw-acf080ae2f5781bd"},{"id":"cw-ad2c537a254dbdc9","name":"K6-2+/475ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2+-475acz"],"fields":[{"key":"Model name","value":"K6-2+/475ACZ","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2+/475ACZ","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2+/475ACZ","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":475,"unit":"MHz","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16,"unit":"W","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Mobile","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-994-r2840","location":"Amd/k6-2+/k6-2+-475acz · revision 2840 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-ad2c537a254dbdc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-994-r2840","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-ad2c537a254dbdc9"},{"id":"cw-ad688a700d2bdd87","name":"Core i5-8300H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8300h"],"fields":[{"key":"Model name","value":"Core i5-8300H","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8300H","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068403373522","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3Z0","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6578-r20845","location":"Intel/core i5/i5-8300h · revision 20845 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-ad688a700d2bdd87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6578-r20845","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ad688a700d2bdd87"},{"id":"cw-ad7c6dd1a54277c3","name":"Exynos 3110","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 3","year":2010,"architecture":"Cortex-A8","process":"45 nm","aliases":["Samsung exynos 3110"],"fields":[{"key":"Model name","value":"Exynos 3110","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3110,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 23, 2010","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 23, 2010","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 3","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AXI","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A8","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A8","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FBGA","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FBGA","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR2-400","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX540","unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":1,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-6856-r21392","location":"Samsung/exynos/3110 · revision 21392 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-ad7c6dd1a54277c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6856-r21392"],"url":"https://museum.vlsi.kr/objects/cw-ad7c6dd1a54277c3"},{"id":"cw-adb1b8ccb034adc1","name":"Hi1610","kind":"sku","entityType":"product-model","subtype":"cpu","company":"HiSilicon","year":2015,"architecture":"Cortex-A57","process":"16 nm","aliases":["Hisilicon kunpeng hi1610"],"fields":[{"key":"Model name","value":"Hi1610","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Hi1610","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2015,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2015,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Hi16xx","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","alternatives":[{"value":"256 GiB","sourceId":"chipswiki-2171-r7280","reason":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x48 KiB","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-2171-r7280","location":"Hisilicon/kunpeng/hi1610 · revision 7280 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-17. Not an independent measurement.","entityId":"cw-adb1b8ccb034adc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","sourceDate":"2019-07-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2171-r7280"],"url":"https://museum.vlsi.kr/objects/cw-adb1b8ccb034adc1"},{"id":"cw-ae0a40b28bc3f5da","name":"Cortex-A15","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2010,"aliases":["Arm holdings microarchitectures cortex-a15"],"fields":[{"key":"Architecture name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 8, 2010","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A9","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A57","unit":"","sourceId":"chipswiki-4146-r13211","location":"Arm holdings/microarchitectures/cortex-a15 · revision 13211 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-ae0a40b28bc3f5da","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4146-r13211"],"url":"https://museum.vlsi.kr/objects/cw-ae0a40b28bc3f5da"},{"id":"cw-ae232b72d805405d","name":"Alchemy Au1550-333MBF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-333mbf"],"fields":[{"key":"Model name","value":"Alchemy Au1550-333MBF","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-333MBF","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-333MBFAA","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1350 mW","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-465-r946","location":"Alchemy/au1550-333mbf · revision 946 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ae232b72d805405d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-465-r946"],"url":"https://museum.vlsi.kr/objects/cw-ae232b72d805405d"},{"id":"cw-ae5cdc72ecf812e7","name":"Ryzen 3 PRO 5350G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 3 pro 5350g"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 5350G","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5350G","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000256","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2021","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-612-r1434","location":"Amd/ryzen 3/pro 5350g · revision 1434 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-ae5cdc72ecf812e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-612-r1434"],"url":"https://museum.vlsi.kr/objects/cw-ae5cdc72ecf812e7"},{"id":"cw-ae72fdd53d230c64","name":"Navi","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2018,"process":"7 nm","aliases":["Amd microarchitectures navi"],"fields":[{"key":"Architecture name","value":"Navi","unit":"","sourceId":"chipswiki-2222-r7535","location":"Amd/microarchitectures/navi · revision 7535 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-18. Not an independent measurement.","entityId":"cw-ae72fdd53d230c64","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","sourceDate":"2019-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2222-r7535","location":"Amd/microarchitectures/navi · revision 7535 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-18. Not an independent measurement.","entityId":"cw-ae72fdd53d230c64","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","sourceDate":"2019-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2222-r7535","location":"Amd/microarchitectures/navi · revision 7535 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-18. Not an independent measurement.","entityId":"cw-ae72fdd53d230c64","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","sourceDate":"2019-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-2222-r7535","location":"Amd/microarchitectures/navi · revision 7535 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-18. Not an independent measurement.","entityId":"cw-ae72fdd53d230c64","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","sourceDate":"2019-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-2222-r7535","location":"Amd/microarchitectures/navi · revision 7535 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-18. Not an independent measurement.","entityId":"cw-ae72fdd53d230c64","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","sourceDate":"2019-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Vega","unit":"","sourceId":"chipswiki-2222-r7535","location":"Amd/microarchitectures/navi · revision 7535 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-18. Not an independent measurement.","entityId":"cw-ae72fdd53d230c64","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","sourceDate":"2019-06-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2222-r7535"],"url":"https://museum.vlsi.kr/objects/cw-ae72fdd53d230c64"},{"id":"cw-ae8593bcf2312845","name":"AMD-K5-PR120ABR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr120abr"],"fields":[{"key":"Model name","value":"AMD-K5-PR120ABR","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR120ABR","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR120ABR","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":90,"unit":"MHz","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"60 MT/s","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8401-r26097","location":"Amd/k5/amd-k5-pr120abr · revision 26097 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ae8593bcf2312845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8401-r26097"],"url":"https://museum.vlsi.kr/objects/cw-ae8593bcf2312845"},{"id":"cw-ae898a08f19f4dc6","name":"EPYC Embedded 3451","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3451"],"fields":[{"key":"Model name","value":"EPYC Embedded 3451","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3451,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3451BMQGAAF","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2150,"unit":"MHz","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9600000000,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 64 KiB","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 8 MiB","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"85.33 GB/s","unit":"","sourceId":"chipswiki-403-r873","location":"Amd/epyc embedded/3451 · revision 873 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-ae898a08f19f4dc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-403-r873","chipswiki-31097-r91556"],"url":"https://museum.vlsi.kr/objects/cw-ae898a08f19f4dc6"},{"id":"cw-aed44fb096f92a2f","name":"Xeon E-2124","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2124"],"fields":[{"key":"Model name","value":"Xeon E-2124","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2124","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403654414","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3WQ","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake E","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","alternatives":[{"value":"128 GiB","sourceId":"chipswiki-1697-r5910","reason":"Intel/xeon e/e-2124 · revision 5910 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":71,"unit":"W","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1697-r5910","location":"Intel/xeon e/e-2124 · revision 5910 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-11. Not an independent measurement.","entityId":"cw-aed44fb096f92a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","sourceDate":"2019-10-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1697-r5910"],"url":"https://museum.vlsi.kr/objects/cw-aed44fb096f92a2f"},{"id":"cw-aed57f4b38a00707","name":"Xeon E5-4660 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4660 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4660 v4","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4660 v4","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002062605","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SD","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":40,"unit":"MiB","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x2.5 MiB","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7710-r25081","location":"Intel/xeon e5/e5-4660 v4 · revision 25081 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-aed57f4b38a00707","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7710-r25081"],"url":"https://museum.vlsi.kr/objects/cw-aed57f4b38a00707"},{"id":"cw-af0273e3534ae849","name":"CN3110-300 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-300bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3110-300 CP","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-300 CP","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-300BG868-CP","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8269-r25929","location":"Cavium/octeon/cn3110-300bg868-cp · revision 25929 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af0273e3534ae849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8269-r25929","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-af0273e3534ae849"},{"id":"cw-af1b441b82d87dbf","name":"Xeon E3-1280 v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v6","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1280 v6"],"fields":[{"key":"Model name","value":"Xeon E3-1280 v6","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1280 v6","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067702870647","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677E31280V6","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR325","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v6","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake DT","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":72,"unit":"W","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1866","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7763-r25151","location":"Intel/xeon e3/e3-1280 v6 · revision 25151 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af1b441b82d87dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7763-r25151"],"url":"https://museum.vlsi.kr/objects/cw-af1b441b82d87dbf"},{"id":"cw-af26dafdfe5659c9","name":"Cortex-X1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2020,"process":"10 nm","aliases":["Arm holdings microarchitectures cortex-x1"],"fields":[{"key":"Architecture name","value":"Cortex-X1","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 26, 2020","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":13,"unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-X2","unit":"","sourceId":"chipswiki-303-r617","location":"Arm holdings/microarchitectures/cortex-x1 · revision 617 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-af26dafdfe5659c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-303-r617"],"url":"https://museum.vlsi.kr/objects/cw-af26dafdfe5659c9"},{"id":"cw-af44e1c2e67bc702","name":"Exynos M4","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Samsung","year":2019,"process":"8 nm","aliases":["Samsung microarchitectures m4"],"fields":[{"key":"Architecture name","value":"Cheetah","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"nm","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":16,"unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"6-way","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"M3","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"M5","unit":"","sourceId":"chipswiki-984-r2794","location":"Samsung/microarchitectures/m4 · revision 2794 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-10. Not an independent measurement.","entityId":"cw-af44e1c2e67bc702","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","sourceDate":"2020-08-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-984-r2794"],"url":"https://museum.vlsi.kr/objects/cw-af44e1c2e67bc702"},{"id":"cw-af684d0abaebd888","name":"Xeon D-2141I","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2141i"],"fields":[{"key":"Model name","value":"Xeon D-2141I","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2141I","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303784100","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZV","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7159-r22597","location":"Intel/xeon d/d-2141i · revision 22597 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-af684d0abaebd888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7159-r22597","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-af684d0abaebd888"},{"id":"cw-af68ad729e4f646d","name":"QorIQ P1025","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":null,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1025"],"fields":[{"key":"Model name","value":"QorIQ P1025","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1025","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8094-r25753","location":"Freescale/qoriq/p1025 · revision 25753 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-561","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":561,"unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-af68ad729e4f646d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8094-r25753","chipswiki-31376-r92171"],"url":"https://museum.vlsi.kr/objects/cw-af68ad729e4f646d"},{"id":"cw-afa305551f5c052a","name":"Am486SX2-50","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SX2","year":1994,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486sx2-50"],"fields":[{"key":"Model name","value":"Am486SX2-50","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486SX2-50","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX2-50","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 1994","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SX2","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX2","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8537-r26733","location":"Amd/am486/am486sx2-50 · revision 26733 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa305551f5c052a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8537-r26733"],"url":"https://museum.vlsi.kr/objects/cw-afa305551f5c052a"},{"id":"cw-afa83a13dbbcd657","name":"8086-2/BQA","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 8086-2-bqa"],"fields":[{"key":"Model name","value":"8086-2/BQA","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8086-2/BQA","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"8086-2/BQA","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M8086","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8520-r26713","location":"Amd/am8086/8086-2-bqa · revision 26713 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-afa83a13dbbcd657","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8520-r26713"],"url":"https://museum.vlsi.kr/objects/cw-afa83a13dbbcd657"},{"id":"cw-afedce47b6306f69","name":"Celeron N3160","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron n3160"],"fields":[{"key":"Model name","value":"Intel Celeron N3160","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3160","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715928","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KP","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2240,"unit":"MHz","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4,"unit":"W","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6865-r21424","location":"Intel/celeron/n3160 · revision 21424 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-afedce47b6306f69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6865-r21424"],"url":"https://museum.vlsi.kr/objects/cw-afedce47b6306f69"},{"id":"cw-affb9a4bc9f101e1","name":"i486SX-25","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SX","year":1991,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486sx-25"],"fields":[{"key":"Model name","value":"Intel i486SX-25","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SX-25","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX-25","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SX-25","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SB80486SX-25","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FA80486SX-25","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 16, 1991","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SX","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX411","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX468","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX514","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX586","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX673","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX676","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX683","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX763","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX779","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX788","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 10","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 10","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 10","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX792","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 11","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 11","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 11","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX800","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 12","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 12","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 12","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX852","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 13","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 13","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 13","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX934","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 14","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 14","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 14","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX679","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 15","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 15","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 15","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX693","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 16","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 16","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 16","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX719","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 17","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 17","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 17","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX790","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 18","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 18","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 18","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX798","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 19","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 19","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 19","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX826","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 20","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 20","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 20","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX838","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 21","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 21","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 21","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX846","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 22","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 22","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 22","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX903","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 23","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 23","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 23","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX930","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / s-spec 24","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 24","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"s-spec 24","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1185000,"unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8079-r25730","location":"Intel/80486/486sx-25 · revision 25730 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-affb9a4bc9f101e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8079-r25730"],"url":"https://museum.vlsi.kr/objects/cw-affb9a4bc9f101e1"},{"id":"cw-b04f84f781ab5e36","name":"Celeron 847E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 847e"],"fields":[{"key":"Model name","value":"Celeron 847E","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"847E","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700849902","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0BU","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6938-r21625","location":"Intel/celeron/847e · revision 21625 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b04f84f781ab5e36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6938-r21625","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-b04f84f781ab5e36"},{"id":"cw-b050a641e3caa5ec","name":"EPYC 7401","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7401"],"fields":[{"key":"Model name","value":"EPYC 7401","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7401,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7401BEVHCAF","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2.25,"unit":"MiB","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x64 KiB","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5073-r16545","location":"Amd/epyc/7401 · revision 16545 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b050a641e3caa5ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5073-r16545","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-b050a641e3caa5ec"},{"id":"cw-b05116047daa8af0","name":"X-Gene 2 APM883408-X2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AppliedMicro","series":"X-Gene 2","year":2015,"architecture":"Shadowcat","process":"28 nm","aliases":["Apm x-gene apm883408-x2"],"fields":[{"key":"Model name","value":"APM883408-X2","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"APM883408-X2","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2014","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2015","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X-Gene","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"X-Gene 2","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Shadowcat","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1866","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-4758-r15344","location":"Apm/x-gene/apm883408-x2 · revision 15344 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-b05116047daa8af0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4758-r15344"],"url":"https://museum.vlsi.kr/objects/cw-b05116047daa8af0"},{"id":"cw-b05db4457cde7e62","name":"Surge S1","kind":"sku","entityType":"product-model","subtype":"soc","company":"Xiaomi","year":null,"architecture":"Cortex-A53","process":"28 nm","aliases":["Xiaomi surge s1"],"fields":[{"key":"Model name","value":"Xiaomi Surge S1","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Xiaomi","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"S1","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 28, 2017","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Surge","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1400,"unit":"MHz","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2200,"unit":"MHz","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AXI","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T860","unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":800,"unit":"MHz","sourceId":"chipswiki-399-r866","location":"Xiaomi/surge/s1 · revision 866 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-07. Not an independent measurement.","entityId":"cw-b05db4457cde7e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","sourceDate":"2022-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-399-r866"],"url":"https://museum.vlsi.kr/objects/cw-b05db4457cde7e62"},{"id":"cw-b077d61ad24a395d","name":"Embedded G-Series T44R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t44r"],"fields":[{"key":"Model name","value":"Embedded G-Series T44R","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T44R","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET44RFPB12GVE","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2011","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9,"unit":"W","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1 × 512 KiB","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6250","unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":280,"unit":"MHz","sourceId":"chipswiki-420-r892","location":"Amd/embedded/t44r · revision 892 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-b077d61ad24a395d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-420-r892","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-b077d61ad24a395d"},{"id":"cw-b0a7d7213b8f6bb4","name":"Xeon W-2191B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2191b"],"fields":[{"key":"Model name","value":"Xeon W-2191B","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2191B","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2017","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 21, 2017","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-815-r2097","location":"Intel/xeon w/w-2191b · revision 2097 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-17. Not an independent measurement.","entityId":"cw-b0a7d7213b8f6bb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","sourceDate":"2021-02-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-815-r2097"],"url":"https://museum.vlsi.kr/objects/cw-b0a7d7213b8f6bb4"},{"id":"cw-b0fb4457525b7251","name":"CN5860-900 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-900bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5860-900 SCP","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-900 SCP","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-900BG1521-SCP","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8114-r25773","location":"Cavium/octeon plus/cn5860-900bg1521-scp · revision 25773 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b0fb4457525b7251","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8114-r25773","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b0fb4457525b7251"},{"id":"cw-b1049257387dda36","name":"Xeon Gold 5117F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5117f"],"fields":[{"key":"Model name","value":"Xeon Gold 5117F","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5117F","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KM","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":113,"unit":"W","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-269-r544","location":"Intel/xeon gold/5117f · revision 544 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-b1049257387dda36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-269-r544"],"url":"https://museum.vlsi.kr/objects/cw-b1049257387dda36"},{"id":"cw-b114994b210f24b5","name":"Core i7-2715QE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2715qe"],"fields":[{"key":"Model name","value":"Core i7-2715QE","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2715QE","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700843908","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR076","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2011","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2011","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7878-r25382","location":"Intel/core i7/i7-2715qe · revision 25382 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b114994b210f24b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7878-r25382","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-b114994b210f24b5"},{"id":"cw-b1169818a286cfca","name":"Core i5-2510E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2510e"],"fields":[{"key":"Model name","value":"Core i5-2510E","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2510E","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700853304","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02U","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7954-r25502","location":"Intel/core i5/i5-2510e · revision 25502 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1169818a286cfca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7954-r25502","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-b1169818a286cfca"},{"id":"cw-b11f680486863720","name":"Xeon E5-1607 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-1000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-1607 v4"],"fields":[{"key":"Model name","value":"Xeon E5-1607 v4","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-1607 v4","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002395500","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-1000","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2PH","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP Workstation","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2.5 MiB","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7749-r25131","location":"Intel/xeon e5/e5-1607 v4 · revision 25131 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b11f680486863720","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7749-r25131"],"url":"https://museum.vlsi.kr/objects/cw-b11f680486863720"},{"id":"cw-b1668beac2ffba3a","name":"CN5850-800 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-800bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5850-800 NSP","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-800 NSP","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-800BG1521-NSP","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8130-r25789","location":"Cavium/octeon plus/cn5850-800bg1521-nsp · revision 25789 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1668beac2ffba3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8130-r25789","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b1668beac2ffba3a"},{"id":"cw-b169d91b894410e5","name":"Snapdragon 660","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2017,"architecture":"Cortex-A73","process":"14 nm","aliases":["Qualcomm snapdragon 600 660"],"fields":[{"key":"Model name","value":"Snapdragon 660","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM660","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 8, 2017","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 8, 2017","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 600","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2.2,"unit":"GHz","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1.84,"unit":"GHz","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 260 Gold","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 260 Silver","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 512","unit":"","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":600,"unit":"MHz","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":650,"unit":"MHz","sourceId":"chipswiki-326-r648","location":"Qualcomm/snapdragon 600/660 · revision 648 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-30. Not an independent measurement.","entityId":"cw-b169d91b894410e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","sourceDate":"2022-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-326-r648"],"url":"https://museum.vlsi.kr/objects/cw-b169d91b894410e5"},{"id":"cw-b171014378d256f8","name":"Xeon E5-2623 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2623 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2623 v4","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2623 v4","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002402400","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2PJ","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2.5 MiB","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7743-r25120","location":"Intel/xeon e5/e5-2623 v4 · revision 25120 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b171014378d256f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7743-r25120"],"url":"https://museum.vlsi.kr/objects/cw-b171014378d256f8"},{"id":"cw-b1842321a5085f58","name":"Core i5-520M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-500","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-520m"],"fields":[{"key":"Model name","value":"Intel Core i5-520M","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-520M","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80617I5520M","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004119AE","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004119AE","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2933.33,"unit":"MHz","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBNB","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBNA","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBU3","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBU4","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1280","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":766,"unit":"MHz","sourceId":"chipswiki-3787-r11778","location":"Intel/core i5/i5-520m · revision 11778 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b1842321a5085f58","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3787-r11778","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-b1842321a5085f58"},{"id":"cw-b18641dd4e5c473b","name":"QCS603","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"QCS600","year":2018,"process":"10 nm","aliases":["Qualcomm vision intelligence qcs603"],"fields":[{"key":"Model name","value":"QCS603","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"QCS603","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 11, 2018","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 11, 2018","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vision Intelligence","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"QCS600","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1600,"unit":"MHz","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 300 Silver","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 300 Gold","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3732","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 615","unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6393-r19871","location":"Qualcomm/vision intelligence/qcs603 · revision 19871 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-b18641dd4e5c473b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6393-r19871"],"url":"https://museum.vlsi.kr/objects/cw-b18641dd4e5c473b"},{"id":"cw-b1ba721402f8e456","name":"CN5734-600 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-600bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5734-600 SP","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-600 SP","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-600BG1217-SP","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8191-r25850","location":"Cavium/octeon plus/cn5734-600bg1217-sp · revision 25850 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1ba721402f8e456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8191-r25850","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-b1ba721402f8e456"},{"id":"cw-b1c4e545a1cee3ec","name":"AMD-K6-2/333BNZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333bnz"],"fields":[{"key":"Model name","value":"K6-2/333BNZ","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333BNZ","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333BNZ","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-360","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8369-r26064","location":"Amd/k6-2/k6-2-333bnz · revision 26064 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1c4e545a1cee3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8369-r26064"],"url":"https://museum.vlsi.kr/objects/cw-b1c4e545a1cee3ec"},{"id":"cw-b1d768e0f107c214","name":"Atom Z620","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z620","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z620"],"fields":[{"key":"Model name","value":"Atom Z620","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z620","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609003996AC","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZE","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z620","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":1.3,"unit":"W","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-25 °C","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8054-r25690","location":"Intel/atom/z620 · revision 25690 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d768e0f107c214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8054-r25690","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-b1d768e0f107c214"},{"id":"cw-b1d7da01620995e9","name":"8080","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"MCS80","year":1974,"architecture":"8080","process":"6 µm","aliases":["Intel mcs-80 8080"],"fields":[{"key":"Model name","value":8080,"unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8080,"unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"C8080","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 15, 1974","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 1974","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MCS-80","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MCS80","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":500,"unit":"kHz","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2.08,"unit":"MHz","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":8080,"unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":6,"unit":"µm","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":20.1,"unit":"mm²","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7809-r25248","location":"Intel/mcs-80/8080 · revision 25248 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b1d7da01620995e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7809-r25248"],"url":"https://museum.vlsi.kr/objects/cw-b1d7da01620995e9"},{"id":"cw-b1eb27268c113f43","name":"A14 Bionic","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2020,"architecture":"Firestorm","process":"5 nm (N5)","aliases":["Apple ax a14"],"fields":[{"key":"Model name","value":"A14 Bionic","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A14 Bionic","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 16, 2020","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2020","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.5","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Firestorm","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Firestorm","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Icestorm","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"5 nm (N5)","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":11800000000,"unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":88,"unit":"mm²","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2-r96913","location":"Apple/ax/a14 · revision 96913 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-12. Not an independent measurement.","entityId":"cw-b1eb27268c113f43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","sourceDate":"2022-12-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2-r96913"],"url":"https://museum.vlsi.kr/objects/cw-b1eb27268c113f43"},{"id":"cw-b1ef8b272fdf9128","name":"Xeon D-1513N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2017,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1513n"],"fields":[{"key":"Model name","value":"D-1513N","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1513N","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068203255106","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KV","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2017","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-3722-r11412","location":"Intel/xeon d/d-1513n · revision 11412 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-b1ef8b272fdf9128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3722-r11412"],"url":"https://museum.vlsi.kr/objects/cw-b1ef8b272fdf9128"},{"id":"cw-b1f487c64dbeda7c","name":"Alchemy Au1250-600MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1250-600mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1250-600MGD","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1250-600MGD","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1250-600MGD","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1400 mW","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-441-r922","location":"Alchemy/au1250-600mgd · revision 922 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-b1f487c64dbeda7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-441-r922"],"url":"https://museum.vlsi.kr/objects/cw-b1f487c64dbeda7c"},{"id":"cw-b250b96385997a12","name":"Cortex-A77","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2019,"process":"10 nm","aliases":["Arm holdings microarchitectures cortex-a77"],"fields":[{"key":"Architecture name","value":"Cortex-A77","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 27, 2019","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":13,"unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"128-512 KiB","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"0-4 MiB","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A76","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A78","unit":"","sourceId":"chipswiki-1089-r3208","location":"Arm holdings/microarchitectures/cortex-a77 · revision 3208 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-07. Not an independent measurement.","entityId":"cw-b250b96385997a12","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","sourceDate":"2020-06-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1089-r3208"],"url":"https://museum.vlsi.kr/objects/cw-b250b96385997a12"},{"id":"cw-b259aab5535be35e","name":"SX-Aurora","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"NEC","year":2018,"aliases":["Nec microarchitectures sx-aurora"],"fields":[{"key":"Architecture name","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":8,"unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"chip","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"chip","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"SX-ACE","unit":"","sourceId":"chipswiki-1136-r3403","location":"Nec/microarchitectures/sx-aurora · revision 3403 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-15. Not an independent measurement.","entityId":"cw-b259aab5535be35e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","sourceDate":"2020-05-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1136-r3403"],"url":"https://museum.vlsi.kr/objects/cw-b259aab5535be35e"},{"id":"cw-b263cd797689814d","name":"Core i5-6685R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6685r"],"fields":[{"key":"Model name","value":"Core i5-6685R","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6685R","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 22, 2016","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 22, 2016","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics 580","unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7911-r25449","location":"Intel/core i5/i5-6685r · revision 25449 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b263cd797689814d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7911-r25449","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-b263cd797689814d"},{"id":"cw-b26f2b063fc52ca9","name":"Xeon Gold 5115","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5115"],"fields":[{"key":"Model name","value":"Xeon Gold 5115","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5115,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303535601","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GB","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1531-r4987","location":"Intel/xeon gold/5115 · revision 4987 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-b26f2b063fc52ca9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1531-r4987"],"url":"https://museum.vlsi.kr/objects/cw-b26f2b063fc52ca9"},{"id":"cw-b288b2dab0e75538","name":"Neoverse N2","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2020,"process":"7 nm","aliases":["Arm holdings microarchitectures neoverse n2"],"fields":[{"key":"Architecture name","value":"Zeus","unit":"","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2020,"unit":"","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Ares","unit":"","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Poseidon","unit":"","sourceId":"chipswiki-775-r1908","location":"Arm holdings/microarchitectures/neoverse n2 · revision 1908 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-b288b2dab0e75538","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-775-r1908"],"url":"https://museum.vlsi.kr/objects/cw-b288b2dab0e75538"},{"id":"cw-b2917bbffb1039f8","name":"Core i7-8550U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-8550u"],"fields":[{"key":"Model name","value":"Core i7-8550U","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8550U","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067703281816","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LC","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 21, 2017","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 21, 2017","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake R","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":123,"unit":"mm²","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-2207-r7466","location":"Intel/core i7/i7-8550u · revision 7466 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","sourceDate":"2019-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-25. Not an independent measurement.","entityId":"cw-b2917bbffb1039f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2207-r7466","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-b2917bbffb1039f8"},{"id":"cw-b2c910340708c39a","name":"Helio X10 (MT6795)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2015,"architecture":"Cortex-A53","process":"28 nm","aliases":["Mediatek helio mt6795"],"fields":[{"key":"Model name","value":"MediaTek Helio X10","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X10","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6795","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6795","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 15, 2014","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 27, 2015","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"MWPOP-1108","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"MWPOP","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR G6200","unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":700,"unit":"MHz","sourceId":"chipswiki-986-r2806","location":"Mediatek/helio/mt6795 · revision 2806 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-b2c910340708c39a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-986-r2806"],"url":"https://museum.vlsi.kr/objects/cw-b2c910340708c39a"},{"id":"cw-b30d28afffdeca0d","name":"Core i3-2340UE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2340ue"],"fields":[{"key":"Model name","value":"Core i3-2340UE","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2340UE","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700849710","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR074","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-8011-r25592","location":"Intel/core i3/i3-2340ue · revision 25592 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b30d28afffdeca0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8011-r25592","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-b30d28afffdeca0d"},{"id":"cw-b3220257d40c2d9e","name":"SPARC64 XII","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Fujitsu","year":2017,"architecture":"SPARC64 XII","process":"20 nm","aliases":["Fujitsu sparc64 sparc64 xii"],"fields":[{"key":"Model name","value":"SPARC64 XII","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Fujitsu","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SPARC64 XII","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2015,"unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 4, 2017","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"SPARC64","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4250,"unit":"MHz","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V9","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SPARC64 XII","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":32,"unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3783-r11749","location":"Fujitsu/sparc64/sparc64 xii · revision 11749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-b3220257d40c2d9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3783-r11749"],"url":"https://museum.vlsi.kr/objects/cw-b3220257d40c2d9e"},{"id":"cw-b35e262b7b6f18fd","name":"CN5830-800 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon plus cn5830-800bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5830-800 SCP","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-800 SCP","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-800BG1521-SCP","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8153-r25812","location":"Cavium/octeon plus/cn5830-800bg1521-scp · revision 25812 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b35e262b7b6f18fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8153-r25812","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b35e262b7b6f18fd"},{"id":"cw-b378ee797a242e79","name":"POWER5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2004,"process":"130 nm","aliases":["Ibm microarchitectures power5"],"fields":[{"key":"Architecture name","value":"POWER5","unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2004,"unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER4","unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER6","unit":"","sourceId":"chipswiki-9919-r31543","location":"Ibm/microarchitectures/power5 · revision 31543 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-b378ee797a242e79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9919-r31543"],"url":"https://museum.vlsi.kr/objects/cw-b378ee797a242e79"},{"id":"cw-b37b8a9a590efa3b","name":"ET-Maxion","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Esperanto","year":2018,"process":"7 nm","aliases":["Esperanto microarchitectures et-maxion"],"fields":[{"key":"Architecture name","value":"ET-Maxion","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Esperanto","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"RV64","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"BOOM v2","unit":"","sourceId":"chipswiki-7136-r22517","location":"Esperanto/microarchitectures/et-maxion · revision 22517 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-b37b8a9a590efa3b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7136-r22517"],"url":"https://museum.vlsi.kr/objects/cw-b37b8a9a590efa3b"},{"id":"cw-b37eeed55923142b","name":"A7","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2013,"architecture":"Cyclone","process":"28 nm","aliases":["Apple ax a7"],"fields":[{"key":"Model name","value":"A7","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2013","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 2013","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cyclone","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cyclone","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":102,"unit":"mm²","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-811-r2071","location":"Apple/ax/a7 · revision 2071 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-26. Not an independent measurement.","entityId":"cw-b37eeed55923142b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","sourceDate":"2021-02-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-811-r2071"],"url":"https://museum.vlsi.kr/objects/cw-b37eeed55923142b"},{"id":"cw-b3fe64e63fd57614","name":"Ryzen 5 2400GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 2400ge"],"fields":[{"key":"Model name","value":"Ryzen 5 2400GE","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2400GE","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD2400C6M4MFB","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 19, 2018","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 19, 2018","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon RX Vega 11","unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1250,"unit":"MHz","sourceId":"chipswiki-5064-r16448","location":"Amd/ryzen 5/2400ge · revision 16448 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-b3fe64e63fd57614","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5064-r16448","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-b3fe64e63fd57614"},{"id":"cw-b402f29c34dd3188","name":"Core i3-7310T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7310t"],"fields":[{"key":"Model name","value":"Core i3-7310T","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7310T","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7300","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":"? °C","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7966-r25537","location":"Intel/core i3/i3-7310t · revision 25537 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b402f29c34dd3188","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7966-r25537"],"url":"https://museum.vlsi.kr/objects/cw-b402f29c34dd3188"},{"id":"cw-b40dfa10681a7197","name":"IC80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 ic80186-6"],"fields":[{"key":"Model name","value":"IC80186-6","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"IC80186-6","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"IC80186-6","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"IC80186-6B","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8647-r26846","location":"Amd/am186/ic80186-6 · revision 26846 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b40dfa10681a7197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8647-r26846"],"url":"https://museum.vlsi.kr/objects/cw-b40dfa10681a7197"},{"id":"cw-b431585feded0b7f","name":"Core i5-8400H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8400h"],"fields":[{"key":"Model name","value":"Core i5-8400H","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8400H","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068403373614","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3Z1","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6577-r20840","location":"Intel/core i5/i5-8400h · revision 20840 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-04. Not an independent measurement.","entityId":"cw-b431585feded0b7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6577-r20840","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-b431585feded0b7f"},{"id":"cw-b44d1491813f1531","name":"Xeon E5-2698 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2698 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2698 v4","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2698 v4","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002024000","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JW","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5,"unit":"MiB","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x256 KiB","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":50,"unit":"MiB","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x2.5 MiB","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7718-r25092","location":"Intel/xeon e5/e5-2698 v4 · revision 25092 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b44d1491813f1531","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7718-r25092"],"url":"https://museum.vlsi.kr/objects/cw-b44d1491813f1531"},{"id":"cw-b478d819afb07983","name":"Godson-2A","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":null,"architecture":"GS464","process":"180 nm","aliases":["Loongson godson 2 2a"],"fields":[{"key":"Model name","value":"Godson-2A","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMICS","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2A","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2003,"unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":250,"unit":"MHz","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7686-r24981","location":"Loongson/godson 2/2a · revision 24981 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b478d819afb07983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7686-r24981"],"url":"https://museum.vlsi.kr/objects/cw-b478d819afb07983"},{"id":"cw-b47bf469845a5cd1","name":"K6-2E/300AMZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-300amz-66"],"fields":[{"key":"Model name","value":"K6-2E/300AMZ-66","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/300AMZ-66","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/300AMZ-66","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8324-r26019","location":"Amd/k6-2/k6-2e-300amz-66 · revision 26019 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b47bf469845a5cd1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8324-r26019"],"url":"https://museum.vlsi.kr/objects/cw-b47bf469845a5cd1"},{"id":"cw-b49a91607a2c2981","name":"McKinley","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2002,"process":"180 nm","aliases":["Intel microarchitectures mckinley"],"fields":[{"key":"Architecture name","value":"McKinley","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"July 8, 2002","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Merced","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Madison","unit":"","sourceId":"chipswiki-8758-r27220","location":"Intel/microarchitectures/mckinley · revision 27220 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-b49a91607a2c2981","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8758-r27220"],"url":"https://museum.vlsi.kr/objects/cw-b49a91607a2c2981"},{"id":"cw-b4ada2c2f4a81fb6","name":"K6-2/400AFR-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400afr-66"],"fields":[{"key":"Model name","value":"K6-2/400AFR-66","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AFR-66","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AFR-66","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8351-r26046","location":"Amd/k6-2/k6-2-400afr-66 · revision 26046 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b4ada2c2f4a81fb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8351-r26046"],"url":"https://museum.vlsi.kr/objects/cw-b4ada2c2f4a81fb6"},{"id":"cw-b4adc08c4d30a930","name":"Cortex-A73","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2016,"aliases":["Arm holdings microarchitectures cortex-a73"],"fields":[{"key":"Architecture name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 29, 2016","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A72","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A75","unit":"","sourceId":"chipswiki-792-r1981","location":"Arm holdings/microarchitectures/cortex-a73 · revision 1981 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-05. Not an independent measurement.","entityId":"cw-b4adc08c4d30a930","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","sourceDate":"2021-04-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-792-r1981"],"url":"https://museum.vlsi.kr/objects/cw-b4adc08c4d30a930"},{"id":"cw-b506d44c960ad79c","name":"Xeon D-1633N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1633n"],"fields":[{"key":"Model name","value":"Xeon D-1633N","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1633N","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3683-r11011","location":"Intel/xeon d/d-1633n · revision 11011 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b506d44c960ad79c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3683-r11011"],"url":"https://museum.vlsi.kr/objects/cw-b506d44c960ad79c"},{"id":"cw-b51f7fd3bc3b1e30","name":"i486DX2-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX2","year":1992,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx2-66"],"fields":[{"key":"Model name","value":"Intel i486DX2-66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX2-66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2SA66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MA80486DX2-66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80P24-66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX2-66","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"TQ80486DX266","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 3, 1992","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX2","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK058","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK080","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX645","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX725","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX731","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX739","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX744","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX750","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX759","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX762","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 10","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 10","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 10","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX807","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 11","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 11","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 11","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX911","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 12","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 12","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 12","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX955","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 13","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 13","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 13","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SYE36","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / s-spec 14","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 14","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"s-spec 14","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MB","sourceId":"chipswiki-678-r1660","location":"Intel/80486/486dx2-66 · revision 1660 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-14. Not an independent measurement.","entityId":"cw-b51f7fd3bc3b1e30","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","sourceDate":"2021-06-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-678-r1660"],"url":"https://museum.vlsi.kr/objects/cw-b51f7fd3bc3b1e30"},{"id":"cw-b53563c63ba38ec7","name":"Xeon E-2224G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2224g"],"fields":[{"key":"Model name","value":"Xeon E-2224G","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2224G","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404173806","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFAW","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4700,"unit":"MHz","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":71,"unit":"W","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2413-r8072","location":"Intel/xeon e/e-2224g · revision 8072 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-b53563c63ba38ec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2413-r8072"],"url":"https://museum.vlsi.kr/objects/cw-b53563c63ba38ec7"},{"id":"cw-b5399ef5f399c499","name":"Am486DX2-80","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-80"],"fields":[{"key":"Model name","value":"Am486DX2-80","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-80","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-80","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1994,"unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 1994","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":80,"unit":"MHz","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":"5.0 V or 3.3 V","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-1279-r4217","location":"Amd/am486/am486dx2-80 · revision 4217 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-21. Not an independent measurement.","entityId":"cw-b5399ef5f399c499","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","sourceDate":"2020-02-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1279-r4217"],"url":"https://museum.vlsi.kr/objects/cw-b5399ef5f399c499"},{"id":"cw-b5516ba2562fb4d1","name":"8008-1","kind":"sku","entityType":"product-model","subtype":"sku","company":"Intel","year":null,"architecture":"8008","process":"10 μm","aliases":["Intel mcs-8 8008-1"],"fields":[{"key":"Model name","value":"8008-1","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8008-1","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"8008-1","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 1972","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MCS-8","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"kHz","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8008,"unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10 μm","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3500,"unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"pMOS","unit":"","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"KiB","sourceId":"chipswiki-7810-r25249","location":"Intel/mcs-8/8008-1 · revision 25249 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5516ba2562fb4d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7810-r25249"],"url":"https://museum.vlsi.kr/objects/cw-b5516ba2562fb4d1"},{"id":"cw-b55c29956707dfd2","name":"QorIQ P1011","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2009,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1011"],"fields":[{"key":"Model name","value":"QorIQ P1011","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1011","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 16, 2008","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2009,"unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8106-r25765","location":"Freescale/qoriq/p1011 · revision 25765 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA-II","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b55c29956707dfd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8106-r25765","chipswiki-31374-r92168"],"url":"https://museum.vlsi.kr/objects/cw-b55c29956707dfd2"},{"id":"cw-b59bdfad443f0ca4","name":"KiloCore","kind":"sku","entityType":"product-model","subtype":"cpu","company":"UC Davis","year":null,"process":"32 nm","aliases":["Uc davis kilocore"],"fields":[{"key":"Model name","value":"KiloCore","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"UC Davis","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 17, 2016","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1.78,"unit":"GHz","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":621000000,"unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":64,"unit":"mm²","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1000,"unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":"0.56 V - 1.1 V","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-676","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-676","unit":"","sourceId":"chipswiki-2541-r8759","location":"Uc davis/kilocore · revision 8759 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b59bdfad443f0ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2541-r8759"],"url":"https://museum.vlsi.kr/objects/cw-b59bdfad443f0ca4"},{"id":"cw-b5b5e181151be6be","name":"Core i3-2390M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2390m"],"fields":[{"key":"Model name","value":"Core i3-2390M","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2390M","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700846906","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700846907","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04M","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0DM","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7999-r25580","location":"Intel/core i3/i3-2390m · revision 25580 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5b5e181151be6be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7999-r25580","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-b5b5e181151be6be"},{"id":"cw-b5c2b5852ca115a5","name":"Xeon E7-2870","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-2800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-2870"],"fields":[{"key":"Model name","value":"Xeon E7-2870","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-2870","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007266AA","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-2800","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3U","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.56,"unit":"MiB","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x3 MiB","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7703-r25073","location":"Intel/xeon e7/e7-2870 · revision 25073 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b5c2b5852ca115a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7703-r25073","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-b5c2b5852ca115a5"},{"id":"cw-b5fd84ffefaf8cd0","name":"POWER9 02CY771","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy771"],"fields":[{"key":"Model name","value":"02CY771","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY771","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY771","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.2,"unit":"GHz","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":60,"unit":"MiB","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x10 MiB","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3940-r12566","location":"Ibm/power/02cy771 · revision 12566 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-b5fd84ffefaf8cd0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3940-r12566"],"url":"https://museum.vlsi.kr/objects/cw-b5fd84ffefaf8cd0"},{"id":"cw-b612a741f493caab","name":"CN3630-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-400bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3630-400 EXP","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-400 EXP","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-400BG1521-EXP","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8238-r25897","location":"Cavium/octeon/cn3630-400bg1521-exp · revision 25897 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b612a741f493caab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8238-r25897","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b612a741f493caab"},{"id":"cw-b629cc1cd10d6392","name":"CN5740-800 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-800bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5740-800 SP","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-800 SP","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-800BG1217-SP","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8181-r25840","location":"Cavium/octeon plus/cn5740-800bg1217-sp · revision 25840 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b629cc1cd10d6392","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8181-r25840","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-b629cc1cd10d6392"},{"id":"cw-b638cb51eb89d534","name":"Ryzen Threadripper PRO 5955WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5900","year":2022,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen threadripper pro 5955wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 5955WX","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5955WX","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000447","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 8, 2022","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5900,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chagall","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 32 MiB","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-394-r840","location":"Amd/ryzen threadripper/pro 5955wx · revision 840 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-b638cb51eb89d534","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-394-r840","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-b638cb51eb89d534"},{"id":"cw-b63baf71d25aa397","name":"Atom x7-Z8700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8700","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x7 z8700"],"fields":[{"key":"Model name","value":"Atom x7-Z8700","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x7-Z8700","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715809","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715825","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2015","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2015","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x7","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8700,"unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR27M","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29W","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1380","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8040-r25672","location":"Intel/atom x7/z8700 · revision 25672 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b63baf71d25aa397","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8040-r25672"],"url":"https://museum.vlsi.kr/objects/cw-b63baf71d25aa397"},{"id":"cw-b65bccb5518762b7","name":"Gen9","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2015,"process":"14 nm","aliases":["Intel microarchitectures gen9"],"fields":[{"key":"Architecture name","value":"Gen9","unit":"","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 5, 2015","unit":"","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen8","unit":"","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen9.5","unit":"","sourceId":"chipswiki-4490-r14591","location":"Intel/microarchitectures/gen9 · revision 14591 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-b65bccb5518762b7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4490-r14591"],"url":"https://museum.vlsi.kr/objects/cw-b65bccb5518762b7"},{"id":"cw-b69eb95ffc769e60","name":"Core i7-7600U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7600","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7600u"],"fields":[{"key":"Model name","value":"Core i7-7600U","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7600U","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067702739628","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR33Z","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7600","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7594-r24692","location":"Intel/core i7/i7-7600u · revision 24692 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","sourceDate":"2017-12-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-22. Not an independent measurement.","entityId":"cw-b69eb95ffc769e60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7594-r24692","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-b69eb95ffc769e60"},{"id":"cw-b6c9cf322ea98a3d","name":"CN8020","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN80xx","year":null,"architecture":"Armv8.1","aliases":["Cavium octeon tx cn8020"],"fields":[{"key":"Model name","value":"Octeon TX CN8020","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON TX","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN80xx","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ArmV8","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Armv8.1","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GB","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":208,"unit":"KiB","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":144,"unit":"KiB","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x72 KiB","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3/4-2100","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3906-r12389","location":"Cavium/octeon tx/cn8020 · revision 12389 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-02. Not an independent measurement.","entityId":"cw-b6c9cf322ea98a3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","sourceDate":"2019-02-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3906-r12389"],"url":"https://museum.vlsi.kr/objects/cw-b6c9cf322ea98a3d"},{"id":"cw-b6f14c4bcbbf4309","name":"Xeon E5-2608L v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2608l v4"],"fields":[{"key":"Model name","value":"Xeon E5-2608L v4","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2608L v4","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002045102","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P9","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":50,"unit":"W","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":20,"unit":"MiB","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2.5 MiB","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7747-r25124","location":"Intel/xeon e5/e5-2608l v4 · revision 25124 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6f14c4bcbbf4309","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7747-r25124"],"url":"https://museum.vlsi.kr/objects/cw-b6f14c4bcbbf4309"},{"id":"cw-b6fc133f56dd6eec","name":"K3V2E","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","year":2013,"architecture":"Cortex-A9","process":"40 nm","aliases":["Hisilicon k3 k3v2e"],"fields":[{"key":"Model name","value":"K3V2E","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K3V2E","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Hi3620","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2013,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2013,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K3","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":600000000,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR2-900","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":6.71,"unit":"GiB/s","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"GC4000","unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":16,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":480,"unit":"MHz","sourceId":"chipswiki-8093-r25747","location":"Hisilicon/k3/k3v2e · revision 25747 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TFBGA-576","unit":"","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TFBGA","unit":"","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":576,"unit":"","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":11.9,"unit":"mm","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":11.9,"unit":"mm","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b6fc133f56dd6eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8093-r25747","chipswiki-31402-r92235"],"url":"https://museum.vlsi.kr/objects/cw-b6fc133f56dd6eec"},{"id":"cw-b6fe8f5c29c2b4ca","name":"Core i3-7101TE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7101te"],"fields":[{"key":"Model name","value":"Core i3-7101TE","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7101TE","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067702867061","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR374","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4254-r13746","location":"Intel/core i3/i3-7101te · revision 13746 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-13. Not an independent measurement.","entityId":"cw-b6fe8f5c29c2b4ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","sourceDate":"2018-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4254-r13746"],"url":"https://museum.vlsi.kr/objects/cw-b6fe8f5c29c2b4ca"},{"id":"cw-b70034e09de7b691","name":"Core i7-1060G7","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i7 i7-1060g7"],"fields":[{"key":"Model name","value":"Core i7-1060G7","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-1060G7","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake Y","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9,"unit":"W","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":64,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1239-r3949","location":"Intel/core i7/i7-1060g7 · revision 3949 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-b70034e09de7b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1239-r3949"],"url":"https://museum.vlsi.kr/objects/cw-b70034e09de7b691"},{"id":"cw-b72cd1dee1832985","name":"CN5745-600 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-600bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5745-600 SP","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-600 SP","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-600BG1217-SP","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8175-r25834","location":"Cavium/octeon plus/cn5745-600bg1217-sp · revision 25834 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b72cd1dee1832985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8175-r25834","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-b72cd1dee1832985"},{"id":"cw-b759a4ffefd2b3a0","name":"Cortex-A8","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2005,"process":"65 nm","aliases":["Arm holdings microarchitectures cortex-a8"],"fields":[{"key":"Architecture name","value":"Cortex-A8","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 5, 2005","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":13,"unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"2-way","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM11","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A9","unit":"","sourceId":"chipswiki-4147-r13218","location":"Arm holdings/microarchitectures/cortex-a8 · revision 13218 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-b759a4ffefd2b3a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4147-r13218"],"url":"https://museum.vlsi.kr/objects/cw-b759a4ffefd2b3a0"},{"id":"cw-b75adea1ec93378b","name":"K6-2E+/400ATZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-400atz"],"fields":[{"key":"Model name","value":"K6-2E+/400ATZ","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/400ATZ","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/400ATZ","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1002-r2853","location":"Amd/k6-2+/k6-2e+-400atz · revision 2853 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-b75adea1ec93378b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1002-r2853","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-b75adea1ec93378b"},{"id":"cw-b77bbde5c058cd73","name":"Am186ED–25KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–25ki\\w"],"fields":[{"key":"Model name","value":"Am186ED–25KI\\W","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–25KI\\W","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–25KI\\W","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14668-r44729","location":"Amd/am186ex/am186ed–25ki\\w · revision 44729 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-b77bbde5c058cd73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14668-r44729"],"url":"https://museum.vlsi.kr/objects/cw-b77bbde5c058cd73"},{"id":"cw-b7ace857c7839d9a","name":"Core i7-8700B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i7 i7-8700b"],"fields":[{"key":"Model name","value":"Core i7-8700B","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8700B","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-977-r2767","location":"Intel/core i7/i7-8700b · revision 2767 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-b7ace857c7839d9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-977-r2767"],"url":"https://museum.vlsi.kr/objects/cw-b7ace857c7839d9a"},{"id":"cw-b7d1b57df582e80f","name":"CN5850-900 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-900bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5850-900 SCP","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-900 SCP","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-900BG1521-SCP","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8126-r25785","location":"Cavium/octeon plus/cn5850-900bg1521-scp · revision 25785 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b7d1b57df582e80f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8126-r25785","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b7d1b57df582e80f"},{"id":"cw-b800e7abbd1687a6","name":"Xeon E7-2820","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-2800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-2820"],"fields":[{"key":"Model name","value":"Xeon E7-2820","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-2820","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007245AA","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-2800","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5.86,"unit":"GT/s","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3R","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x3 MiB","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-1280-r4246","location":"Intel/xeon e7/e7-2820 · revision 4246 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","sourceDate":"2020-02-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-18. Not an independent measurement.","entityId":"cw-b800e7abbd1687a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1280-r4246","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-b800e7abbd1687a6"},{"id":"cw-b813143732634537","name":"CN3840-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-400bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3840-400 SCP","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-400 SCP","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-400BG1521-SCP","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8218-r25877","location":"Cavium/octeon/cn3840-400bg1521-scp · revision 25877 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b813143732634537","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8218-r25877","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b813143732634537"},{"id":"cw-b84649f923fc31d1","name":"Xeon E3-1260L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1260l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1260L v5","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1260L v5","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201921903","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2CR","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LH","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v5","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7766-r25158","location":"Intel/xeon e3/e3-1260l v5 · revision 25158 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84649f923fc31d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7766-r25158"],"url":"https://museum.vlsi.kr/objects/cw-b84649f923fc31d1"},{"id":"cw-b84dc4768c389465","name":"CN3110-550 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-550bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3110-550 SCP","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-550 SCP","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-550BG868-SCP","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8254-r25914","location":"Cavium/octeon/cn3110-550bg868-scp · revision 25914 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b84dc4768c389465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8254-r25914","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-b84dc4768c389465"},{"id":"cw-b850125dd9a3e324","name":"Larrabee","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2008,"process":"45 nm","aliases":["Intel microarchitectures larrabee"],"fields":[{"key":"Architecture name","value":"Larrabee","unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 12, 2008","unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":8,"unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86","unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Polaris","unit":"","sourceId":"chipswiki-3754-r11663","location":"Intel/microarchitectures/larrabee · revision 11663 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b850125dd9a3e324","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3754-r11663"],"url":"https://museum.vlsi.kr/objects/cw-b850125dd9a3e324"},{"id":"cw-b851b8ee962f5829","name":"VY86C810","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1996,"architecture":"ARM8","process":"0.5 µm","aliases":["Vti vl86cx vy86c810"],"fields":[{"key":"Model name","value":"VY86C810","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C810","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C810","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 26, 1996","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 1996","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv4","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM8","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM810","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":53.5,"unit":"mm²","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-7622-r24877","location":"Vti/vl86cx/vy86c810 · revision 24877 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-144","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":144,"unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b851b8ee962f5829","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7622-r24877","chipswiki-31401-r92231"],"url":"https://museum.vlsi.kr/objects/cw-b851b8ee962f5829"},{"id":"cw-b8785e3d178fb310","name":"Xeon Phi 7285","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"x205","year":2017,"architecture":"Knights Mill","process":"14 nm","aliases":["Intel xeon phi 7285"],"fields":[{"key":"Model name","value":"Xeon Phi 7285","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7285,"unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HJ8068303823800","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3VE","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 18, 2017","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 18, 2017","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Phi","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"x205","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Knights Mill","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A0","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":68,"unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":272,"unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":384,"unit":"GiB","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":250,"unit":"W","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4.25,"unit":"MiB","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2.125,"unit":"MiB","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"68x32 KiB","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2.125,"unit":"MiB","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"68x32 KiB","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":34,"unit":"MiB","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"34x1 MiB","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-2547-r8773","location":"Intel/xeon phi/7285 · revision 8773 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-b8785e3d178fb310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2547-r8773"],"url":"https://museum.vlsi.kr/objects/cw-b8785e3d178fb310"},{"id":"cw-b87e8066f6ea802b","name":"Core i3-2370LM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2370lm"],"fields":[{"key":"Model name","value":"Core i3-2370LM","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2370LM","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701066102","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR03Q","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-8003-r25584","location":"Intel/core i3/i3-2370lm · revision 25584 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b87e8066f6ea802b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8003-r25584","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-b87e8066f6ea802b"},{"id":"cw-b882a757a3d79184","name":"AMD-X5-133SFZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-133sfz"],"fields":[{"key":"Model name","value":"AMD-X5-133SFZ","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-133SFZ","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-133SFZ","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133,"unit":"MHz","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SQFP-208","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SQFP","unit":"","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8523-r26718","location":"Amd/am5x86/amd-x5-133sfz · revision 26718 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b882a757a3d79184","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8523-r26718"],"url":"https://museum.vlsi.kr/objects/cw-b882a757a3d79184"},{"id":"cw-b88720f6c678d704","name":"Celeron B710","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"700","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b710"],"fields":[{"key":"Model name","value":"Celeron B710","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B710","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701078501","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0DS","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":700,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6931-r21618","location":"Intel/celeron/b710 · revision 21618 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-b88720f6c678d704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6931-r21618","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-b88720f6c678d704"},{"id":"cw-b88d1e0adf74bb10","name":"Xeon D-1581","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1581"],"fields":[{"key":"Model name","value":"Xeon D-1581","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1581","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570204","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LZ","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.5 MiB","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3667-r10992","location":"Intel/xeon d/d-1581 · revision 10992 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b88d1e0adf74bb10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3667-r10992"],"url":"https://museum.vlsi.kr/objects/cw-b88d1e0adf74bb10"},{"id":"cw-b8a7f69c535cae09","name":"POWER6+","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2008,"process":"65 nm","aliases":["Ibm microarchitectures power6+"],"fields":[{"key":"Architecture name","value":"POWER6+","unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2008,"unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER6","unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER7","unit":"","sourceId":"chipswiki-15947-r52538","location":"Ibm/microarchitectures/power6+ · revision 52538 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-02-01. Not an independent measurement.","entityId":"cw-b8a7f69c535cae09","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","sourceDate":"2017-02-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15947-r52538"],"url":"https://museum.vlsi.kr/objects/cw-b8a7f69c535cae09"},{"id":"cw-b8b10e35855172e8","name":"Duron 950 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron d950aut1b"],"fields":[{"key":"Model name","value":"Duron 950","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 950","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D950AUT1B","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0950AUT1B","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 6, 2001","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 6, 2001","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":950,"unit":"MHz","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":41.5,"unit":"W","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8429-r26137","location":"Amd/duron/d950aut1b · revision 26137 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8b10e35855172e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8429-r26137"],"url":"https://museum.vlsi.kr/objects/cw-b8b10e35855172e8"},{"id":"cw-b8b4780d8e669402","name":"Alchemy Au1550-333MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-333mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1550-333MBC","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-333MBC","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-333MBCAA","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1350 mW","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-467-r948","location":"Alchemy/au1550-333mbc · revision 948 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-b8b4780d8e669402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-467-r948"],"url":"https://museum.vlsi.kr/objects/cw-b8b4780d8e669402"},{"id":"cw-b8e33ddb1ebfc938","name":"Atom N280","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N200","year":2009,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom n280"],"fields":[{"key":"Model name","value":"Atom N280","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N280","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AU80586GF028D","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLGL9","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2008,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2009","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N200","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1666.66,"unit":"MHz","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"666.66 MT/s","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Nettop 2008","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Calistoga","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Diamondville","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":112,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":25.9638,"unit":"mm²","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.5,"unit":"W","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8072-r25708","location":"Intel/atom/n280 · revision 25708 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8e33ddb1ebfc938","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8072-r25708","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-b8e33ddb1ebfc938"},{"id":"cw-b8ea51bb108f50de","name":"N80C286-20","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80C286","year":1990,"architecture":"80286","process":"800 nm","aliases":["Amd am286 n80c286-20"],"fields":[{"key":"Model name","value":"N80C286-20","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80C286-20","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N80C286-20","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1990,"unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80C286","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"20 MT/s","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":165,"unit":"°C","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8592-r26790","location":"Amd/am286/n80c286-20 · revision 26790 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b8ea51bb108f50de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8592-r26790"],"url":"https://museum.vlsi.kr/objects/cw-b8ea51bb108f50de"},{"id":"cw-b903180fe98e52ff","name":"FT-1500A/16","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Phytium","series":"FT-1500A","year":2016,"architecture":"Earth","process":"28 nm","aliases":["Phytium feiteng ft-1500a-16"],"fields":[{"key":"Model name","value":"FT-1500A/16","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Phytium","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FT-1500A/16","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 26, 2015","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 26, 2016","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"FeiTeng","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"FT-1500A","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Earth","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Xiaomi FTC660","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1944","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1944","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"15x32 KiB","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3766-r11689","location":"Phytium/feiteng/ft-1500a-16 · revision 11689 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-b903180fe98e52ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3766-r11689"],"url":"https://museum.vlsi.kr/objects/cw-b903180fe98e52ff"},{"id":"cw-b9036e564498ca34","name":"Core i5-560M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-500","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-560m"],"fields":[{"key":"Model name","value":"Intel Core i5-560M","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-560M","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80617I5560M","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617005487AA","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005487AA","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3199.99,"unit":"MHz","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTS","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTT","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":766,"unit":"MHz","sourceId":"chipswiki-2041-r6903","location":"Intel/core i5/i5-560m · revision 6903 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-b9036e564498ca34","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2041-r6903","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-b9036e564498ca34"},{"id":"cw-b912ad1e67cae3db","name":"CN3630-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-500bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3630-500 NSP","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-500 NSP","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-500BG1521-NSP","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8234-r25893","location":"Cavium/octeon/cn3630-500bg1521-nsp · revision 25893 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-b912ad1e67cae3db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8234-r25893","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-b912ad1e67cae3db"},{"id":"cw-b929104d3aabb1f9","name":"Xeon W-2102","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2102"],"fields":[{"key":"Model name","value":"Xeon W-2102","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2102","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303532802","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LG","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":71.53,"unit":"GiB/s","sourceId":"chipswiki-4518-r14682","location":"Intel/xeon w/w-2102 · revision 14682 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-b929104d3aabb1f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4518-r14682"],"url":"https://museum.vlsi.kr/objects/cw-b929104d3aabb1f9"},{"id":"cw-b96f28dd4ec5bf36","name":"Snapdragon 855","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"800","year":2019,"architecture":"Cortex-A76","process":"7 nm","aliases":["Qualcomm snapdragon 800 855"],"fields":[{"key":"Model name","value":"Qualcomm Snapdragon 855","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM855","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SM8150","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 4, 2018","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2019","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 800","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2420,"unit":"MHz","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2840,"unit":"MHz","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 485 Gold","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 485 Silver","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":6700000000,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73.27,"unit":"mm²","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"1x64 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"1x64 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x512 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":384,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":192,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"3x64 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":192,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"3x64 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":768,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"3x256 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 3)","value":512,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 3)","value":256,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 3)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 3)","value":"2-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 3)","value":256,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 3)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 3)","value":"4-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 3)","value":512,"unit":"KiB","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 3)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 3)","value":"8-way set associative","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 3)","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"Cache (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 640 GPU","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":"2 (384x2 ALU)","unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":257,"unit":"MHz","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":585,"unit":"MHz","sourceId":"chipswiki-41-r96981","location":"Qualcomm/snapdragon 800/855 · revision 96981 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-29. Not an independent measurement.","entityId":"cw-b96f28dd4ec5bf36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","sourceDate":"2022-10-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-41-r96981"],"url":"https://museum.vlsi.kr/objects/cw-b96f28dd4ec5bf36"},{"id":"cw-b97c5d9a3daebc70","name":"Xeon D-1649N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1649n"],"fields":[{"key":"Model name","value":"Xeon D-1649N","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1649N","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3684-r11012","location":"Intel/xeon d/d-1649n · revision 11012 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-b97c5d9a3daebc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3684-r11012"],"url":"https://museum.vlsi.kr/objects/cw-b97c5d9a3daebc70"},{"id":"cw-b980544120403ebd","name":"Core i5-7Y54","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7Y","year":2016,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7y54"],"fields":[{"key":"Model name","value":"Core i5-7Y54","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7Y54","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739826","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZX","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR345","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7Y","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-4977-r16099","location":"Intel/core i5/i5-7y54 · revision 16099 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-b980544120403ebd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4977-r16099"],"url":"https://museum.vlsi.kr/objects/cw-b980544120403ebd"},{"id":"cw-b9866652a55468de","name":"Rock Creek","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2009,"process":"45 nm","aliases":["Intel microarchitectures rock creek"],"fields":[{"key":"Architecture name","value":"Rock Creek","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"December 2009","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":48,"unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"KiB","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"tile","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"tile","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Polaris","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Knights Ferry","unit":"","sourceId":"chipswiki-3750-r11649","location":"Intel/microarchitectures/rock creek · revision 11649 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-b9866652a55468de","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3750-r11649"],"url":"https://museum.vlsi.kr/objects/cw-b9866652a55468de"},{"id":"cw-ba0438c3286c1255","name":"Snapdragon 675","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2018,"architecture":"Cortex-A76","process":"11 nm","aliases":["Qualcomm snapdragon 600 675"],"fields":[{"key":"Model name","value":"Snapdragon 675","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM675","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 22, 2018","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 22, 2018","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 600","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2000,"unit":"MHz","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 460 Gold","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 460 Silver","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":11,"unit":"nm","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":64,"unit":"KiB","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 612","unit":"","sourceId":"chipswiki-557-r1160","location":"Qualcomm/snapdragon 600/675 · revision 1160 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-18. Not an independent measurement.","entityId":"cw-ba0438c3286c1255","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","sourceDate":"2021-12-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-557-r1160"],"url":"https://museum.vlsi.kr/objects/cw-ba0438c3286c1255"},{"id":"cw-ba0c09d55791bd0d","name":"ARM3","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Acorn","year":1989,"process":"1.5 µm","aliases":["Acorn microarchitectures arm3"],"fields":[{"key":"Architecture name","value":"ARM3","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Acorn Computers","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Sanyo","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":1989,"unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":3,"unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-way","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv2a","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"KiB","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / l1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM3","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM250","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM2","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM6","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM250","unit":"","sourceId":"chipswiki-573-r1233","location":"Acorn/microarchitectures/arm3 · revision 1233 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-ba0c09d55791bd0d","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-573-r1233"],"url":"https://museum.vlsi.kr/objects/cw-ba0c09d55791bd0d"},{"id":"cw-ba5f5361d11dc7ca","name":"Am186ER–50VI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–50vi\\w"],"fields":[{"key":"Model name","value":"Am186ER–50VI\\W","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–50VI\\W","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–50VI\\W","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 31, 1998","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14632-r44693","location":"Amd/am186ex/am186er–50vi\\w · revision 44693 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ba5f5361d11dc7ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14632-r44693"],"url":"https://museum.vlsi.kr/objects/cw-ba5f5361d11dc7ca"},{"id":"cw-ba6c4c6897433e00","name":"Celeron G4920","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel celeron g4920"],"fields":[{"key":"Model name","value":"Celeron G4920","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4920","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80684G4920","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403378011","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YL","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6446-r20179","location":"Intel/celeron/g4920 · revision 20179 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ba6c4c6897433e00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6446-r20179"],"url":"https://museum.vlsi.kr/objects/cw-ba6c4c6897433e00"},{"id":"cw-baa72d29af6519ea","name":"CN3630-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3630-600 NSP","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-600 NSP","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-600BG1521-NSP","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8231-r25890","location":"Cavium/octeon/cn3630-600bg1521-nsp · revision 25890 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-baa72d29af6519ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8231-r25890","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-baa72d29af6519ea"},{"id":"cw-bac9ccc86f7a6abf","name":"Ryzen 3 PRO 4450U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 pro 4450u"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 4450U","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4450U","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000104","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2020","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2020","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 5","unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":5,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-690-r1684","location":"Amd/ryzen 3/pro 4450u · revision 1684 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-bac9ccc86f7a6abf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-690-r1684"],"url":"https://museum.vlsi.kr/objects/cw-bac9ccc86f7a6abf"},{"id":"cw-bb1fedc643ccbd7f","name":"Am2016","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 2","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2016"],"fields":[{"key":"Model name","value":"Am2016","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2016","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2016","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 15, 2007","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 15, 2007","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 2","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":120,"unit":"","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8667-r26866","location":"Ambric/am2000/am2016 · revision 26866 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb1fedc643ccbd7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8667-r26866"],"url":"https://museum.vlsi.kr/objects/cw-bb1fedc643ccbd7f"},{"id":"cw-bb4df69799f17366","name":"CN5745-800 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-800bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5745-800 SSP","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-800 SSP","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-800BG1217-SSP","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8172-r25831","location":"Cavium/octeon plus/cn5745-800bg1217-ssp · revision 25831 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb4df69799f17366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8172-r25831","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-bb4df69799f17366"},{"id":"cw-bb4f21c3d8cd3b72","name":"Embedded G-Series T48L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t48l"],"fields":[{"key":"Model name","value":"Embedded G-Series T48L","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T48L","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET48LGBB22GVE","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 1, 2011","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-418-r890","location":"Amd/embedded/t48l · revision 890 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-bb4f21c3d8cd3b72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-418-r890","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-bb4f21c3d8cd3b72"},{"id":"cw-bb813ed6430c3000","name":"Lakefield","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2019,"process":"22 nm","aliases":["Intel microarchitectures lakefield"],"fields":[{"key":"Architecture name","value":"Lakefield","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":5,"unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"512 KiB + 1.5 MiB","unit":"","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"architecture scope","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"architecture scope","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-640-r1543","location":"Intel/microarchitectures/lakefield · revision 1543 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"chip","note":"Source-reported parameter; source revision 2021-08-14. Not an independent measurement.","entityId":"cw-bb813ed6430c3000","scope":"chip","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","sourceDate":"2021-08-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-640-r1543"],"url":"https://museum.vlsi.kr/objects/cw-bb813ed6430c3000"},{"id":"cw-bb8b51a1571f5b7c","name":"K6-2/233AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-233afr"],"fields":[{"key":"Model name","value":"K6-2/233AFR","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/233AFR","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/233AFR","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8389-r26084","location":"Amd/k6-2/k6-2-233afr · revision 26084 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bb8b51a1571f5b7c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8389-r26084"],"url":"https://museum.vlsi.kr/objects/cw-bb8b51a1571f5b7c"},{"id":"cw-bbafd65c7cfbd442","name":"PPS-4 (10660)","kind":"sku","entityType":"product-model","subtype":"sku","company":"Rockwell International","year":1972,"architecture":"PPS-4","process":"10 μm","aliases":["Rockwell international pps-4 10660"],"fields":[{"key":"Model name","value":"Rockwell PPS-4","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Rockwell International","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Rockwell International","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PPS-4","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":10660,"unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":12660,"unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 1972","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PPS-4","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":198.864,"unit":"kHz","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"PPS-4","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10 μm","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1900,"unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":12,"unit":"mm²","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"KiB","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"600 mW","unit":"","sourceId":"chipswiki-286-r574","location":"Rockwell international/pps-4/10660 · revision 574 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-bbafd65c7cfbd442","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-286-r574"],"url":"https://museum.vlsi.kr/objects/cw-bbafd65c7cfbd442"},{"id":"cw-bbbe882d0e06f356","name":"CN5745-900 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-900bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5745-900 SP","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-900 SP","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-900BG1217-SP","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8171-r25830","location":"Cavium/octeon plus/cn5745-900bg1217-sp · revision 25830 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbbe882d0e06f356","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8171-r25830","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-bbbe882d0e06f356"},{"id":"cw-bbea5d4f2b5f8d96","name":"Celeron 3965U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3900","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron 3965u"],"fields":[{"key":"Model name","value":"Celeron 3965U","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3965U","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067702739934","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34A","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3900,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-8035-r25666","location":"Intel/celeron/3965u · revision 25666 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bbea5d4f2b5f8d96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8035-r25666","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-bbea5d4f2b5f8d96"},{"id":"cw-bbf683bcbeb3bdd6","name":"AMD-X5-150ADW","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-150adw"],"fields":[{"key":"Model name","value":"AMD-X5-150ADW","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-150ADW","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-150ADW","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":150,"unit":"MHz","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-791-r1971","location":"Amd/am5x86/amd-x5-150adw · revision 1971 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-11. Not an independent measurement.","entityId":"cw-bbf683bcbeb3bdd6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","sourceDate":"2021-04-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-791-r1971"],"url":"https://museum.vlsi.kr/objects/cw-bbf683bcbeb3bdd6"},{"id":"cw-bc05784aa9de6210","name":"K6-2/350AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-350afk"],"fields":[{"key":"Model name","value":"K6-2/350AFK","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/350AFK","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/350AFK","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":349.99,"unit":"MHz","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8366-r26061","location":"Amd/k6-2/k6-2-350afk · revision 26061 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc05784aa9de6210","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8366-r26061"],"url":"https://museum.vlsi.kr/objects/cw-bc05784aa9de6210"},{"id":"cw-bc06694486fcb486","name":"Duron 750 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d750ast1b"],"fields":[{"key":"Model name","value":"Duron 750","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 750","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D750AST1B","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 5, 2000","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 5, 2000","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":750,"unit":"MHz","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":31.2,"unit":"W","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8435-r26143","location":"Amd/duron/d750ast1b · revision 26143 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc06694486fcb486","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8435-r26143"],"url":"https://museum.vlsi.kr/objects/cw-bc06694486fcb486"},{"id":"cw-bc2bf55003838a77","name":"Ryzen 7 5800HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 5800hs"],"fields":[{"key":"Model name","value":"Ryzen 7 5800HS","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5800HS","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000295","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-719-r1729","location":"Amd/ryzen 7/5800hs · revision 1729 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-bc2bf55003838a77","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-719-r1729"],"url":"https://museum.vlsi.kr/objects/cw-bc2bf55003838a77"},{"id":"cw-bc2d58bda57fa652","name":"K6-2/333AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333afr"],"fields":[{"key":"Model name","value":"K6-2/333AFR","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333AFR","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333AFR","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8375-r26070","location":"Amd/k6-2/k6-2-333afr · revision 26070 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc2d58bda57fa652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8375-r26070"],"url":"https://museum.vlsi.kr/objects/cw-bc2d58bda57fa652"},{"id":"cw-bc386c29303d432c","name":"CN5740-600 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-600bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5740-600 SSP","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-600 SSP","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-600BG1217-SSP","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8182-r25841","location":"Cavium/octeon plus/cn5740-600bg1217-ssp · revision 25841 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bc386c29303d432c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8182-r25841","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-bc386c29303d432c"},{"id":"cw-bc967dd0a6d9c6ba","name":"Xeon Gold 5217","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5217"],"fields":[{"key":"Model name","value":"Xeon Gold 5217","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5217,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504214302","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBF","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":115,"unit":"W","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1527-r4981","location":"Intel/xeon gold/5217 · revision 4981 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bc967dd0a6d9c6ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1527-r4981"],"url":"https://museum.vlsi.kr/objects/cw-bc967dd0a6d9c6ba"},{"id":"cw-bcb3ac0f29ae186f","name":"Esther","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"VIA Technologies","year":null,"process":"90 nm","aliases":["Via technologies microarchitectures esther"],"fields":[{"key":"Architecture name","value":"Esther","unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"VIA Technologies","unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":16,"unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Nehemiah","unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Isaiah","unit":"","sourceId":"chipswiki-7378-r23864","location":"Via technologies/microarchitectures/esther · revision 23864 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-bcb3ac0f29ae186f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7378-r23864"],"url":"https://museum.vlsi.kr/objects/cw-bcb3ac0f29ae186f"},{"id":"cw-bcbe29416d003a42","name":"Exynos 7885","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2018,"architecture":"Cortex-A73","process":"14 nm","aliases":["Samsung exynos 7885"],"fields":[{"key":"Model name","value":"Exynos 7885","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7885,"unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 13, 2018","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 13, 2018","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1600,"unit":"MHz","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"7,46GB/s","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"LPP","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":"2.000.000.000","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GB","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":8,"unit":"W","sourceId":"chipswiki-839-r2200","location":"Samsung/exynos/7885 · revision 2200 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-16. Not an independent measurement.","entityId":"cw-bcbe29416d003a42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","sourceDate":"2021-01-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-839-r2200"],"url":"https://museum.vlsi.kr/objects/cw-bcbe29416d003a42"},{"id":"cw-bcc5f71e08e9146e","name":"Xeon D-1533N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2017,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1533n"],"fields":[{"key":"Model name","value":"Xeon D-1533N","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1533N","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068203255103","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KS","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2017","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3724-r11417","location":"Intel/xeon d/d-1533n · revision 11417 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-bcc5f71e08e9146e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3724-r11417"],"url":"https://museum.vlsi.kr/objects/cw-bcc5f71e08e9146e"},{"id":"cw-bcee336c4ed0cdd4","name":"Celeron 887","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 887"],"fields":[{"key":"Model name","value":"Celeron 887","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":887,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148101","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085400","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085401","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FE","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR090","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0VA","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6934-r21621","location":"Intel/celeron/887 · revision 21621 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-bcee336c4ed0cdd4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6934-r21621","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-bcee336c4ed0cdd4"},{"id":"cw-bd076f9274aaef02","name":"z990","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2003,"process":"0.13 µm","aliases":["Ibm microarchitectures z990"],"fields":[{"key":"Architecture name","value":"z990","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2003,"unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.13,"unit":"µm","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z900","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z9","unit":"","sourceId":"chipswiki-9266-r28844","location":"Ibm/microarchitectures/z990 · revision 28844 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-bd076f9274aaef02","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9266-r28844"],"url":"https://museum.vlsi.kr/objects/cw-bd076f9274aaef02"},{"id":"cw-bd1aab5936811c39","name":"CN3110-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-400bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3110-400 SCP","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-400 SCP","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-400BG868-SCP","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8262-r25922","location":"Cavium/octeon/cn3110-400bg868-scp · revision 25922 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd1aab5936811c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8262-r25922","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-bd1aab5936811c39"},{"id":"cw-bd52c65ab04f9422","name":"Alchemy Au1250-500MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1250-500mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1250-500MGD","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1250-500MGD","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1250-500MGD","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1300 mW","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"2 GB/s","unit":"","sourceId":"chipswiki-443-r924","location":"Alchemy/au1250-500mgd · revision 924 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-bd52c65ab04f9422","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-443-r924"],"url":"https://museum.vlsi.kr/objects/cw-bd52c65ab04f9422"},{"id":"cw-bd5cbdbb900f0df3","name":"Core i7-990X Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-900","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7ee i7-990x"],"fields":[{"key":"Model name","value":"Core i7-990X Extreme Edition","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-990X","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80613005931AA","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80613I7990X","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 13, 2011","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 13, 2011","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-900","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3460,"unit":"MHz","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3733,"unit":"MHz","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBVZ","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gulftown","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":239,"unit":"mm²","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA1366","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7818-r25273","location":"Intel/core i7ee/i7-990x · revision 25273 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd5cbdbb900f0df3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7818-r25273"],"url":"https://museum.vlsi.kr/objects/cw-bd5cbdbb900f0df3"},{"id":"cw-bd8281fccb73b54f","name":"EPYC 74F3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 74f3"],"fields":[{"key":"Model name","value":"EPYC 74F3","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"74F3","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000317","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000317WOF","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24 × 512 KiB","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-748-r1789","location":"Amd/epyc/74f3 · revision 1789 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-bd8281fccb73b54f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-748-r1789"],"url":"https://museum.vlsi.kr/objects/cw-bd8281fccb73b54f"},{"id":"cw-bd85ab095308e734","name":"Xeon Platinum 8260M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8260m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8260M","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8260M","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504201201","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9J","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1461-r4908","location":"Intel/xeon platinum/8260m · revision 4908 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd85ab095308e734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1461-r4908"],"url":"https://museum.vlsi.kr/objects/cw-bd85ab095308e734"},{"id":"cw-bd890cf857b984b7","name":"ThunderX2 CN9960","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","year":2018,"architecture":"Vulcan","process":"16 nm","aliases":["Cavium thunderx2 cn9960"],"fields":[{"key":"Model name","value":"ThunderX2 CN9960","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN9960","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9960-2200LG4077-Y21-G","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9960-2000LG4077-Y21-G","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9960-1800LG4077-Y21-G","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9960-1600LG4077-Y21-G","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX2","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1600,"unit":"MHz","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1800,"unit":"MHz","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2000,"unit":"MHz","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":2200,"unit":"MHz","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vulcan","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-4335-r13948","location":"Cavium/thunderx2/cn9960 · revision 13948 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-bd890cf857b984b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4335-r13948"],"url":"https://museum.vlsi.kr/objects/cw-bd890cf857b984b7"},{"id":"cw-bd90c381c23b1963","name":"Alchemy Au1000-400MCC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1000-400mcc"],"fields":[{"key":"Model name","value":"Alchemy Au1000-400MCC","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1000-400MCC","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1000-400MCC","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2000","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 2001","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"DA","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HA","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HB","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HC","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HD","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.400 GB/s","unit":"","sourceId":"chipswiki-486-r970","location":"Alchemy/au1000-400mcc · revision 970 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bd90c381c23b1963","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-486-r970"],"url":"https://museum.vlsi.kr/objects/cw-bd90c381c23b1963"},{"id":"cw-bd91800ca962fc05","name":"Core i7-2657M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2657m"],"fields":[{"key":"Model name","value":"Core i7-2657M","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2657M","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701040804","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR03S","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7888-r25392","location":"Intel/core i7/i7-2657m · revision 25392 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bd91800ca962fc05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7888-r25392","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-bd91800ca962fc05"},{"id":"cw-bd9d55c16d6b0f86","name":"Xeon Platinum 8280L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8280l"],"fields":[{"key":"Model name","value":"Xeon Platinum 8280L","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8280L","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504228201","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9R","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4.5 TiB","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1454-r4901","location":"Intel/xeon platinum/8280l · revision 4901 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bd9d55c16d6b0f86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1454-r4901"],"url":"https://museum.vlsi.kr/objects/cw-bd9d55c16d6b0f86"},{"id":"cw-bdc379a7d7564d9d","name":"Xeon Platinum 8156","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8156"],"fields":[{"key":"Model name","value":"Xeon Platinum 8156","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8156,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303368800","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AV","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2562-r8830","location":"Intel/xeon platinum/8156 · revision 8830 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-bdc379a7d7564d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2562-r8830"],"url":"https://museum.vlsi.kr/objects/cw-bdc379a7d7564d9d"},{"id":"cw-bdddda3e9b97dcd2","name":"Xeon E-2104G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2104g"],"fields":[{"key":"Model name","value":"Xeon E-2104G","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2104G","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake E","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-2526-r8664","location":"Intel/xeon e/e-2104g · revision 8664 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-bdddda3e9b97dcd2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2526-r8664"],"url":"https://museum.vlsi.kr/objects/cw-bdddda3e9b97dcd2"},{"id":"cw-bdde2cfcab8c759f","name":"Core i3-2395M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2395m"],"fields":[{"key":"Model name","value":"Core i3-2395M","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2395M","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701070900","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0G7","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7996-r25577","location":"Intel/core i3/i3-2395m · revision 25577 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bdde2cfcab8c759f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7996-r25577","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-bdde2cfcab8c759f"},{"id":"cw-bdee41283e1f85ba","name":"Ryzen 7 3700U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 3700u"],"fields":[{"key":"Model name","value":"Ryzen 7 3700U","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3700U","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3700C4T4MFG","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-2184-r7373","reason":"Amd/ryzen 7/3700u · revision 7373 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 10","unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":10,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-2184-r7373","location":"Amd/ryzen 7/3700u · revision 7373 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-bdee41283e1f85ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2184-r7373"],"url":"https://museum.vlsi.kr/objects/cw-bdee41283e1f85ba"},{"id":"cw-be088d7d8d657602","name":"Athlon MP 1900+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp amp1900dms3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1900+","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1900+","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMP1900DMS3C","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 12, 2001","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 12, 2001","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":66,"unit":"W","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8455-r26648","location":"Amd/athlon mp/amp1900dms3c · revision 26648 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be088d7d8d657602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8455-r26648","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-be088d7d8d657602"},{"id":"cw-be0fc166f7991a7a","name":"IA80186","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1985,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 ia80186"],"fields":[{"key":"Model name","value":"IA80186","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"IA80186","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"IA80186B","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1985,"unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8649-r26848","location":"Amd/am186/ia80186 · revision 26848 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be0fc166f7991a7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8649-r26848"],"url":"https://museum.vlsi.kr/objects/cw-be0fc166f7991a7a"},{"id":"cw-be64b81246e2c72e","name":"MSM6260","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2006,"architecture":"ARM9","process":"65 nm","aliases":["Qualcomm msm6xxx msm6260"],"fields":[{"key":"Model name","value":"Qualcomm MSM6260","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6260","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2005,"unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 2006","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":225,"unit":"MHz","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7661-r24924","location":"Qualcomm/msm6xxx/msm6260 · revision 24924 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be64b81246e2c72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7661-r24924"],"url":"https://museum.vlsi.kr/objects/cw-be64b81246e2c72e"},{"id":"cw-be6cd7d4a1e701ea","name":"VY86C06040","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1994,"architecture":"ARM6","process":"0.8 µm","aliases":["Vti vl86cx vy86c06040"],"fields":[{"key":"Model name","value":"VY86C06040","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C06040","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C06040","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 7, 1994","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM6","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM60","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.8,"unit":"µm","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":35530,"unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":5.89,"unit":"mm²","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3,"unit":"","sourceId":"chipswiki-7630-r24885","location":"Vti/vl86cx/vy86c06040 · revision 24885 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-31437-r92358","location":"Template:Packages/vti/tqfp-100 · revision 92358 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-100&oldid=92358","sourceDate":"2017-07-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-31437-r92358","location":"Template:Packages/vti/tqfp-100 · revision 92358 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-be6cd7d4a1e701ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-100&oldid=92358","sourceDate":"2017-07-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7630-r24885","chipswiki-31437-r92358"],"url":"https://museum.vlsi.kr/objects/cw-be6cd7d4a1e701ea"},{"id":"cw-be7e2a83e7367388","name":"Core i3-8100F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8100f"],"fields":[{"key":"Model name","value":"Core i3-8100F","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8100F","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80684I38100F","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2019","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2019","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3986-r12827","location":"Intel/core i3/i3-8100f · revision 12827 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-09. Not an independent measurement.","entityId":"cw-be7e2a83e7367388","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","sourceDate":"2019-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3986-r12827"],"url":"https://museum.vlsi.kr/objects/cw-be7e2a83e7367388"},{"id":"cw-be81947e509aa4c1","name":"Alchemy Au1100-400MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-400mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1100-400MBC","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-400MBC","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-400MBCBA","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-400MBCBC","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-400MBCBD","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-400MBCBE","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-400MBCBF","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BA","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BC","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BD","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BE","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BF","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.22,"unit":"V","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.400 GB/s","unit":"","sourceId":"chipswiki-471-r952","location":"Alchemy/au1100-400mbc · revision 952 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-be81947e509aa4c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-471-r952"],"url":"https://museum.vlsi.kr/objects/cw-be81947e509aa4c1"},{"id":"cw-be873113f9f80013","name":"Xeon W-3175X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3000","year":2019,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-3175x"],"fields":[{"key":"Model name","value":"Xeon W-3175X","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3175X","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80673W3175X","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067304237800","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF6L","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 8, 2018","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 30,, 2019","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3000","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":255,"unit":"W","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-761-r1856","location":"Intel/xeon w/w-3175x · revision 1856 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-be873113f9f80013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-761-r1856"],"url":"https://museum.vlsi.kr/objects/cw-be873113f9f80013"},{"id":"cw-be8ab0bdfba37ca8","name":"ARM7","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":1993,"aliases":["Arm holdings microarchitectures arm7"],"fields":[{"key":"Architecture name","value":"ARM7","unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":1993,"unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM6","unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM8","unit":"","sourceId":"chipswiki-4154-r13231","location":"Arm holdings/microarchitectures/arm7 · revision 13231 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-be8ab0bdfba37ca8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4154-r13231"],"url":"https://museum.vlsi.kr/objects/cw-be8ab0bdfba37ca8"},{"id":"cw-be9d00a50ffb2c28","name":"Ryzen 5 4600HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 4600hs"],"fields":[{"key":"Model name","value":"Ryzen 5 4600HS","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4600HS","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-684-r1678","location":"Amd/ryzen 5/4600hs · revision 1678 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-be9d00a50ffb2c28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-684-r1678"],"url":"https://museum.vlsi.kr/objects/cw-be9d00a50ffb2c28"},{"id":"cw-bf0a8891869d8c42","name":"Alchemy Au1500-400MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1500-400mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1500-400MBC","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-400MBC","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1500-400MBC","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2001","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AB","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AC","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AD","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.400 GB/s","unit":"","sourceId":"chipswiki-480-r964","location":"Alchemy/au1500-400mbc · revision 964 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-bf0a8891869d8c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-480-r964"],"url":"https://museum.vlsi.kr/objects/cw-bf0a8891869d8c42"},{"id":"cw-bf2faa606cf04dbf","name":"AMD-X5-133SDZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-133sdz"],"fields":[{"key":"Model name","value":"AMD-X5-133SDZ","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-133SDZ","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-133SDZ","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133,"unit":"MHz","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SQFP-208","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SQFP","unit":"","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8526-r26721","location":"Amd/am5x86/amd-x5-133sdz · revision 26721 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf2faa606cf04dbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8526-r26721"],"url":"https://museum.vlsi.kr/objects/cw-bf2faa606cf04dbf"},{"id":"cw-bf334d13d4e65923","name":"AMD-K6-III/450AHX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Desktop","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii amd-k6-iii-450ahx"],"fields":[{"key":"Model name","value":"AMD-K6-III/450AHX","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/450AHX","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/450AHX","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 13, 1999","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 13, 1999","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Desktop","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.4,"unit":"V","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8300-r25989","location":"Amd/k6-iii/amd-k6-iii-450ahx · revision 25989 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bf334d13d4e65923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8300-r25989"],"url":"https://museum.vlsi.kr/objects/cw-bf334d13d4e65923"},{"id":"cw-bf45d2015f3cca92","name":"Exynos 7580","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2015,"architecture":"Cortex-A53","process":"28 nm","aliases":["Samsung exynos 7580"],"fields":[{"key":"Model name","value":"Exynos 7580","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7580,"unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2015","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2015","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6843-r21327","location":"Samsung/exynos/7580 · revision 21327 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-bf45d2015f3cca92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6843-r21327"],"url":"https://museum.vlsi.kr/objects/cw-bf45d2015f3cca92"},{"id":"cw-bf512eb1235aa292","name":"Am186ER–25VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–25vc\\w"],"fields":[{"key":"Model name","value":"Am186ER–25VC\\W","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–25VC\\W","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–25VC\\W","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14646-r44707","location":"Amd/am186ex/am186er–25vc\\w · revision 44707 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-bf512eb1235aa292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14646-r44707"],"url":"https://museum.vlsi.kr/objects/cw-bf512eb1235aa292"},{"id":"cw-bf70b3da5f06634e","name":"Helio X23 (MT6797D)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2016,"architecture":"Cortex-A53","process":"20 nm","aliases":["Mediatek helio mt6797d"],"fields":[{"key":"Model name","value":"Helio X23","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X23","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6797D","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6797D","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2, 2016","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2, 2016","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2300,"unit":"MHz","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1850,"unit":"MHz","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1400,"unit":"MHz","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1600","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":780,"unit":"MHz","sourceId":"chipswiki-2212-r7485","location":"Mediatek/helio/mt6797d · revision 7485 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-bf70b3da5f06634e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2212-r7485"],"url":"https://museum.vlsi.kr/objects/cw-bf70b3da5f06634e"},{"id":"cw-bfaec6767a4a7d76","name":"AMD-K6-2/300ANZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300anz-66"],"fields":[{"key":"Model name","value":"K6-2/300ANZ-66","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300ANZ-66","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300ANZ-66","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8378-r26073","location":"Amd/k6-2/k6-2-300anz-66 · revision 26073 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfaec6767a4a7d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8378-r26073"],"url":"https://museum.vlsi.kr/objects/cw-bfaec6767a4a7d76"},{"id":"cw-bfbab73e00e8ceff","name":"Xeon Gold 5218T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5218t"],"fields":[{"key":"Model name","value":"Xeon Gold 5218T","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5218T","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1521-r4973","location":"Intel/xeon gold/5218t · revision 4973 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-bfbab73e00e8ceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1521-r4973"],"url":"https://museum.vlsi.kr/objects/cw-bfbab73e00e8ceff"},{"id":"cw-bfc96f37a6cdb790","name":"AM9080APCB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080apcb"],"fields":[{"key":"Model name","value":"AMD AM9080APCB","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080APCB","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080APCB","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8463-r26656","location":"Amd/am9080/am9080apcb · revision 26656 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfc96f37a6cdb790","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8463-r26656"],"url":"https://museum.vlsi.kr/objects/cw-bfc96f37a6cdb790"},{"id":"cw-bfcbcb08dd4cb375","name":"AMD-K6-IIIE+/450APZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iiie+-450apz"],"fields":[{"key":"Model name","value":"AMD-K6-IIIE+/450APZ","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/450APZ","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/450APZ","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.7,"unit":"V","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":12,"unit":"W","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8314-r26004","location":"Amd/k6-iii+/amd-k6-iiie+-450apz · revision 26004 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-bfcbcb08dd4cb375","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8314-r26004"],"url":"https://museum.vlsi.kr/objects/cw-bfcbcb08dd4cb375"},{"id":"cw-bfd5b834902c95c1","name":"EPYC Embedded 3151","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3151"],"fields":[{"key":"Model name","value":"EPYC Embedded 3151","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3151,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3151BJR48AF","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 8 MiB","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"42.67 GB/s","unit":"","sourceId":"chipswiki-410-r880","location":"Amd/epyc embedded/3151 · revision 880 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4r2","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-bfd5b834902c95c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-410-r880","chipswiki-31098-r91557"],"url":"https://museum.vlsi.kr/objects/cw-bfd5b834902c95c1"},{"id":"cw-c01928fb704c4345","name":"Centriq 2452","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"2400","year":2017,"architecture":"Falkor","process":"10 nm","aliases":["Qualcomm centriq 2452"],"fields":[{"key":"Model name","value":"Centriq 2452","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":2452,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Centriq","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2400,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Falkor","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":18000000000,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":398,"unit":"mm²","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":46,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":46,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4.3125,"unit":"MiB","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2.875,"unit":"MiB","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"46x64 KiB","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.4375,"unit":"MiB","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"46x32 KiB","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":11.5,"unit":"MiB","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x512 KiB","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":57.5,"unit":"MiB","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"11.5x5 MiB","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-7671-r24938","location":"Qualcomm/centriq/2452 · revision 24938 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2808","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2808,"unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":55,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":55,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2808","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c01928fb704c4345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7671-r24938","chipswiki-31367-r92153"],"url":"https://museum.vlsi.kr/objects/cw-c01928fb704c4345"},{"id":"cw-c020c12cbec5ea70","name":"Pentium G4400","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) g4400"],"fields":[{"key":"Model name","value":"Pentium G4400","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4400","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662G4400","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662G4400","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927306","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DC","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HK","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4 3000mhz","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-913-r2499","location":"Intel/pentium (2009)/g4400 · revision 2499 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-05. Not an independent measurement.","entityId":"cw-c020c12cbec5ea70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","sourceDate":"2020-11-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-913-r2499"],"url":"https://museum.vlsi.kr/objects/cw-c020c12cbec5ea70"},{"id":"cw-c036537e2b09dee7","name":"K6-2/350AFQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-350afq"],"fields":[{"key":"Model name","value":"K6-2/350AFQ","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/350AFQ","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/350AFQ","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":349.99,"unit":"MHz","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8365-r26060","location":"Amd/k6-2/k6-2-350afq · revision 26060 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c036537e2b09dee7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8365-r26060"],"url":"https://museum.vlsi.kr/objects/cw-c036537e2b09dee7"},{"id":"cw-c06604381cd68d17","name":"Ryzen Embedded V2546","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V2000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen embedded v2546"],"fields":[{"key":"Model name","value":"Ryzen Embedded V2546","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V2546","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000246","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 10, 2020","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 10, 2020","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V2000","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3950,"unit":"MHz","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Grey Hawk","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6 × 32 KiB","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6 × 32 KiB","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6 × 512 KiB","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 4 MiB","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-881-r2292","location":"Amd/ryzen embedded/v2546 · revision 2292 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-c06604381cd68d17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-881-r2292"],"url":"https://museum.vlsi.kr/objects/cw-c06604381cd68d17"},{"id":"cw-c06e2bd3fa65edf4","name":"Ryzen Threadripper PRO 3995WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3900","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen threadripper pro 3995wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 3995WX","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3995WX","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000087","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000087WOF","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 14, 2020","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3900,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Castle Peak","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":38740000000,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64 × 512 KiB","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16 × 16 MiB","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-384-r829","location":"Amd/ryzen threadripper/pro 3995wx · revision 829 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-c06e2bd3fa65edf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-384-r829","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-c06e2bd3fa65edf4"},{"id":"cw-c07aba73eae70113","name":"Core i5-6600T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6600t"],"fields":[{"key":"Model name","value":"Core i5-6600T","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6600T","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7912-r25450","location":"Intel/core i5/i5-6600t · revision 25450 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c07aba73eae70113","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7912-r25450","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-c07aba73eae70113"},{"id":"cw-c0bfb10632aeabc7","name":"MSM6200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2002,"architecture":"ARM7","process":"180 nm","aliases":["Qualcomm msm6xxx msm6200"],"fields":[{"key":"Model name","value":"Qualcomm MSM6200","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6200","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 20, 2001","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2002","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM7","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM7TDMI","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FBGA-208","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FBGA","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":0,"unit":"KiB","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"No L1$","unit":"","sourceId":"chipswiki-7664-r24930","location":"Qualcomm/msm6xxx/msm6200 · revision 24930 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c0bfb10632aeabc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7664-r24930"],"url":"https://museum.vlsi.kr/objects/cw-c0bfb10632aeabc7"},{"id":"cw-c0d719a29c82962e","name":"Snow Ridge","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2019,"process":"10 nm","aliases":["Intel microarchitectures snow ridge"],"fields":[{"key":"Architecture name","value":"Snow Ridge","unit":"","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Tanner Ridge","unit":"","sourceId":"chipswiki-2166-r7247","location":"Intel/microarchitectures/snow ridge · revision 7247 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-21. Not an independent measurement.","entityId":"cw-c0d719a29c82962e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","sourceDate":"2019-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2166-r7247"],"url":"https://museum.vlsi.kr/objects/cw-c0d719a29c82962e"},{"id":"cw-c0deb91c318dbc9e","name":"EPYC 7281","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7281"],"fields":[{"key":"Model name","value":"EPYC 7281","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7281,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x64 KiB","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x8 MiB","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3824-r12077","location":"Amd/epyc/7281 · revision 12077 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","sourceDate":"2019-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-22. Not an independent measurement.","entityId":"cw-c0deb91c318dbc9e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3824-r12077","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-c0deb91c318dbc9e"},{"id":"cw-c113a3a815e82271","name":"Centriq 2460","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"2400","year":2017,"architecture":"Falkor","process":"10 nm","aliases":["Qualcomm centriq 2460"],"fields":[{"key":"Model name","value":"Centriq 2460","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":2460,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Centriq","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2400,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Falkor","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":18000000000,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":398,"unit":"mm²","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4.5,"unit":"MiB","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":3,"unit":"MiB","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48x64 KiB","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x512 KiB","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":60,"unit":"MiB","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x5 MiB","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-7670-r24937","location":"Qualcomm/centriq/2460 · revision 24937 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2808","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2808,"unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":55,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":55,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2808","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c113a3a815e82271","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7670-r24937","chipswiki-31367-r92153"],"url":"https://museum.vlsi.kr/objects/cw-c113a3a815e82271"},{"id":"cw-c1868d03155ebf0a","name":"Am2045B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 2","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2045b"],"fields":[{"key":"Model name","value":"Am2045B","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2045B","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2045B","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 15, 2007","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 15, 2007","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 2","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":180000000,"unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":344,"unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-896","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-896","unit":"","sourceId":"chipswiki-8662-r26861","location":"Ambric/am2000/am2045b · revision 26861 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c1868d03155ebf0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8662-r26861"],"url":"https://museum.vlsi.kr/objects/cw-c1868d03155ebf0a"},{"id":"cw-c18d47543932ea02","name":"CN5840-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5840-600 SCP","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-600 SCP","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-600BG1521-SCP","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8144-r25803","location":"Cavium/octeon plus/cn5840-600bg1521-scp · revision 25803 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18d47543932ea02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8144-r25803","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-c18d47543932ea02"},{"id":"cw-c18fee4d575765c1","name":"CN5850-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5850-600 NSP","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-600 NSP","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-600BG1521-NSP","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8133-r25792","location":"Cavium/octeon plus/cn5850-600bg1521-nsp · revision 25792 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c18fee4d575765c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8133-r25792","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-c18fee4d575765c1"},{"id":"cw-c196d3795146fc68","name":"Xeon E3-1501L v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1501l v6"],"fields":[{"key":"Model name","value":"Xeon E3-1501L v6","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1501L v6","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3EZ","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P630","unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6412-r20011","location":"Intel/xeon e3/e3-1501l v6 · revision 20011 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-c196d3795146fc68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6412-r20011","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-c196d3795146fc68"},{"id":"cw-c1e98308c4e469fe","name":"Celeron 897","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 897"],"fields":[{"key":"Model name","value":"Celeron 897","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":897,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148201","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085300","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085301","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FF","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08Z","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F6","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V9","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6932-r21619","location":"Intel/celeron/897 · revision 21619 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c1e98308c4e469fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6932-r21619","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-c1e98308c4e469fe"},{"id":"cw-c1f6449ed4630ea5","name":"Celeron N3000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron n3000"],"fields":[{"key":"Model name","value":"Intel Celeron N3000","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3000","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715915","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29J","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2015","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2015","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1040,"unit":"MHz","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2080,"unit":"MHz","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4,"unit":"W","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6857-r21409","location":"Intel/celeron/n3000 · revision 21409 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-c1f6449ed4630ea5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6857-r21409"],"url":"https://museum.vlsi.kr/objects/cw-c1f6449ed4630ea5"},{"id":"cw-c211771e045f1670","name":"AMD-K6-2/266BNZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-266bnz"],"fields":[{"key":"Model name","value":"K6-2/266BNZ","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/266BNZ","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/266BNZ","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-360","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8383-r26078","location":"Amd/k6-2/k6-2-266bnz · revision 26078 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c211771e045f1670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8383-r26078"],"url":"https://museum.vlsi.kr/objects/cw-c211771e045f1670"},{"id":"cw-c22bd2453af3e279","name":"Core M 5Y70","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2014,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y70"],"fields":[{"key":"Model name","value":"Core M 5Y70","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y70","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065801875604","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 2, 2014","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR216","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"E0","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1300000000,"unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":82,"unit":"mm²","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1234","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"MiB","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7812-r25261","location":"Intel/core m/5y70 · revision 25261 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c22bd2453af3e279","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7812-r25261"],"url":"https://museum.vlsi.kr/objects/cw-c22bd2453af3e279"},{"id":"cw-c23612da65c44c3f","name":"Core i7-1065G7","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i7 i7-1065g7"],"fields":[{"key":"Model name","value":"Core i7-1065G7","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-1065G7","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":64,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-989-r2831","location":"Intel/core i7/i7-1065g7 · revision 2831 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-28. Not an independent measurement.","entityId":"cw-c23612da65c44c3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","sourceDate":"2020-07-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-989-r2831"],"url":"https://museum.vlsi.kr/objects/cw-c23612da65c44c3f"},{"id":"cw-c25fdcdda1fe9074","name":"EPYC 7F72","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7f72"],"fields":[{"key":"Model name","value":"EPYC 7F72","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7F72","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000141","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000141WOF","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 14, 2020","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 14, 2020","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":192,"unit":"MiB","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x16 MiB","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-1196-r3738","location":"Amd/epyc/7f72 · revision 3738 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-c25fdcdda1fe9074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1196-r3738"],"url":"https://museum.vlsi.kr/objects/cw-c25fdcdda1fe9074"},{"id":"cw-c29c80c36b1299a7","name":"R-Car E2","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"2nd Gen","year":2016,"architecture":"Cortex-A7","process":"28 nm","aliases":["Renesas r-car e2"],"fields":[{"key":"Model name","value":"R-Car E2","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E2","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A7794","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 22, 2014","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2016","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2nd Gen","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1000,"unit":"MHz","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":780,"unit":"MHz","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A7","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SH-4A","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":3,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":3,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":96,"unit":"KiB","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"3x32 KiB","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"3x32 KiB","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":9.93,"unit":"GiB/s","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX540","unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":1,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":260,"unit":"MHz","sourceId":"chipswiki-7652-r24913","location":"Renesas/r-car/e2 · revision 24913 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-501","unit":"","sourceId":"chipswiki-31424-r92292","location":"Template:Packages/renesas/fcbga-501 · revision 92292 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31424-r92292","location":"Template:Packages/renesas/fcbga-501 · revision 92292 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":501,"unit":"","sourceId":"chipswiki-31424-r92292","location":"Template:Packages/renesas/fcbga-501 · revision 92292 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31424-r92292","location":"Template:Packages/renesas/fcbga-501 · revision 92292 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":21,"unit":"mm","sourceId":"chipswiki-31424-r92292","location":"Template:Packages/renesas/fcbga-501 · revision 92292 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":21,"unit":"mm","sourceId":"chipswiki-31424-r92292","location":"Template:Packages/renesas/fcbga-501 · revision 92292 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c29c80c36b1299a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7652-r24913","chipswiki-31424-r92292"],"url":"https://museum.vlsi.kr/objects/cw-c29c80c36b1299a7"},{"id":"cw-c2cb02a7ed515e2f","name":"Core i7-720QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2009,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7 i7-720qm"],"fields":[{"key":"Model name","value":"Intel Core i7-720QM","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-720QM","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80607I7720QM","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BY80607002907AH","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 24, 2009","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 23, 2009","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1599.99,"unit":"MHz","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBLY","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Clarksfield","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":30,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":774000000,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":296,"unit":"mm²","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.075,"unit":"V","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988A","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G1","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7832-r25322","location":"Intel/core i7/i7-720qm · revision 25322 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c2cb02a7ed515e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7832-r25322"],"url":"https://museum.vlsi.kr/objects/cw-c2cb02a7ed515e2f"},{"id":"cw-c35b15ed6be7eff1","name":"Xeon Platinum 8284","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8284"],"fields":[{"key":"Model name","value":"Xeon Platinum 8284","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8284,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 10, 2019","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 10, 2019","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1837-r6199","location":"Intel/xeon platinum/8284 · revision 6199 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-20. Not an independent measurement.","entityId":"cw-c35b15ed6be7eff1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","sourceDate":"2019-09-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1837-r6199"],"url":"https://museum.vlsi.kr/objects/cw-c35b15ed6be7eff1"},{"id":"cw-c373197f84637f34","name":"MSM6700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2004,"architecture":"ARM9","aliases":["Qualcomm msm6xxx msm6700"],"fields":[{"key":"Model name","value":"Qualcomm MSM6700","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6700","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 22, 2003","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2004,"unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7655-r24916","location":"Qualcomm/msm6xxx/msm6700 · revision 24916 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c373197f84637f34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7655-r24916"],"url":"https://museum.vlsi.kr/objects/cw-c373197f84637f34"},{"id":"cw-c37dce5482cd363c","name":"Post-K","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Fujitsu","year":2018,"aliases":["Fujitsu microarchitectures post-k"],"fields":[{"key":"Architecture name","value":"Post-K","unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Fujitsu","unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":52,"unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-5559-r17991","location":"Fujitsu/microarchitectures/post-k · revision 17991 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-25. Not an independent measurement.","entityId":"cw-c37dce5482cd363c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","sourceDate":"2018-06-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5559-r17991"],"url":"https://museum.vlsi.kr/objects/cw-c37dce5482cd363c"},{"id":"cw-c39d008ebc1c6b8c","name":"Core i3-6300T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6300t"],"fields":[{"key":"Model name","value":"Core i3-6300T","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6300T","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927004","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662I36300T","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662I36300T","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HD","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7978-r25555","location":"Intel/core i3/i3-6300t · revision 25555 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d008ebc1c6b8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7978-r25555","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-c39d008ebc1c6b8c"},{"id":"cw-c39d58c23ad3b7d1","name":"CN5740-600 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-600bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5740-600 SP","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-600 SP","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-600BG1217-SP","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8183-r25842","location":"Cavium/octeon plus/cn5740-600bg1217-sp · revision 25842 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c39d58c23ad3b7d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8183-r25842","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-c39d58c23ad3b7d1"},{"id":"cw-c3fdeefbbeaa8b85","name":"Core i3-6100U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6100u"],"fields":[{"key":"Model name","value":"Core i3-6100U","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6100U","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201931104","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EU","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 520","unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7983-r25560","location":"Intel/core i3/i3-6100u · revision 25560 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c3fdeefbbeaa8b85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7983-r25560","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-c3fdeefbbeaa8b85"},{"id":"cw-c41c5ab692afc05b","name":"Core i5-5675R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5600","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i5 i5-5675r"],"fields":[{"key":"Model name","value":"Intel Core i5-5675R","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-5675R","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802483401","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5600,"unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2AJ","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"G0","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7931-r25473","location":"Intel/core i5/i5-5675r · revision 25473 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c41c5ab692afc05b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7931-r25473","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-c41c5ab692afc05b"},{"id":"cw-c41d65af191e714f","name":"Ryzen Embedded V1404I","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V1000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded v1404i"],"fields":[{"key":"Model name","value":"Ryzen Embedded V1404I","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V1404I","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1404C4T4MFB","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2018","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2018","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Great Horned Owl","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-930-r2555","location":"Amd/ryzen embedded/v1404i · revision 2555 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-c41d65af191e714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-930-r2555"],"url":"https://museum.vlsi.kr/objects/cw-c41d65af191e714f"},{"id":"cw-c433d4203cd3cf83","name":"Xeon E-2276G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2276g"],"fields":[{"key":"Model name","value":"Xeon E-2276G","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2276G","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404227703","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF7M","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4900,"unit":"MHz","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149.6,"unit":"mm²","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2407-r8040","location":"Intel/xeon e/e-2276g · revision 8040 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-c433d4203cd3cf83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2407-r8040"],"url":"https://museum.vlsi.kr/objects/cw-c433d4203cd3cf83"},{"id":"cw-c45fdebe7fbac5a0","name":"Core i3-6100TE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6100te"],"fields":[{"key":"Model name","value":"Core i3-6100TE","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6100TE","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201938603","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LS","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7984-r25561","location":"Intel/core i3/i3-6100te · revision 25561 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c45fdebe7fbac5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7984-r25561","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-c45fdebe7fbac5a0"},{"id":"cw-c46c3ea623eff549","name":"Kunpeng 916 (Hi1616)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"HiSilicon","year":2017,"architecture":"Cortex-A72","process":"16 nm","aliases":["Hisilicon kunpeng hi1616"],"fields":[{"key":"Model name","value":"Hi1616","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Hi1616","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2017","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2017","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Hi16xx","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A72","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x48 KiB","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":71.53,"unit":"GiB/s","sourceId":"chipswiki-2566-r8973","location":"Hisilicon/kunpeng/hi1616 · revision 8973 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-c46c3ea623eff549","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2566-r8973"],"url":"https://museum.vlsi.kr/objects/cw-c46c3ea623eff549"},{"id":"cw-c4be0ade3389f75d","name":"Core i3-7120T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7000","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7120t"],"fields":[{"key":"Model name","value":"Core i3-7120T","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7120T","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35Q","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7000","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":92,"unit":"°C","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7970-r25542","location":"Intel/core i3/i3-7120t · revision 25542 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4be0ade3389f75d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7970-r25542"],"url":"https://museum.vlsi.kr/objects/cw-c4be0ade3389f75d"},{"id":"cw-c4df032e740a7b04","name":"K6-2E/300AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-300amz"],"fields":[{"key":"Model name","value":"K6-2E/300AMZ","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/300AMZ","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/300AMZ","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8325-r26020","location":"Amd/k6-2/k6-2e-300amz · revision 26020 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c4df032e740a7b04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8325-r26020"],"url":"https://museum.vlsi.kr/objects/cw-c4df032e740a7b04"},{"id":"cw-c501de8ddc58d694","name":"Xeon E7-8870","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-8800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-8870"],"fields":[{"key":"Model name","value":"Xeon E7-8870","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8870","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615005757AB","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8800","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3E","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x3 MiB","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7691-r25061","location":"Intel/xeon e7/e7-8870 · revision 25061 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c501de8ddc58d694","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7691-r25061","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-c501de8ddc58d694"},{"id":"cw-c50629dc9dd08349","name":"CN5750-900 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5750-900bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5750-900 SP","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5750-900 SP","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5750-900BG1217-SP","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8163-r25822","location":"Cavium/octeon plus/cn5750-900bg1217-sp · revision 25822 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c50629dc9dd08349","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8163-r25822","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-c50629dc9dd08349"},{"id":"cw-c522fe065af15cb6","name":"Celeron 867","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 867"],"fields":[{"key":"Model name","value":"Celeron 867","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":867,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148901","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701022801","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FK","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V3","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2012","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2012","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6936-r21623","location":"Intel/celeron/867 · revision 21623 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-c522fe065af15cb6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6936-r21623","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-c522fe065af15cb6"},{"id":"cw-c529949d1922ca4e","name":"Xeon Gold 6238R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6238r"],"fields":[{"key":"Model name","value":"Xeon Gold 6238R","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6238R","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1268-r4107","location":"Intel/xeon gold/6238r · revision 4107 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-c529949d1922ca4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1268-r4107"],"url":"https://museum.vlsi.kr/objects/cw-c529949d1922ca4e"},{"id":"cw-c55edd8647ae1c6d","name":"Pentium Gold 4415U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium gold 4415u"],"fields":[{"key":"Model name","value":"Pentium Gold 4415U","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4415U","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067702739932","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR348","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-1821-r6113","location":"Intel/pentium gold/4415u · revision 6113 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","sourceDate":"2019-09-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-29. Not an independent measurement.","entityId":"cw-c55edd8647ae1c6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1821-r6113","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-c55edd8647ae1c6d"},{"id":"cw-c572a1980db04233","name":"Core i7-7510U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7500","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7510u"],"fields":[{"key":"Model name","value":"Core i7-7510U","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7510U","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34F","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 2017","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7500","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7831-r25319","location":"Intel/core i7/i7-7510u · revision 25319 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c572a1980db04233","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7831-r25319","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-c572a1980db04233"},{"id":"cw-c5a135a585252f1f","name":"EPYC 7513","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7513"],"fields":[{"key":"Model name","value":"EPYC 7513","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7513,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000334","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000334WOF","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3650,"unit":"MHz","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-734-r1755","location":"Amd/epyc/7513 · revision 1755 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c5a135a585252f1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-734-r1755"],"url":"https://museum.vlsi.kr/objects/cw-c5a135a585252f1f"},{"id":"cw-c5af46831a226850","name":"Am486SX-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SX","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486sx-33"],"fields":[{"key":"Model name","value":"Am486SX-33","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486SX-33","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX-33","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 1993","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SX","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8539-r26735","location":"Amd/am486/am486sx-33 · revision 26735 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5af46831a226850","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8539-r26735"],"url":"https://museum.vlsi.kr/objects/cw-c5af46831a226850"},{"id":"cw-c5d1462c1cacb4f0","name":"Athlon MP 2200+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2002,"architecture":"K7","process":"130 nm","aliases":["Amd athlon mp amsn2200dkt3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2200+","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2200+","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2200DKT3C","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 27, 2002","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 27, 2002","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":85,"unit":"mm²","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.65,"unit":"V","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8450-r26643","location":"Amd/athlon mp/amsn2200dkt3c · revision 26643 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c5d1462c1cacb4f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8450-r26643","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-c5d1462c1cacb4f0"},{"id":"cw-c5d2890bdc3e63a5","name":"Penryn","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2007,"process":"45 nm","aliases":["Intel microarchitectures penryn (client)"],"fields":[{"key":"Architecture name","value":"Penryn","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November, 2007","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Core","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Nehalem","unit":"","sourceId":"chipswiki-6983-r21823","location":"Intel/microarchitectures/penryn (client) · revision 21823 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-c5d2890bdc3e63a5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6983-r21823"],"url":"https://museum.vlsi.kr/objects/cw-c5d2890bdc3e63a5"},{"id":"cw-c6022b5de31e3f90","name":"CN5830-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5830-600 EXP","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-600 EXP","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-600BG1521-EXP","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8158-r25817","location":"Cavium/octeon plus/cn5830-600bg1521-exp · revision 25817 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6022b5de31e3f90","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8158-r25817","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-c6022b5de31e3f90"},{"id":"cw-c62851f076efd31a","name":"Core i7-2675QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2675qm"],"fields":[{"key":"Model name","value":"Core i7-2675QM","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2675QM","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701065600","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02S","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7883-r25387","location":"Intel/core i7/i7-2675qm · revision 25387 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62851f076efd31a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7883-r25387","chipswiki-31408-r92251"],"url":"https://museum.vlsi.kr/objects/cw-c62851f076efd31a"},{"id":"cw-c62a31492b2b611a","name":"Core i7-2820QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2820qm"],"fields":[{"key":"Model name","value":"Core i7-2820QM","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2820QM","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700834709","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700834912","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR012","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR00U","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2011","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2011","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7874-r25378","location":"Intel/core i7/i7-2820qm · revision 25378 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c62a31492b2b611a","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7874-r25378","chipswiki-31408-r92251","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-c62a31492b2b611a"},{"id":"cw-c65716b6ecac66db","name":"CHA","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Centaur Technology","year":null,"process":"16 nm","aliases":["Centaur microarchitectures cha"],"fields":[{"key":"Architecture name","value":"CHA","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Centaur Technology","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":8,"unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-180-r350","location":"Centaur/microarchitectures/cha · revision 350 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-09-30. Not an independent measurement.","entityId":"cw-c65716b6ecac66db","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","sourceDate":"2022-09-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-180-r350"],"url":"https://museum.vlsi.kr/objects/cw-c65716b6ecac66db"},{"id":"cw-c66e2d4bc8464175","name":"Pentium G4520","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) g4520"],"fields":[{"key":"Model name","value":"Pentium G4520","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4520","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662G4520","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HM","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7784-r25219","location":"Intel/pentium (2009)/g4520 · revision 25219 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c66e2d4bc8464175","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7784-r25219"],"url":"https://museum.vlsi.kr/objects/cw-c66e2d4bc8464175"},{"id":"cw-c685b730bf6792dc","name":"Xeon Gold 6126F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6126f"],"fields":[{"key":"Model name","value":"Xeon Gold 6126F","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6126F","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593400","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KE","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1517-r4969","location":"Intel/xeon gold/6126f · revision 4969 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c685b730bf6792dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1517-r4969"],"url":"https://museum.vlsi.kr/objects/cw-c685b730bf6792dc"},{"id":"cw-c697ad1e195c0c2e","name":"EPYC 7413","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7413"],"fields":[{"key":"Model name","value":"EPYC 7413","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7413,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000323","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000323WOF","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2650,"unit":"MHz","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24 × 512 KiB","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-731-r1752","location":"Amd/epyc/7413 · revision 1752 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-c697ad1e195c0c2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-731-r1752"],"url":"https://museum.vlsi.kr/objects/cw-c697ad1e195c0c2e"},{"id":"cw-c6af14819bb938a5","name":"CN3850-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3850-600 NSP","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-600 NSP","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3850-600BG1521-NSP","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8204-r25863","location":"Cavium/octeon/cn3850-600bg1521-nsp · revision 25863 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c6af14819bb938a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8204-r25863","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-c6af14819bb938a5"},{"id":"cw-c6ba55b3911ed5ab","name":"Piledriver","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2012,"process":"32 nm","aliases":["Amd microarchitectures piledriver"],"fields":[{"key":"Architecture name","value":"Piledriver","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 15, 2012","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Bulldozer","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Steamroller","unit":"","sourceId":"chipswiki-667-r1613","location":"Amd/microarchitectures/piledriver · revision 1613 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-14. Not an independent measurement.","entityId":"cw-c6ba55b3911ed5ab","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","sourceDate":"2021-07-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-667-r1613"],"url":"https://museum.vlsi.kr/objects/cw-c6ba55b3911ed5ab"},{"id":"cw-c6d0f7c52d9eecb2","name":"EPYC 7282","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7282"],"fields":[{"key":"Model name","value":"EPYC 7282","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7282,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000078","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000078WOF","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x16 MiB","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-842-r2215","location":"Amd/epyc/7282 · revision 2215 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-c6d0f7c52d9eecb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-842-r2215"],"url":"https://museum.vlsi.kr/objects/cw-c6d0f7c52d9eecb2"},{"id":"cw-c6dae886100c3a6e","name":"Ryzen 3 5300GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 3 5300ge"],"fields":[{"key":"Model name","value":"Ryzen 3 5300GE","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5300GE","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000262","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 13, 2021","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-708-r1714","location":"Amd/ryzen 3/5300ge · revision 1714 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-c6dae886100c3a6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-708-r1714"],"url":"https://museum.vlsi.kr/objects/cw-c6dae886100c3a6e"},{"id":"cw-c70e9e6a0a1f14cf","name":"CN5734-900 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-900bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5734-900 SP","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-900 SP","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-900BG1217-SP","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8187-r25846","location":"Cavium/octeon plus/cn5734-900bg1217-sp · revision 25846 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c70e9e6a0a1f14cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8187-r25846","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-c70e9e6a0a1f14cf"},{"id":"cw-c7335d2e18fa29fd","name":"Atom x3-C3200RK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"C3000","year":2015,"architecture":"Silvermont","process":"28 nm","aliases":["Intel atom x3 x3-c3200rk"],"fields":[{"key":"Model name","value":"Atom x3-C3200RK","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x3-C3200RK","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x3","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C3000","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Silvermont","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SoFIA","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SoFIA","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8049-r25685","location":"Intel/atom x3/x3-c3200rk · revision 25685 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7335d2e18fa29fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8049-r25685"],"url":"https://museum.vlsi.kr/objects/cw-c7335d2e18fa29fd"},{"id":"cw-c737002e91cd69bf","name":"FastMATH 2 GHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intrinsity","year":2002,"architecture":"FashMATH","process":"130 nm","aliases":["Intrinsity fastmath fastmath-2"],"fields":[{"key":"Model name","value":"FastMATH 2 GHz","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intrinsity","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FastMATH-2","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2001,"unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2002,"unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"FastMATH","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"RapidIO","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"FashMATH","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"Dynamic CMOS","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-670","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"256 blocks × 16 words/block","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"256 blocks × 16 words/block","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7689-r24984","location":"Intrinsity/fastmath/fastmath-2 · revision 24984 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c737002e91cd69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7689-r24984"],"url":"https://museum.vlsi.kr/objects/cw-c737002e91cd69bf"},{"id":"cw-c73eb581b5cbac93","name":"Xeon W-3245","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3245"],"fields":[{"key":"Model name","value":"Xeon W-3245","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3245","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504152900","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFD","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1706-r5939","location":"Intel/xeon w/w-3245 · revision 5939 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-c73eb581b5cbac93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1706-r5939"],"url":"https://museum.vlsi.kr/objects/cw-c73eb581b5cbac93"},{"id":"cw-c741ac76e32cad14","name":"Ryzen 3 PRO 2200G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 pro 2200g"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 2200G","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2200G","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD220BC5M4MFB","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4910-r15839","location":"Amd/ryzen 3/pro 2200g · revision 15839 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","sourceDate":"2018-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-07. Not an independent measurement.","entityId":"cw-c741ac76e32cad14","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4910-r15839","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-c741ac76e32cad14"},{"id":"cw-c74b71a8c32f8b0c","name":"Core i5-9500T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-9500t"],"fields":[{"key":"Model name","value":"Core i5-9500T","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-9500T","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403362510","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF4D","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-9000","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1620-r5488","location":"Intel/core i5/i5-9500t · revision 5488 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-13. Not an independent measurement.","entityId":"cw-c74b71a8c32f8b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","sourceDate":"2019-11-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1620-r5488"],"url":"https://museum.vlsi.kr/objects/cw-c74b71a8c32f8b0c"},{"id":"cw-c794d44143753ec8","name":"Xeon Platinum 8176","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8176"],"fields":[{"key":"Model name","value":"Xeon Platinum 8176","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8176,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303314700","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37A","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1467-r4914","location":"Intel/xeon platinum/8176 · revision 4914 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-c794d44143753ec8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1467-r4914"],"url":"https://museum.vlsi.kr/objects/cw-c794d44143753ec8"},{"id":"cw-c7969f2661a9939b","name":"Embedded G-Series T40E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t40e"],"fields":[{"key":"Model name","value":"Embedded G-Series T40E","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T40E","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET40EFSB22GVE","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 23, 2011","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6.4,"unit":"W","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6250","unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":280,"unit":"MHz","sourceId":"chipswiki-423-r895","location":"Amd/embedded/t40e · revision 895 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-c7969f2661a9939b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-423-r895","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-c7969f2661a9939b"},{"id":"cw-c7a8b35b144e3ef8","name":"Celeron J4005","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Goldmont Plus","process":"14 nm","aliases":["Intel celeron j4005"],"fields":[{"key":"Model name","value":"Celeron J4005","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J4005","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068003067416","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3S5","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":112,"unit":"KiB","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 600","unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":250,"unit":"MHz","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":700,"unit":"MHz","sourceId":"chipswiki-917-r2516","location":"Intel/celeron/j4005 · revision 2516 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","sourceDate":"2020-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1090","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1090,"unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-27. Not an independent measurement.","entityId":"cw-c7a8b35b144e3ef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-917-r2516","chipswiki-31338-r92075"],"url":"https://museum.vlsi.kr/objects/cw-c7a8b35b144e3ef8"},{"id":"cw-c7ae875cdbadc234","name":"Pentium Gold G5620","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel pentium gold g5620"],"fields":[{"key":"Model name","value":"Pentium Gold G5620","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G5620","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":4000,"unit":"MHz","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-2848-r9553","location":"Intel/pentium gold/g5620 · revision 9553 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-c7ae875cdbadc234","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2848-r9553"],"url":"https://museum.vlsi.kr/objects/cw-c7ae875cdbadc234"},{"id":"cw-c7d8c7c83cd6c273","name":"Alchemy Au1500-333MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1500-333mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1500-333MBD","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-333MBD","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1500-333MBD","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2001","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AB","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AC","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AD","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-483-r967","location":"Alchemy/au1500-333mbd · revision 967 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-c7d8c7c83cd6c273","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-483-r967"],"url":"https://museum.vlsi.kr/objects/cw-c7d8c7c83cd6c273"},{"id":"cw-c7f113b1ebcbd5b8","name":"Cortex-A17","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2014,"aliases":["Arm holdings microarchitectures cortex-a17"],"fields":[{"key":"Architecture name","value":"Cortex-A17","unit":"","sourceId":"chipswiki-4149-r13226","location":"Arm holdings/microarchitectures/cortex-a17 · revision 13226 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-c7f113b1ebcbd5b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4149-r13226","location":"Arm holdings/microarchitectures/cortex-a17 · revision 13226 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-c7f113b1ebcbd5b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4149-r13226","location":"Arm holdings/microarchitectures/cortex-a17 · revision 13226 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-c7f113b1ebcbd5b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 11, 2014","unit":"","sourceId":"chipswiki-4149-r13226","location":"Arm holdings/microarchitectures/cortex-a17 · revision 13226 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-c7f113b1ebcbd5b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-4149-r13226","location":"Arm holdings/microarchitectures/cortex-a17 · revision 13226 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-c7f113b1ebcbd5b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A12","unit":"","sourceId":"chipswiki-4149-r13226","location":"Arm holdings/microarchitectures/cortex-a17 · revision 13226 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-c7f113b1ebcbd5b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4149-r13226"],"url":"https://museum.vlsi.kr/objects/cw-c7f113b1ebcbd5b8"},{"id":"cw-c7f5ce5d9302f0a3","name":"CN5860-1000 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-1000bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5860-1000 EXP","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-1000 EXP","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-1000BG1521-EXP","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8125-r25784","location":"Cavium/octeon plus/cn5860-1000bg1521-exp · revision 25784 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c7f5ce5d9302f0a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8125-r25784","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-c7f5ce5d9302f0a3"},{"id":"cw-c82c2dd07934fa5b","name":"Xeon Gold 5119T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5119t"],"fields":[{"key":"Model name","value":"Xeon Gold 5119T","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5119T","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3MN","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-268-r543","location":"Intel/xeon gold/5119t · revision 543 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-c82c2dd07934fa5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-268-r543"],"url":"https://museum.vlsi.kr/objects/cw-c82c2dd07934fa5b"},{"id":"cw-c83de53d37c27f85","name":"CN5840-800 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-800bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5840-800 EXP","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-800 EXP","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-800BG1521-EXP","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8143-r25802","location":"Cavium/octeon plus/cn5840-800bg1521-exp · revision 25802 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c83de53d37c27f85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8143-r25802","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-c83de53d37c27f85"},{"id":"cw-c83ed78e9229aaea","name":"Pentium Gold G4620","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G4600","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium gold g4620"],"fields":[{"key":"Model name","value":"Pentium Gold G4620","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4620","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677G4620","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35E","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G4600","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7585-r24644","location":"Intel/pentium gold/g4620 · revision 24644 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-c83ed78e9229aaea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7585-r24644"],"url":"https://museum.vlsi.kr/objects/cw-c83ed78e9229aaea"},{"id":"cw-c8754e6f1fbff7f6","name":"PEZY-SC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"PEZY","year":2014,"process":"28 nm","aliases":["Pezy pezy-scx pezy-sc"],"fields":[{"key":"Model name","value":"PEZY-SC","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"PEZY","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PEZY-SC","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Supercomputer","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2013,"unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2014","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PEZY-SCx","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":733.33,"unit":"MHz","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3730000000,"unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":411.6,"unit":"mm²","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1024,"unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8192,"unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":32,"unit":"KiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"2x16 KiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":32,"unit":"KiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"2x16 KiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x64 KiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":3,"unit":"MiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":2,"unit":"MiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"1024x2 KiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"per processor element","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":1,"unit":"MiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"512x2 KiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"per 2 processor elements","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":4,"unit":"MiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x2 MiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"per city","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 2)","value":8,"unit":"MiB","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 2)","value":"4x2 MiB","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity — Cache (section 2)","value":"per prefecture","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":127.156,"unit":"GiB/s","sourceId":"chipswiki-4785-r15454","location":"Pezy/pezy-scx/pezy-sc · revision 15454 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2112","unit":"","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2112,"unit":"","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":47.5,"unit":"mm","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":47.5,"unit":"mm","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.05,"unit":"mm","sourceId":"chipswiki-31352-r92105","location":"Template:Packages/pezy/fcbga-2112 · revision 92105 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-c8754e6f1fbff7f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4785-r15454","chipswiki-31352-r92105"],"url":"https://museum.vlsi.kr/objects/cw-c8754e6f1fbff7f6"},{"id":"cw-c87e77657c1eaadc","name":"Duron 1400 (Applebred)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2003,"architecture":"K7","process":"130 nm","aliases":["Amd duron dhd1400dlv1c"],"fields":[{"key":"Model name","value":"Duron 1400","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1400","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD1400DLV1C","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2003","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2003","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266.66 MT/s","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Applebred","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":80.89,"unit":"mm²","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":57,"unit":"W","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8424-r26132","location":"Amd/duron/dhd1400dlv1c · revision 26132 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c87e77657c1eaadc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8424-r26132"],"url":"https://museum.vlsi.kr/objects/cw-c87e77657c1eaadc"},{"id":"cw-c8a08125b4404377","name":"Helio P10 M (MT6755M)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2016,"architecture":"Cortex-A53","process":"28 nm","aliases":["Mediatek helio mt6755m"],"fields":[{"key":"Model name","value":"Helio P10 M","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P10 M","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6755M","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6755M","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 1, 2015","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2016","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1200,"unit":"MHz","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":6.95,"unit":"GiB/s","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T860","unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-1294-r4328","location":"Mediatek/helio/mt6755m · revision 4328 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-c8a08125b4404377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1294-r4328"],"url":"https://museum.vlsi.kr/objects/cw-c8a08125b4404377"},{"id":"cw-c8a2e2e1fa71dba5","name":"AMD-K5-PR150ABR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1997,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr150abr"],"fields":[{"key":"Model name","value":"AMD-K5-PR150ABR","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR150ABR","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR150ABR","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":105,"unit":"MHz","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"60 MT/s","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":2,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8398-r26094","location":"Amd/k5/amd-k5-pr150abr · revision 26094 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8a2e2e1fa71dba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8398-r26094"],"url":"https://museum.vlsi.kr/objects/cw-c8a2e2e1fa71dba5"},{"id":"cw-c8ba273da8456db0","name":"Core i5-2430M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2430m"],"fields":[{"key":"Model name","value":"Core i5-2430M","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2430M","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700995505","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085800","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04W","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR072","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7961-r25511","location":"Intel/core i5/i5-2430m · revision 25511 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-c8ba273da8456db0","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7961-r25511","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-c8ba273da8456db0"},{"id":"cw-c957de9ea0af68cd","name":"Cannon Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2018,"process":"10 nm","aliases":["Intel microarchitectures cannon lake"],"fields":[{"key":"Architecture name","value":"Cannon Lake","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 15, 2018","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way?","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cannon Lake Y","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Kaby Lake","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Ice Lake","unit":"","sourceId":"chipswiki-2036-r6890","location":"Intel/microarchitectures/cannon lake · revision 6890 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-05. Not an independent measurement.","entityId":"cw-c957de9ea0af68cd","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","sourceDate":"2019-08-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2036-r6890"],"url":"https://museum.vlsi.kr/objects/cw-c957de9ea0af68cd"},{"id":"cw-c96584290c37ceee","name":"eMAG 8180","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ampere Computing","series":"eMAG 1","year":2018,"architecture":"Skylark","process":"16 nm","aliases":["Ampere computing emag 8180"],"fields":[{"key":"Model name","value":"eMAG 8180","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ampere Computing","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8180,"unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 5, 2018","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 8, 2018","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"eMAG","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"eMAG 1","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylark","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.85,"unit":"V","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x32 MiB","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-4753-r15334","location":"Ampere computing/emag/8180 · revision 15334 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-3211","unit":"","sourceId":"chipswiki-31305-r92007","location":"Template:Packages/ampere computing/fcbga-3211 · revision 92007 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fampere%20computing%2Ffcbga-3211&oldid=92007","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31305-r92007","location":"Template:Packages/ampere computing/fcbga-3211 · revision 92007 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fampere%20computing%2Ffcbga-3211&oldid=92007","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":3211,"unit":"","sourceId":"chipswiki-31305-r92007","location":"Template:Packages/ampere computing/fcbga-3211 · revision 92007 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fampere%20computing%2Ffcbga-3211&oldid=92007","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":50,"unit":"mm","sourceId":"chipswiki-31305-r92007","location":"Template:Packages/ampere computing/fcbga-3211 · revision 92007 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fampere%20computing%2Ffcbga-3211&oldid=92007","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":50,"unit":"mm","sourceId":"chipswiki-31305-r92007","location":"Template:Packages/ampere computing/fcbga-3211 · revision 92007 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-c96584290c37ceee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fampere%20computing%2Ffcbga-3211&oldid=92007","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4753-r15334","chipswiki-31305-r92007"],"url":"https://museum.vlsi.kr/objects/cw-c96584290c37ceee"},{"id":"cw-c974263eb5d7043e","name":"Xeon Platinum 9282","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"9200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 9282"],"fields":[{"key":"Model name","value":"Xeon Platinum 9282","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9282,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":9200,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Walker Pass","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake AP","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":56,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":112,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":400,"unit":"W","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"56x32 KiB","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"56x32 KiB","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":56,"unit":"MiB","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"56x1 MiB","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":77,"unit":"MiB","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"56x1.375 MiB","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":12,"unit":"","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":262.26,"unit":"GiB/s","sourceId":"chipswiki-274-r552","location":"Intel/xeon platinum/9282 · revision 552 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-31. Not an independent measurement.","entityId":"cw-c974263eb5d7043e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","sourceDate":"2022-07-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-274-r552"],"url":"https://museum.vlsi.kr/objects/cw-c974263eb5d7043e"},{"id":"cw-c9e343f72ca95db1","name":"K6-2E+/500ACR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-500acr"],"fields":[{"key":"Model name","value":"K6-2E+/500ACR","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/500ACR","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/500ACR","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18.5,"unit":"W","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1008-r2859","location":"Amd/k6-2+/k6-2e+-500acr · revision 2859 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-c9e343f72ca95db1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1008-r2859","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-c9e343f72ca95db1"},{"id":"cw-ca1419506dc0b457","name":"Athlon MP 2800+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2003,"architecture":"K7","process":"130 nm","aliases":["Amd athlon mp amsn2800dut4c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2800+","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2800+","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2800DUT4C","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 6, 2003","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 6, 2003","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133,"unit":"MHz","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Barton","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":10,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":54300000,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":101,"unit":"mm²","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8445-r26638","location":"Amd/athlon mp/amsn2800dut4c · revision 26638 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1419506dc0b457","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8445-r26638","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-ca1419506dc0b457"},{"id":"cw-ca1a59e33a361f22","name":"Core i3-6102E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6102e"],"fields":[{"key":"Model name","value":"Core i3-6102E","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6102E","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202400105","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DX","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7982-r25559","location":"Intel/core i3/i3-6102e · revision 25559 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca1a59e33a361f22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7982-r25559","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ca1a59e33a361f22"},{"id":"cw-ca22fafe5a551a04","name":"Core i7-820QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2009,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7 i7-820qm"],"fields":[{"key":"Model name","value":"Intel Core i7-820QM","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-820QM","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BY80607002904AK","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 24, 2009","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 23, 2009","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1733.33,"unit":"MHz","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3066.66,"unit":"MHz","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBLX","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Clarksfield","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":30,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":774000000,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":296,"unit":"mm²","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.075,"unit":"V","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988A","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G1","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7130-r22499","location":"Intel/core i7/i7-820qm · revision 22499 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-ca22fafe5a551a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7130-r22499"],"url":"https://museum.vlsi.kr/objects/cw-ca22fafe5a551a04"},{"id":"cw-ca23540820dc2a25","name":"Core i3-8100T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8100t"],"fields":[{"key":"Model name","value":"Core i3-8100T","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8100T","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377415","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3Y8","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":82,"unit":"°C","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6452-r20191","location":"Intel/core i3/i3-8100t · revision 20191 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-ca23540820dc2a25","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6452-r20191"],"url":"https://museum.vlsi.kr/objects/cw-ca23540820dc2a25"},{"id":"cw-ca25eba80396b668","name":"Gen5.75 (Ironlake)","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2010,"process":"45 nm","aliases":["Intel microarchitectures gen5.75"],"fields":[{"key":"Architecture name","value":"Gen5.75","unit":"","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January, 2010","unit":"","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen5","unit":"","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen6","unit":"","sourceId":"chipswiki-15962-r52691","location":"Intel/microarchitectures/gen5.75 · revision 52691 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-ca25eba80396b668","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15962-r52691"],"url":"https://museum.vlsi.kr/objects/cw-ca25eba80396b668"},{"id":"cw-ca698d8aedd8ff87","name":"Pentium 927","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) 927"],"fields":[{"key":"Model name","value":"Pentium 927","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":927,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148801","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085000","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085001","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FJ","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08W","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F3","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V6","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-7797-r25235","location":"Intel/pentium (2009)/927 · revision 25235 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca698d8aedd8ff87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7797-r25235","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-ca698d8aedd8ff87"},{"id":"cw-ca7083ab41467adc","name":"CN3120-300 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-300bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3120-300 CP","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-300 CP","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-300BG868-CP","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8253-r25913","location":"Cavium/octeon/cn3120-300bg868-cp · revision 25913 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca7083ab41467adc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8253-r25913","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-ca7083ab41467adc"},{"id":"cw-ca72a38b01c2c28e","name":"CN5740-1000 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-1000bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5740-1000 SSP","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-1000 SSP","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-1000BG1217-SSP","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8184-r25843","location":"Cavium/octeon plus/cn5740-1000bg1217-ssp · revision 25843 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca72a38b01c2c28e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8184-r25843","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-ca72a38b01c2c28e"},{"id":"cw-ca733ea548b8eec7","name":"C80186-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 c80186-1"],"fields":[{"key":"Model name","value":"C80186-1","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C80186-1","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"C80186-1","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"C80186-1B","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2.5 MT/s","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8654-r26853","location":"Amd/am186/c80186-1 · revision 26853 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ca733ea548b8eec7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8654-r26853"],"url":"https://museum.vlsi.kr/objects/cw-ca733ea548b8eec7"},{"id":"cw-ca83744f861b30cf","name":"Xeon Silver 4110","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon silver 4110"],"fields":[{"key":"Model name","value":"Xeon Silver 4110","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4110,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806734110","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303561400","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GH","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1451-r4895","location":"Intel/xeon silver/4110 · revision 4895 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ca83744f861b30cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1451-r4895"],"url":"https://museum.vlsi.kr/objects/cw-ca83744f861b30cf"},{"id":"cw-cab97a39db334192","name":"Exynos 990","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2020,"architecture":"Mongoose 5","process":"7 nm","aliases":["Samsung exynos 990"],"fields":[{"key":"Model name","value":"Exynos 9999","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":990,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 23, 2019","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2020,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Mongoose 5","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Mongoose 5","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","alternatives":[{"value":"12 GiB","sourceId":"chipswiki-551-r1140","reason":"Samsung/exynos/990 · revision 1140 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":192,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"2x32 KiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":1,"unit":"MiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"2x512 KiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"16-way set associative","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 1)","value":"2x1 MiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"16-way set associative","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"2x256 KiB","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR5-5500","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"44 GB/s","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G77","unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":800,"unit":"MHz","sourceId":"chipswiki-551-r1140","location":"Samsung/exynos/990 · revision 1140 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-cab97a39db334192","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-551-r1140"],"url":"https://museum.vlsi.kr/objects/cw-cab97a39db334192"},{"id":"cw-cabe7ba181398e88","name":"Core i7-975 Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-900","year":2009,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7ee i7-975"],"fields":[{"key":"Model name","value":"Core i7-975 Extreme Edition","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-975","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80601002274AA","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80601975","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 2, 2009","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Jun 2, 2009","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-900","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3333,"unit":"MHz","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBEQ","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"X58","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Bloomfield","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D0","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":731000000,"unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":263,"unit":"mm²","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA1366","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7820-r25275","location":"Intel/core i7ee/i7-975 · revision 25275 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cabe7ba181398e88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7820-r25275"],"url":"https://museum.vlsi.kr/objects/cw-cabe7ba181398e88"},{"id":"cw-cac6960a6ecda9b1","name":"CN5850-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5850-600 EXP","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-600 EXP","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-600BG1521-EXP","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8134-r25793","location":"Cavium/octeon plus/cn5850-600bg1521-exp · revision 25793 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cac6960a6ecda9b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8134-r25793","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-cac6960a6ecda9b1"},{"id":"cw-cacd6fa3f9fbe519","name":"Am486DX4-120NV8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4V","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-120nv8t"],"fields":[{"key":"Model name","value":"Am486DX4-120NV8T","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-120NV8T","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-120NV8T","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4V","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":120,"unit":"MHz","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8552-r26748","location":"Amd/am486/am486dx4-120nv8t · revision 26748 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cacd6fa3f9fbe519","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8552-r26748"],"url":"https://museum.vlsi.kr/objects/cw-cacd6fa3f9fbe519"},{"id":"cw-caf0a6fd7719bb33","name":"Am486DXLV-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1993,"architecture":"80486","aliases":["Amd am486 am486dxlv-33"],"fields":[{"key":"Model name","value":"Am486DXLV-33","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DXLV-33","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A8048DXLV-33","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1993","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DXLV","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8542-r26738","location":"Amd/am486/am486dxlv-33 · revision 26738 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-caf0a6fd7719bb33","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8542-r26738"],"url":"https://museum.vlsi.kr/objects/cw-caf0a6fd7719bb33"},{"id":"cw-cb07f3037a96b652","name":"FastMATH 3 GHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intrinsity","year":null,"architecture":"FashMATH","process":"130 nm","aliases":["Intrinsity fastmath fastmath-3"],"fields":[{"key":"Model name","value":"FastMATH 3 GHz","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intrinsity","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FastMATH-3","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2003,"unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"FastMATH","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"RapidIO","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"FashMATH","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"Dynamic CMOS","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.25,"unit":"V","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-670","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"256 blocks × 16 words/block","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"256 blocks × 16 words/block","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7688-r24983","location":"Intrinsity/fastmath/fastmath-3 · revision 24983 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb07f3037a96b652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7688-r24983"],"url":"https://museum.vlsi.kr/objects/cw-cb07f3037a96b652"},{"id":"cw-cb2d2d67b16e3bbe","name":"Atom Z600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z600","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z600"],"fields":[{"key":"Model name","value":"Atom Z600","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z600","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609004002AC","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZP","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z600","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":1.3,"unit":"W","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-25 °C","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":200,"unit":"MHz","sourceId":"chipswiki-8059-r25695","location":"Intel/atom/z600 · revision 25695 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb2d2d67b16e3bbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8059-r25695","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-cb2d2d67b16e3bbe"},{"id":"cw-cb3019ea667b6695","name":"Xeon Platinum 8260L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8260l"],"fields":[{"key":"Model name","value":"Xeon Platinum 8260L","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8260L","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504201001","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9G","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4.5 TiB","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1463-r4910","location":"Intel/xeon platinum/8260l · revision 4910 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cb3019ea667b6695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1463-r4910"],"url":"https://museum.vlsi.kr/objects/cw-cb3019ea667b6695"},{"id":"cw-cb365f845ec90020","name":"Xeon W-3275","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3275"],"fields":[{"key":"Model name","value":"Xeon W-3275","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3275","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504153101","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFF","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1703-r5935","location":"Intel/xeon w/w-3275 · revision 5935 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-cb365f845ec90020","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1703-r5935"],"url":"https://museum.vlsi.kr/objects/cw-cb365f845ec90020"},{"id":"cw-cb48619e205fd507","name":"Core i3-2375M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2013,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2375m"],"fields":[{"key":"Model name","value":"Core i3-2375M","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2375M","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701313100","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0U4","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2013","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2013","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8001-r25582","location":"Intel/core i3/i3-2375m · revision 25582 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb48619e205fd507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8001-r25582","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-cb48619e205fd507"},{"id":"cw-cb4a2ca819f7c4d3","name":"Core i7-8809G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-8809g"],"fields":[{"key":"Model name","value":"Core i7-8809G","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8809G","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake G","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","alternatives":[{"value":"DDR4-2400","sourceId":"chipswiki-5570-r18114","reason":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / type 2. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory ECC — Memory controller (section 1)","value":"No","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 1)","value":64,"unit":"GiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":1,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":2,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller / HBM 2 (section 2)","value":"HBM2","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller / HBM 2 (section 2)","value":4,"unit":"GiB","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller / HBM 2 (section 2)","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Integrated graphics (section 1)","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Integrated graphics (section 1)","value":24,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Integrated graphics (section 1)","value":3,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Integrated graphics (section 1)","value":350,"unit":"MHz","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Integrated graphics (section 1)","value":1100,"unit":"MHz","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Discrete graphics (section 2)","value":"Radeon RX Vega M GH","unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Discrete graphics (section 2)","value":24,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Discrete graphics (section 2)","value":1063,"unit":"MHz","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Discrete graphics (section 2)","value":1190,"unit":"MHz","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Discrete graphics (section 2)","value":6,"unit":"","sourceId":"chipswiki-5570-r18114","location":"Intel/core i7/i7-8809g · revision 18114 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-06-18. Not an independent measurement.","entityId":"cw-cb4a2ca819f7c4d3","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","sourceDate":"2018-06-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5570-r18114"],"url":"https://museum.vlsi.kr/objects/cw-cb4a2ca819f7c4d3"},{"id":"cw-cb5b8e972e391835","name":"Core i5-8400B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8400b"],"fields":[{"key":"Model name","value":"Core i5-8400B","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8400B","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-4957-r16040","location":"Intel/core i5/i5-8400b · revision 16040 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-cb5b8e972e391835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4957-r16040"],"url":"https://museum.vlsi.kr/objects/cw-cb5b8e972e391835"},{"id":"cw-cb70c35358bbb3eb","name":"Atom Z670","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z650","year":2011,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z670"],"fields":[{"key":"Model name","value":"Atom Z670","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z670","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609007293AA","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC2P","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 11, 2011","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 11, 2011","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z650","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Oak Trail","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":3,"unit":"W","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8051-r25687","location":"Intel/atom/z670 · revision 25687 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cb70c35358bbb3eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8051-r25687","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-cb70c35358bbb3eb"},{"id":"cw-cbb318ea29ac4004","name":"Scorpio Engine","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2017,"architecture":"Enhanced Jaguar","process":"16 nm","aliases":["Microsoft scorpio engine"],"fields":[{"key":"Model name","value":"Scorpio Engine","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Scorpio Engine","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Console","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2017","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 7, 2017","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Enhanced Jaguar","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Enhanced Jaguar","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7000000000,"unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":359,"unit":"mm²","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"GDDR5-6800","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":12,"unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":12,"unit":"","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":304,"unit":"GiB/s","sourceId":"chipswiki-2182-r7359","location":"Microsoft/scorpio engine · revision 7359 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-cbb318ea29ac4004","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2182-r7359"],"url":"https://museum.vlsi.kr/objects/cw-cbb318ea29ac4004"},{"id":"cw-cbc250387f3a7ddb","name":"Celeron B830","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b830"],"fields":[{"key":"Model name","value":"Celeron B830","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B830","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700848702","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0HR","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2011","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2011","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6925-r21611","location":"Intel/celeron/b830 · revision 21611 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-cbc250387f3a7ddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6925-r21611","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-cbc250387f3a7ddb"},{"id":"cw-cbc98a1b7b77302f","name":"Core i9-9900T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i9-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i9 i9-9900t"],"fields":[{"key":"Model name","value":"Core i9-9900T","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i9-9900T","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403874122","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRG1B","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-9000","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1373-r4595","location":"Intel/core i9/i9-9900t · revision 4595 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-cbc98a1b7b77302f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1373-r4595","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-cbc98a1b7b77302f"},{"id":"cw-cc1cfec3be0a7e76","name":"POWER9 02CY489","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy489"],"fields":[{"key":"Model name","value":"02CY489","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY489","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY489","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.8,"unit":"GHz","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":72,"unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4.5,"unit":"MiB","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"9x512 KiB","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":90,"unit":"MiB","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"9x10 MiB","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3947-r12591","location":"Ibm/power/02cy489 · revision 12591 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-cc1cfec3be0a7e76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3947-r12591"],"url":"https://museum.vlsi.kr/objects/cw-cc1cfec3be0a7e76"},{"id":"cw-cc2d723591eb233f","name":"Cortex-A715","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2022,"process":"7 nm","aliases":["Arm holdings microarchitectures cortex-a715"],"fields":[{"key":"Architecture name","value":"Cortex-A715","unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2022,"unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A710","unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Hunter","unit":"","sourceId":"chipswiki-307-r622","location":"Arm holdings/microarchitectures/cortex-a715 · revision 622 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-cc2d723591eb233f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-307-r622"],"url":"https://museum.vlsi.kr/objects/cw-cc2d723591eb233f"},{"id":"cw-cc3572883e6d5a82","name":"Meteor Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2023,"process":"Intel 4","aliases":["Intel microarchitectures meteor lake"],"fields":[{"key":"Architecture name","value":"Meteor Lake","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2023,"unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"Intel 4","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Redwood Cove","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Crestmont","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Raptor Lake","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Arrow Lake","unit":"","sourceId":"chipswiki-495-r989","location":"Intel/microarchitectures/meteor lake · revision 989 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-04. Not an independent measurement.","entityId":"cw-cc3572883e6d5a82","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","sourceDate":"2022-03-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-495-r989"],"url":"https://museum.vlsi.kr/objects/cw-cc3572883e6d5a82"},{"id":"cw-cc3e891b7a38e679","name":"Athlon MP 1200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp ahx1200ams3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1200","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1200","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AHX1200AMS3C","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54.7,"unit":"W","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8461-r26654","location":"Amd/athlon mp/ahx1200ams3c · revision 26654 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cc3e891b7a38e679","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8461-r26654"],"url":"https://museum.vlsi.kr/objects/cw-cc3e891b7a38e679"},{"id":"cw-cca122852afed6da","name":"Helio X20 (MT6797)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2016,"architecture":"Cortex-A53","process":"20 nm","aliases":["Mediatek helio mt6797"],"fields":[{"key":"Model name","value":"MediaTek Helio X20","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X20","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6797","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6797","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 12, 2015","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2016","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2100,"unit":"MHz","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1850,"unit":"MHz","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1400,"unit":"MHz","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1600","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"12.8 GB/s (11.92 GiB/s)","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":780,"unit":"MHz","sourceId":"chipswiki-769-r1884","location":"Mediatek/helio/mt6797 · revision 1884 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-03. Not an independent measurement.","entityId":"cw-cca122852afed6da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","sourceDate":"2021-05-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-769-r1884"],"url":"https://museum.vlsi.kr/objects/cw-cca122852afed6da"},{"id":"cw-ccaebb1869c8211a","name":"CN3860-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3860-600 NSP","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-600 NSP","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-600BG1521-NSP","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8195-r25854","location":"Cavium/octeon/cn3860-600bg1521-nsp · revision 25854 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccaebb1869c8211a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8195-r25854","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-ccaebb1869c8211a"},{"id":"cw-ccb5a192ec07ff2b","name":"Core i3-2367M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2367m"],"fields":[{"key":"Model name","value":"Core i3-2367M","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2367M","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047904","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CV","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8004-r25585","location":"Intel/core i3/i3-2367m · revision 25585 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ccb5a192ec07ff2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8004-r25585","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-ccb5a192ec07ff2b"},{"id":"cw-ccd4c685b3ecc0fd","name":"Am186ES–20KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–20ki\\w"],"fields":[{"key":"Model name","value":"Am186ES–20KI\\W","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–20KI\\W","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–20KI\\W","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14626-r44687","location":"Amd/am186ex/am186es–20ki\\w · revision 44687 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ccd4c685b3ecc0fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14626-r44687"],"url":"https://museum.vlsi.kr/objects/cw-ccd4c685b3ecc0fd"},{"id":"cw-cd0412b18cb3ea3c","name":"LuJiaZui","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Zhaoxin","year":2019,"process":"16 nm","aliases":["Zhaoxin microarchitectures lujiazui"],"fields":[{"key":"Architecture name","value":"LuJiaZui","unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"WuDaoKou","unit":"","sourceId":"chipswiki-1575-r5202","location":"Zhaoxin/microarchitectures/lujiazui · revision 5202 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-12. Not an independent measurement.","entityId":"cw-cd0412b18cb3ea3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","sourceDate":"2019-12-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1575-r5202"],"url":"https://museum.vlsi.kr/objects/cw-cd0412b18cb3ea3c"},{"id":"cw-cd053cc89c61af4c","name":"Am186ED–33KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–33kc\\w"],"fields":[{"key":"Model name","value":"Am186ED–33KC\\W","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–33KC\\W","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–33KC\\W","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14666-r44727","location":"Amd/am186ex/am186ed–33kc\\w · revision 44727 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-cd053cc89c61af4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14666-r44727"],"url":"https://museum.vlsi.kr/objects/cw-cd053cc89c61af4c"},{"id":"cw-cd1299af724a5bb2","name":"Xeon E7-2850","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-2800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-2850"],"fields":[{"key":"Model name","value":"Xeon E7-2850","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-2850","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007452AA","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-2800","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3W","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.56,"unit":"MiB","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.4 MiB","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7705-r25075","location":"Intel/xeon e7/e7-2850 · revision 25075 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd1299af724a5bb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7705-r25075","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-cd1299af724a5bb2"},{"id":"cw-cd5407aae34f0b37","name":"CN5740-900 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-900bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5740-900 SSP","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-900 SSP","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-900BG1217-SSP","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8178-r25837","location":"Cavium/octeon plus/cn5740-900bg1217-ssp · revision 25837 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd5407aae34f0b37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8178-r25837","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-cd5407aae34f0b37"},{"id":"cw-cd598788f23a1ec1","name":"Xeon Gold 6248R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6248r"],"fields":[{"key":"Model name","value":"Xeon Gold 6248R","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6248R","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-972-r2740","location":"Intel/xeon gold/6248r · revision 2740 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-31. Not an independent measurement.","entityId":"cw-cd598788f23a1ec1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","sourceDate":"2020-08-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-972-r2740"],"url":"https://museum.vlsi.kr/objects/cw-cd598788f23a1ec1"},{"id":"cw-cd6ed57b5ac46d2d","name":"ECM3532","kind":"sku","entityType":"product-model","subtype":"soc","company":"Eta Compute","year":2020,"architecture":"Cortex-M3","aliases":["Eta compute ecm353x ecm3532"],"fields":[{"key":"Model name","value":"ECM3532","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Eta Compute","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"ECM3532","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 12, 2020","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2020","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ECM353x","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7-M","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-M3","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1295-r4329","location":"Eta compute/ecm353x/ecm3532 · revision 4329 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-12. Not an independent measurement.","entityId":"cw-cd6ed57b5ac46d2d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","sourceDate":"2020-02-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1295-r4329"],"url":"https://museum.vlsi.kr/objects/cw-cd6ed57b5ac46d2d"},{"id":"cw-cd83fc2eb56e75a0","name":"AMD-K5-PR100ABR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"SSA/5","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr100abr"],"fields":[{"key":"Model name","value":"AMD-K5-PR100ABR","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR100ABR","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR100ABR","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 17, 1996","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 17, 1996","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"SSA/5","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":99.99,"unit":"MHz","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SSA/5","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":0,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":161,"unit":"mm²","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8403-r26099","location":"Amd/k5/amd-k5-pr100abr · revision 26099 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cd83fc2eb56e75a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8403-r26099"],"url":"https://museum.vlsi.kr/objects/cw-cd83fc2eb56e75a0"},{"id":"cw-cd8ec9496dba06ea","name":"Core i7-8565U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-8565u"],"fields":[{"key":"Model name","value":"Core i7-8565U","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8565U","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8068404064405","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SREJP","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"W0","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","alternatives":[{"value":"64 GiB","sourceId":"chipswiki-886-r2303","reason":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-886-r2303","location":"Intel/core i7/i7-8565u · revision 2303 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-25. Not an independent measurement.","entityId":"cw-cd8ec9496dba06ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","sourceDate":"2020-12-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-886-r2303"],"url":"https://museum.vlsi.kr/objects/cw-cd8ec9496dba06ea"},{"id":"cw-cda904ba2c2c718e","name":"z9","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2006,"process":"90 nm","aliases":["Ibm microarchitectures z9"],"fields":[{"key":"Architecture name","value":"z9","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2006,"unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z990","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z10","unit":"","sourceId":"chipswiki-13216-r38680","location":"Ibm/microarchitectures/z9 · revision 38680 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-cda904ba2c2c718e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13216-r38680"],"url":"https://museum.vlsi.kr/objects/cw-cda904ba2c2c718e"},{"id":"cw-cdbbfc487ff018b8","name":"POWER4","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2001,"process":"180 nm","aliases":["Ibm microarchitectures power4"],"fields":[{"key":"Architecture name","value":"POWER4","unit":"","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2001,"unit":"","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER3","unit":"","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER5","unit":"","sourceId":"chipswiki-9917-r31532","location":"Ibm/microarchitectures/power4 · revision 31532 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-cdbbfc487ff018b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9917-r31532"],"url":"https://museum.vlsi.kr/objects/cw-cdbbfc487ff018b8"},{"id":"cw-cdc4c6ae7433a0ec","name":"Electronic Arrays 9002 (EA9002)","kind":"sku","entityType":"product-model","subtype":"sku","company":"Electronic Arrays","year":1976,"aliases":["EA9002"],"fields":[{"key":"Model name","value":"Electronic Arrays 9002 (EA9002)","unit":"","sourceId":"chipswiki-1619-r5482","location":"EA9002 · revision 5482 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-14. Not an independent measurement.","entityId":"cw-cdc4c6ae7433a0ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=EA9002&oldid=5482","sourceDate":"2019-11-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Electronic Arrays","unit":"","sourceId":"chipswiki-1619-r5482","location":"EA9002 · revision 5482 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-14. Not an independent measurement.","entityId":"cw-cdc4c6ae7433a0ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=EA9002&oldid=5482","sourceDate":"2019-11-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Electronic Arrays","unit":"","sourceId":"chipswiki-1619-r5482","location":"EA9002 · revision 5482 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-14. Not an independent measurement.","entityId":"cw-cdc4c6ae7433a0ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=EA9002&oldid=5482","sourceDate":"2019-11-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1976,"unit":"","sourceId":"chipswiki-1619-r5482","location":"EA9002 · revision 5482 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-14. Not an independent measurement.","entityId":"cw-cdc4c6ae7433a0ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=EA9002&oldid=5482","sourceDate":"2019-11-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":"8-bit","unit":"","sourceId":"chipswiki-1619-r5482","location":"EA9002 · revision 5482 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-14. Not an independent measurement.","entityId":"cw-cdc4c6ae7433a0ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=EA9002&oldid=5482","sourceDate":"2019-11-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1619-r5482"],"url":"https://museum.vlsi.kr/objects/cw-cdc4c6ae7433a0ec"},{"id":"cw-cde866c4e0cef601","name":"Ryzen 3 PRO 1300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen PRO","year":null,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 pro 1300"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 1300","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 1300","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD130BBBM4KAE","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen PRO","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Summit Ridge","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-7355-r23750","location":"Amd/ryzen 3/pro 1300 · revision 23750 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-cde866c4e0cef601","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7355-r23750","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-cde866c4e0cef601"},{"id":"cw-cdfe375669df6063","name":"Core i3-8000T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8000t"],"fields":[{"key":"Model name","value":"Core i3-8000T","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8000T","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YR","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2018","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2018","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-5450-r17746","location":"Intel/core i3/i3-8000t · revision 17746 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-cdfe375669df6063","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5450-r17746"],"url":"https://museum.vlsi.kr/objects/cw-cdfe375669df6063"},{"id":"cw-ce01d599c883995e","name":"Sophon BM1680","kind":"sku","entityType":"product-model","subtype":"sku","company":"Bitmain","year":2017,"process":"28 nm","aliases":["Bitmain sophon bm1680"],"fields":[{"key":"Model name","value":"Sophon BM1680","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Bitmain","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"BM1680","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 25, 2017","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Sophon","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":41,"unit":"W","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-5068-r16483","location":"Bitmain/sophon/bm1680 · revision 16483 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1599","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1599,"unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":33,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":33,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.18,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-ce01d599c883995e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5068-r16483","chipswiki-31370-r92158"],"url":"https://museum.vlsi.kr/objects/cw-ce01d599c883995e"},{"id":"cw-ce180aae338167b4","name":"Xeon E3-1545M v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1545m v5"],"fields":[{"key":"Model name","value":"Xeon E3-1545M v5","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1545M v5","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"JQ8066202193209","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QU","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics P580","unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7757-r25139","location":"Intel/xeon e3/e3-1545m v5 · revision 25139 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce180aae338167b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7757-r25139","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ce180aae338167b4"},{"id":"cw-ce42f97064baabf6","name":"QorIQ P1024","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2012,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1024"],"fields":[{"key":"Model name","value":"QorIQ P1024","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1024","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":533,"unit":"MHz","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8095-r25754","location":"Freescale/qoriq/p1024 · revision 25754 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-561","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":561,"unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce42f97064baabf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8095-r25754","chipswiki-31376-r92171"],"url":"https://museum.vlsi.kr/objects/cw-ce42f97064baabf6"},{"id":"cw-ce529ffb2b52c300","name":"Ryzen 5 5500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 5500u"],"fields":[{"key":"Model name","value":"Ryzen 5 5500U","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5500U","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000375","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lucienne","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":104,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1800,"unit":"MHz","sourceId":"chipswiki-712-r1718","location":"Amd/ryzen 5/5500u · revision 1718 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-ce529ffb2b52c300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-712-r1718"],"url":"https://museum.vlsi.kr/objects/cw-ce529ffb2b52c300"},{"id":"cw-ce5353e361d9ea8b","name":"Xeon E-2176M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2176m"],"fields":[{"key":"Model name","value":"Xeon E-2176M","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2176M","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068403359116","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YX","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-4958-r16042","location":"Intel/xeon e/e-2176m · revision 16042 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-ce5353e361d9ea8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4958-r16042","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ce5353e361d9ea8b"},{"id":"cw-ce645216db23dc5b","name":"Am486DX2-100V16B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1995,"architecture":"80486","process":"350 nm","aliases":["Amd am486 am486dx2-100v16b"],"fields":[{"key":"Model name","value":"Am486DX2-100V16B","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-100V16B","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-100V16B","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8571-r26769","location":"Amd/am486/am486dx2-100v16b · revision 26769 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ce645216db23dc5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8571-r26769"],"url":"https://museum.vlsi.kr/objects/cw-ce645216db23dc5b"},{"id":"cw-ce9aa8f1a4543bc0","name":"Opteron A1170","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"A1100","year":2016,"architecture":"Cortex-A57","process":"28 nm","aliases":["Amd opteron a1170"],"fields":[{"key":"Model name","value":"Opteron A1170","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Global Foundries","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A1170","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"OA1170AQD8NAD","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2014","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2016","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Opteron","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A1100","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Seattle","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":32,"unit":"W","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":80,"unit":"°C","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 48 KiB","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"3-way set associative","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 1 MiB","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"29.9 GB/s","unit":"","sourceId":"chipswiki-957-r2707","location":"Amd/opteron/a1170 · revision 2707 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP1","unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1021,"unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":27,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":27,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.46,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-ce9aa8f1a4543bc0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-957-r2707","chipswiki-31113-r91580"],"url":"https://museum.vlsi.kr/objects/cw-ce9aa8f1a4543bc0"},{"id":"cw-cee2554521ef4d53","name":"Tiger Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2020,"process":"10 nm","aliases":["Intel microarchitectures tiger lake"],"fields":[{"key":"Architecture name","value":"Tiger Lake","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 2, 2020","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1280,"unit":"KiB","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tiger Lake U","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tiger Lake H","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Ice Lake (client)","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alder Lake","unit":"","sourceId":"chipswiki-674-r1643","location":"Intel/microarchitectures/tiger lake · revision 1643 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-cee2554521ef4d53","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-674-r1643"],"url":"https://museum.vlsi.kr/objects/cw-cee2554521ef4d53"},{"id":"cw-cee8853b415fc802","name":"Xeon Gold 6130F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6130f"],"fields":[{"key":"Model name","value":"Xeon Gold 6130F","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6130F","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593300","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KD","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1512-r4964","location":"Intel/xeon gold/6130f · revision 4964 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cee8853b415fc802","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1512-r4964"],"url":"https://museum.vlsi.kr/objects/cw-cee8853b415fc802"},{"id":"cw-cf391af41360a885","name":"Pentium 4405U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) 4405u"],"fields":[{"key":"Model name","value":"Pentium 4405U","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4405U","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201930905","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EX","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 3, 2015","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7800-r25239","location":"Intel/pentium (2009)/4405u · revision 25239 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf391af41360a885","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7800-r25239","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-cf391af41360a885"},{"id":"cw-cf681dc79a2c15be","name":"K3V2","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","year":2012,"architecture":"Cortex-A9","process":"40 nm","aliases":["Hisilicon k3 k3v2"],"fields":[{"key":"Model name","value":"K3V2","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K3V2","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Hi3620","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 2012","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 2012","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K3","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":600000000,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR2-900","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":6.71,"unit":"GiB/s","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"GC4000","unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":16,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":480,"unit":"MHz","sourceId":"chipswiki-5200-r17057","location":"Hisilicon/k3/k3v2 · revision 17057 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","sourceDate":"2018-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TFBGA-576","unit":"","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TFBGA","unit":"","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":576,"unit":"","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":11.9,"unit":"mm","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":11.9,"unit":"mm","sourceId":"chipswiki-31402-r92235","location":"Template:Packages/hisilicon/tfbga-576 · revision 92235 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-21. Not an independent measurement.","entityId":"cw-cf681dc79a2c15be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5200-r17057","chipswiki-31402-r92235"],"url":"https://museum.vlsi.kr/objects/cw-cf681dc79a2c15be"},{"id":"cw-cf8766d259e2930b","name":"Core i7-2630QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2630qm"],"fields":[{"key":"Model name","value":"Core i7-2630QM","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2630QM","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700837005","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02Y","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2011","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2011","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7895-r25399","location":"Intel/core i7/i7-2630qm · revision 25399 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-cf8766d259e2930b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7895-r25399","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-cf8766d259e2930b"},{"id":"cw-cfaf4aa8e8c30365","name":"Core i5-8310Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2019,"architecture":"Amber Lake","process":"14 nm","aliases":["Intel core i5 i5-8310y"],"fields":[{"key":"Model name","value":"Core i5-8310Y","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8310Y","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739888","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SREKP","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 4, 2019","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 4, 2019","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Amber Lake","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Amber Lake","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Amber Lake Y","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":7,"unit":"W","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 617","unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3698-r11040","location":"Intel/core i5/i5-8310y · revision 11040 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-cfaf4aa8e8c30365","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3698-r11040"],"url":"https://museum.vlsi.kr/objects/cw-cfaf4aa8e8c30365"},{"id":"cw-cfbb08f80cbd7687","name":"Xeon Gold 6238","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6238"],"fields":[{"key":"Model name","value":"Xeon Gold 6238","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6238,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":22,"unit":"MiB","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x1 MiB","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30.25,"unit":"MiB","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x1.375 MiB","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-517-r1050","location":"Intel/xeon gold/6238 · revision 1050 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-cfbb08f80cbd7687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-517-r1050"],"url":"https://museum.vlsi.kr/objects/cw-cfbb08f80cbd7687"},{"id":"cw-cfbf5583bf1ac1b6","name":"Xeon Gold 6252","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6252"],"fields":[{"key":"Model name","value":"Xeon Gold 6252","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6252,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194401","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806956252","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF91","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1478-r4926","location":"Intel/xeon gold/6252 · revision 4926 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-cfbf5583bf1ac1b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1478-r4926"],"url":"https://museum.vlsi.kr/objects/cw-cfbf5583bf1ac1b6"},{"id":"cw-d00105bac22f2cda","name":"Athlon Silver 3050U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2020,"architecture":"Zen","process":"14 nm","aliases":["Amd athlon silver 3050u"],"fields":[{"key":"Model name","value":"Athlon Silver 3050U","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3050U","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3050C4T2OFG","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon Silver","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dali","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 2","unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1384-r4658","location":"Amd/athlon silver/3050u · revision 4658 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-14. Not an independent measurement.","entityId":"cw-d00105bac22f2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","sourceDate":"2020-01-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1384-r4658"],"url":"https://museum.vlsi.kr/objects/cw-d00105bac22f2cda"},{"id":"cw-d01892e31e29464b","name":"Core i3-6120T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":null,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 6120t"],"fields":[{"key":"Model name","value":"Core i3-6120T","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6120T","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927104","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HF","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 9, 2016","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8020-r25602","location":"Intel/core i3/6120t · revision 25602 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d01892e31e29464b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8020-r25602","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-d01892e31e29464b"},{"id":"cw-d02b66878c196463","name":"ARMADA 618","kind":"sku","entityType":"product-model","subtype":"soc","company":"Marvell","series":"600","year":2010,"architecture":"Sheeva PJ4","process":"55 nm","aliases":["Marvell armada 618"],"fields":[{"key":"Model name","value":"ARMADA 618","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Marvell","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":618,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"88AP618","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 16, 2010","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 16, 2010","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ARMADA 600","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":600,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv6","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sheeva PJ4","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"ARMADA","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sheeva PJ4","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":55,"unit":"nm","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCCBGA-640","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCCBGA","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":7.942,"unit":"GiB/s","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"GC860","unit":"","sourceId":"chipswiki-7675-r24970","location":"Marvell/armada/618 · revision 24970 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d02b66878c196463","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7675-r24970"],"url":"https://museum.vlsi.kr/objects/cw-d02b66878c196463"},{"id":"cw-d04a13799951e8a4","name":"Core m5-6Y54","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"m-6Y","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core m m5-6y54"],"fields":[{"key":"Model name","value":"Core m5-6Y54","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"m5-6Y54","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8066201930524","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EM","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core m5","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"m-6Y","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake Y","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":5,"unit":"°C","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 515","unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-4982-r16104","location":"Intel/core m/m5-6y54 · revision 16104 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d04a13799951e8a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4982-r16104"],"url":"https://museum.vlsi.kr/objects/cw-d04a13799951e8a4"},{"id":"cw-d06db3f299a4460b","name":"QorIQ P1012","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2010,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1012"],"fields":[{"key":"Model name","value":"QorIQ P1012","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1012","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 7, 2009","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2010","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8105-r25764","location":"Freescale/qoriq/p1012 · revision 25764 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA-II","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d06db3f299a4460b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8105-r25764","chipswiki-31374-r92168"],"url":"https://museum.vlsi.kr/objects/cw-d06db3f299a4460b"},{"id":"cw-d0b4127b014a47fd","name":"Core i7-940XM Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-900","year":2010,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7ee i7-940xm"],"fields":[{"key":"Model name","value":"Core i7-940XM Extreme Edition","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-940XM","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BY80607002526AE","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 5, 2010","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-900","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3333.33,"unit":"MHz","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSC","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Clarksfield","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":30,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":774000000,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":296,"unit":"mm²","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G1","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-1572-r5184","location":"Intel/core i7ee/i7-940xm · revision 5184 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-13. Not an independent measurement.","entityId":"cw-d0b4127b014a47fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","sourceDate":"2019-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1572-r5184"],"url":"https://museum.vlsi.kr/objects/cw-d0b4127b014a47fd"},{"id":"cw-d10581c3cbde6056","name":"CN3850-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-500bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3850-500 NSP","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-500 NSP","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3850-500BG1521-NSP","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8207-r25866","location":"Cavium/octeon/cn3850-500bg1521-nsp · revision 25866 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d10581c3cbde6056","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8207-r25866","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-d10581c3cbde6056"},{"id":"cw-d1174a536c5ffed8","name":"SHAVE v2.0","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Movidius","year":2011,"process":"65 nm","aliases":["Movidius microarchitectures shave v2.0"],"fields":[{"key":"Architecture name","value":"SHAVE v2.0","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2011,"unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"VLLIW","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SHAVE","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"KiB","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / l1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"chip","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"chip","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"SHAVE v1.0","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"SHAVE v3.0","unit":"","sourceId":"chipswiki-838-r2189","location":"Movidius/microarchitectures/shave v2.0 · revision 2189 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-20. Not an independent measurement.","entityId":"cw-d1174a536c5ffed8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","sourceDate":"2021-01-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-838-r2189"],"url":"https://museum.vlsi.kr/objects/cw-d1174a536c5ffed8"},{"id":"cw-d16114c978142484","name":"K6-2+/500ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2+-500acz"],"fields":[{"key":"Model name","value":"K6-2+/500ACZ","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2+/500ACZ","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2+/500ACZ","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16,"unit":"W","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Mobile","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-995-r2841","location":"Amd/k6-2+/k6-2+-500acz · revision 2841 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-d16114c978142484","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-995-r2841","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-d16114c978142484"},{"id":"cw-d1990d57ba557ebb","name":"Pentium B960","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) b960"],"fields":[{"key":"Model name","value":"Pentium B960","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B960","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700997701","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701123900","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07V","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0C9","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 3, 2011","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 3, 2011","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-3814-r11982","location":"Intel/pentium (2009)/b960 · revision 11982 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","sourceDate":"2019-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-03. Not an independent measurement.","entityId":"cw-d1990d57ba557ebb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3814-r11982","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d1990d57ba557ebb"},{"id":"cw-d1ac62e566bd157f","name":"Core i3-7007U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7007","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7007u"],"fields":[{"key":"Model name","value":"Intel Core i3-7007U","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7007U","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR344","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 2017","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7007","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","alternatives":[{"value":"64 GiB","sourceId":"chipswiki-7976-r25553","reason":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7976-r25553","location":"Intel/core i3/i3-7007u · revision 25553 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1ac62e566bd157f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7976-r25553","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-d1ac62e566bd157f"},{"id":"cw-d1b6bd38415572c7","name":"Kaby Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2016,"process":"14 nm","aliases":["Intel microarchitectures kaby lake"],"fields":[{"key":"Architecture name","value":"Kaby Lake","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 30, 2016","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake R","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake G","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake DT","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 7","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake X","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / core name 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 8","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"core name 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Skylake","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Coffee Lake","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cannon Lake","unit":"","sourceId":"chipswiki-297-r598","location":"Intel/microarchitectures/kaby lake · revision 598 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-d1b6bd38415572c7","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-297-r598"],"url":"https://museum.vlsi.kr/objects/cw-d1b6bd38415572c7"},{"id":"cw-d1c76cf1f5190390","name":"Core i7-640UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-640um"],"fields":[{"key":"Model name","value":"Intel Core i7-640UM","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-640UM","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617003888AD","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1199.99,"unit":"MHz","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBMM","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSR","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7849-r25348","location":"Intel/core i7/i7-640um · revision 25348 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1c76cf1f5190390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7849-r25348","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-d1c76cf1f5190390"},{"id":"cw-d1dfba223c97faa8","name":"Core i7-2535QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2535qm"],"fields":[{"key":"Model name","value":"Core i7-2535QM","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2535QM","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700838300","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CL","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7902-r25406","location":"Intel/core i7/i7-2535qm · revision 25406 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d1dfba223c97faa8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7902-r25406","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-d1dfba223c97faa8"},{"id":"cw-d1f4c687e7926e9f","name":"Xeon E5-4640 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4640 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4640 v4","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4640 v4","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002061701","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SC","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x256 KiB","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x2.5 MiB","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-4468-r14395","location":"Intel/xeon e5/e5-4640 v4 · revision 14395 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-13. Not an independent measurement.","entityId":"cw-d1f4c687e7926e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","sourceDate":"2018-11-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4468-r14395"],"url":"https://museum.vlsi.kr/objects/cw-d1f4c687e7926e9f"},{"id":"cw-d20acab8b5cf910e","name":"CN3010-300 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3010-300bg525-scp"],"fields":[{"key":"Model name","value":"Cavium CN3010-300 SCP","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3010-300 SCP","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3010-300BG525-SCP","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-525","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.986,"unit":"GiB/s","sourceId":"chipswiki-8274-r25934","location":"Cavium/octeon/cn3010-300bg525-scp · revision 25934 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d20acab8b5cf910e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8274-r25934"],"url":"https://museum.vlsi.kr/objects/cw-d20acab8b5cf910e"},{"id":"cw-d237e99cfd01af12","name":"Pentium Gold G5600T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel pentium gold g5600t"],"fields":[{"key":"Model name","value":"Pentium Gold G5600T","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G5600T","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377714","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YF","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2849-r9558","location":"Intel/pentium gold/g5600t · revision 9558 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-d237e99cfd01af12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2849-r9558"],"url":"https://museum.vlsi.kr/objects/cw-d237e99cfd01af12"},{"id":"cw-d241909f7815461e","name":"CN5850-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5850-600 SCP","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-600 SCP","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-600BG1521-SCP","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8132-r25791","location":"Cavium/octeon plus/cn5850-600bg1521-scp · revision 25791 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d241909f7815461e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8132-r25791","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-d241909f7815461e"},{"id":"cw-d26a234ce5bb2b4a","name":"CN5850-1000 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-1000bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5850-1000 SCP","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-1000 SCP","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-1000BG1521-SCP","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8135-r25794","location":"Cavium/octeon plus/cn5850-1000bg1521-scp · revision 25794 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d26a234ce5bb2b4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8135-r25794","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-d26a234ce5bb2b4a"},{"id":"cw-d28328ac6a32e22f","name":"Atom Z650","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z650","year":2011,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z650"],"fields":[{"key":"Model name","value":"Atom Z650","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z650","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609007296AA","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC2Q","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 11, 2011","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 11, 2011","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z650","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Oak Trail","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":3,"unit":"W","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8052-r25688","location":"Intel/atom/z650 · revision 25688 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d28328ac6a32e22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8052-r25688","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-d28328ac6a32e22f"},{"id":"cw-d2dc4c116f68bc00","name":"Am186ER–40VI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–40vi\\w"],"fields":[{"key":"Model name","value":"Am186ER–40VI\\W","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–40VI\\W","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–40VI\\W","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14637-r44698","location":"Amd/am186ex/am186er–40vi\\w · revision 44698 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d2dc4c116f68bc00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14637-r44698"],"url":"https://museum.vlsi.kr/objects/cw-d2dc4c116f68bc00"},{"id":"cw-d306eae2a68db9c3","name":"K6-2/450ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-450ack"],"fields":[{"key":"Model name","value":"K6-2/450ACK","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/450ACK","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/450ACK","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8347-r26042","location":"Amd/k6-2/k6-2-450ack · revision 26042 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d306eae2a68db9c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8347-r26042"],"url":"https://museum.vlsi.kr/objects/cw-d306eae2a68db9c3"},{"id":"cw-d3485df908f1e350","name":"Cortex-A34","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":null,"aliases":["Arm holdings microarchitectures cortex-a34"],"fields":[{"key":"Architecture name","value":"Cortex-A34","unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8 AArch64","unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"128KB-1MB","unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"architecture scope","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture scope","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A35","unit":"","sourceId":"chipswiki-559-r1175","location":"Arm holdings/microarchitectures/cortex-a34 · revision 1175 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-04. Not an independent measurement.","entityId":"cw-d3485df908f1e350","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","sourceDate":"2021-12-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-559-r1175"],"url":"https://museum.vlsi.kr/objects/cw-d3485df908f1e350"},{"id":"cw-d34bf40b8f20643f","name":"QorIQ P1016","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":null,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1016"],"fields":[{"key":"Model name","value":"QorIQ P1016","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1016","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8101-r25760","location":"Freescale/qoriq/p1016 · revision 25760 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-561","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":561,"unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d34bf40b8f20643f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8101-r25760","chipswiki-31376-r92171"],"url":"https://museum.vlsi.kr/objects/cw-d34bf40b8f20643f"},{"id":"cw-d35aaa909968f82d","name":"Snapdragon 665","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2019,"architecture":"Cortex-A73","process":"11 nm","aliases":["Qualcomm snapdragon 600 665"],"fields":[{"key":"Model name","value":"Snapdragon 665","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SM6125","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 9, 2019","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 9, 2019","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 600","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":4500,"unit":"MHz","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1800,"unit":"MHz","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 260 Gold","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 260 Silver","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":11,"unit":"nm","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 610","unit":"","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2.4,"unit":"GHz","sourceId":"chipswiki-588-r1359","location":"Qualcomm/snapdragon 600/665 · revision 1359 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-12. Not an independent measurement.","entityId":"cw-d35aaa909968f82d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","sourceDate":"2021-10-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-588-r1359"],"url":"https://museum.vlsi.kr/objects/cw-d35aaa909968f82d"},{"id":"cw-d3726350b1b136ed","name":"Goldmont Plus","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2017,"process":"14 nm","aliases":["Intel microarchitectures goldmont plus"],"fields":[{"key":"Architecture name","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"December 11, 2017","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"4 Cores","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"4 Cores","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake Refresh","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Goldmont","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Tremont","unit":"","sourceId":"chipswiki-1233-r3879","location":"Intel/microarchitectures/goldmont plus · revision 3879 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d3726350b1b136ed","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1233-r3879"],"url":"https://museum.vlsi.kr/objects/cw-d3726350b1b136ed"},{"id":"cw-d37561614b11bb38","name":"Xeon D-1571","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1571"],"fields":[{"key":"Model name","value":"Xeon D-1571","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1571","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570310","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2M0","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.5 MiB","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3737-r11446","location":"Intel/xeon d/d-1571 · revision 11446 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-d37561614b11bb38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3737-r11446"],"url":"https://museum.vlsi.kr/objects/cw-d37561614b11bb38"},{"id":"cw-d3cc084be597bf79","name":"Xeon Gold 5117","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5117"],"fields":[{"key":"Model name","value":"Xeon Gold 5117","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5117,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37S","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-270-r545","location":"Intel/xeon gold/5117 · revision 545 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-d3cc084be597bf79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-270-r545"],"url":"https://museum.vlsi.kr/objects/cw-d3cc084be597bf79"},{"id":"cw-d3ce028bf2a4b3bd","name":"AMD-X5-160","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":null,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-160"],"fields":[{"key":"Model name","value":"AMD-X5-160","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-160","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1996,"unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":160,"unit":"MHz","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8521-r26714","location":"Amd/am5x86/amd-x5-160 · revision 26714 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3ce028bf2a4b3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8521-r26714"],"url":"https://museum.vlsi.kr/objects/cw-d3ce028bf2a4b3bd"},{"id":"cw-d3f37d99623fcf6c","name":"CN3120-550 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-550bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3120-550 NSP","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-550 NSP","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-550BG868-NSP","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8239-r25899","location":"Cavium/octeon/cn3120-550bg868-nsp · revision 25899 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d3f37d99623fcf6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8239-r25899","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-d3f37d99623fcf6c"},{"id":"cw-d41895248c47e875","name":"Core i3-2393M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2393m"],"fields":[{"key":"Model name","value":"Core i3-2393M","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2393M","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701084601","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR09S","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 14, 2011","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 14, 2011","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7998-r25579","location":"Intel/core i3/i3-2393m · revision 25579 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d41895248c47e875","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7998-r25579","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d41895248c47e875"},{"id":"cw-d42ededc8c0dabd1","name":"Nehalem","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2008,"process":"45 nm","aliases":["Intel microarchitectures nehalem (client)"],"fields":[{"key":"Architecture name","value":"Nehalem","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August, 2008","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Penryn","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Westmere","unit":"","sourceId":"chipswiki-3898-r12328","location":"Intel/microarchitectures/nehalem (client) · revision 12328 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-d42ededc8c0dabd1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3898-r12328"],"url":"https://museum.vlsi.kr/objects/cw-d42ededc8c0dabd1"},{"id":"cw-d431d5db13bbcaf4","name":"Xeon Gold 6140M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6140m"],"fields":[{"key":"Model name","value":"Xeon Gold 6140M","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6140M","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405500","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AZ","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1504-r4956","location":"Intel/xeon gold/6140m · revision 4956 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d431d5db13bbcaf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1504-r4956"],"url":"https://museum.vlsi.kr/objects/cw-d431d5db13bbcaf4"},{"id":"cw-d43a8a65bbe3c9ee","name":"Core i7-2685QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2685qm"],"fields":[{"key":"Model name","value":"Core i7-2685QM","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2685QM","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701160200","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0GH","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7881-r25385","location":"Intel/core i7/i7-2685qm · revision 25385 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d43a8a65bbe3c9ee","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7881-r25385","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d43a8a65bbe3c9ee"},{"id":"cw-d446cd29b0ca8eb7","name":"Core i7-6567U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6567u"],"fields":[{"key":"Model name","value":"Core i7-6567U","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6567U","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202499000","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JH","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 550","unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7846-r25344","location":"Intel/core i7/i7-6567u · revision 25344 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d446cd29b0ca8eb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7846-r25344","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-d446cd29b0ca8eb7"},{"id":"cw-d45f5d55310eab0f","name":"AMD-K6-III/333AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-333afk"],"fields":[{"key":"Model name","value":"AMD-K6-III/333AFK","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/333AFK","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/333AFK","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8310-r26000","location":"Amd/k6-iii-p/amd-k6-iii-333afk · revision 26000 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d45f5d55310eab0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8310-r26000"],"url":"https://museum.vlsi.kr/objects/cw-d45f5d55310eab0f"},{"id":"cw-d47b663d3d07464d","name":"Am486DX-40","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dx-40"],"fields":[{"key":"Model name","value":"Am486DX-40","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX-40","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-40","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 1993","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":89,"unit":"mm²","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8573-r26771","location":"Amd/am486/am486dx-40 · revision 26771 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d47b663d3d07464d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8573-r26771"],"url":"https://museum.vlsi.kr/objects/cw-d47b663d3d07464d"},{"id":"cw-d4827dd599aba915","name":"Xeon E-2246G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2246g"],"fields":[{"key":"Model name","value":"Xeon E-2246G","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2246G","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404227903","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF7N","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149.6,"unit":"mm²","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2409-r8044","location":"Intel/xeon e/e-2246g · revision 8044 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d4827dd599aba915","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2409-r8044"],"url":"https://museum.vlsi.kr/objects/cw-d4827dd599aba915"},{"id":"cw-d48acd1f134fc1dd","name":"J8086","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 j8086"],"fields":[{"key":"Model name","value":"AMD J8086","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J8086","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J8086","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J8086","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8508-r26701","location":"Amd/am8086/j8086 · revision 26701 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d48acd1f134fc1dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8508-r26701"],"url":"https://museum.vlsi.kr/objects/cw-d48acd1f134fc1dd"},{"id":"cw-d491d6f3190284a0","name":"z10","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2008,"process":"65 nm","aliases":["Ibm microarchitectures z10"],"fields":[{"key":"Architecture name","value":"z10","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 2008","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z9","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z196","unit":"","sourceId":"chipswiki-9265-r28836","location":"Ibm/microarchitectures/z10 · revision 28836 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-06. Not an independent measurement.","entityId":"cw-d491d6f3190284a0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","sourceDate":"2017-11-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9265-r28836"],"url":"https://museum.vlsi.kr/objects/cw-d491d6f3190284a0"},{"id":"cw-d4f58d33d77f8f82","name":"Xeon Platinum 8175M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8175m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8175M","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8175M","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-189-r379","location":"Intel/xeon platinum/8175m · revision 379 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-22. Not an independent measurement.","entityId":"cw-d4f58d33d77f8f82","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","sourceDate":"2022-09-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-189-r379"],"url":"https://museum.vlsi.kr/objects/cw-d4f58d33d77f8f82"},{"id":"cw-d4ff806112d33df0","name":"Xeon Gold 6254","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6254"],"fields":[{"key":"Model name","value":"Xeon Gold 6254","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6254,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194501","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF92","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1476-r4924","location":"Intel/xeon gold/6254 · revision 4924 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-d4ff806112d33df0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1476-r4924"],"url":"https://museum.vlsi.kr/objects/cw-d4ff806112d33df0"},{"id":"cw-d50de917bf52596f","name":"Embedded G-Series T16R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2012,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t16r"],"fields":[{"key":"Model name","value":"Embedded G-Series T16R","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T16R","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET16RFWB12GVE","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 2012","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":615,"unit":"MHz","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1 × 512 KiB","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6250","unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":276,"unit":"MHz","sourceId":"chipswiki-426-r898","location":"Amd/embedded/t16r · revision 898 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","sourceDate":"2022-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-02. Not an independent measurement.","entityId":"cw-d50de917bf52596f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-426-r898","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-d50de917bf52596f"},{"id":"cw-d50f3052ede990b0","name":"K6-2/450AGX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-450agx"],"fields":[{"key":"Model name","value":"K6-2/450AGX","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/450AGX","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/450AGX","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 11, 1999","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.3,"unit":"V","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8344-r26039","location":"Amd/k6-2/k6-2-450agx · revision 26039 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d50f3052ede990b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8344-r26039"],"url":"https://museum.vlsi.kr/objects/cw-d50f3052ede990b0"},{"id":"cw-d57429c6dad8c2aa","name":"Cloud AI 100","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Qualcomm","year":2021,"process":"7 nm","aliases":["Qualcomm microarchitectures cloud ai 100"],"fields":[{"key":"Architecture name","value":"Cloud AI 100","unit":"","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"March, 2021","unit":"","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"VLIW","unit":"","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-605-r1411","location":"Qualcomm/microarchitectures/cloud ai 100 · revision 1411 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-09-15. Not an independent measurement.","entityId":"cw-d57429c6dad8c2aa","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","sourceDate":"2021-09-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-605-r1411"],"url":"https://museum.vlsi.kr/objects/cw-d57429c6dad8c2aa"},{"id":"cw-d596820c6eb81f9b","name":"Vector Engine Type 10CE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NEC","series":"Type 10E","year":2020,"architecture":"SX-Aurora","process":"16 nm","aliases":["Nec vector engine type 10ce"],"fields":[{"key":"Model name","value":"VE Type 10CE","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Type 10CE","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 2019","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2020","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vector Engine","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Type 10E","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SX-Aurora TSUBASA","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":493.68,"unit":"mm²","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-1300","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":48,"unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"998.4 GB/s","unit":"","sourceId":"chipswiki-1590-r5320","location":"Nec/vector engine/type 10ce · revision 5320 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d596820c6eb81f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1590-r5320"],"url":"https://museum.vlsi.kr/objects/cw-d596820c6eb81f9b"},{"id":"cw-d5c6076cf7817321","name":"Am486DX4-100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-100"],"fields":[{"key":"Model name","value":"Am486DX4-100","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-100","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-100","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 1994","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8559-r26755","location":"Amd/am486/am486dx4-100 · revision 26755 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d5c6076cf7817321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8559-r26755"],"url":"https://museum.vlsi.kr/objects/cw-d5c6076cf7817321"},{"id":"cw-d62759c1be47491c","name":"80286-8/BZC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am286 MIL","year":1987,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 80286-8-bzc"],"fields":[{"key":"Model name","value":"80286-8/BZC","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"80286-8/BZC","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80286-8/BZC","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1987,"unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1987","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am286 MIL","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8 MT/s","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8612-r26810","location":"Amd/am286/80286-8-bzc · revision 26810 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d62759c1be47491c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8612-r26810"],"url":"https://museum.vlsi.kr/objects/cw-d62759c1be47491c"},{"id":"cw-d62adc1e2fa8c547","name":"Xeon E-2286G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2286g"],"fields":[{"key":"Model name","value":"Xeon E-2286G","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2286G","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404173706","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF7C","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4900,"unit":"MHz","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149.6,"unit":"mm²","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":95,"unit":"W","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2405-r8036","location":"Intel/xeon e/e-2286g · revision 8036 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-d62adc1e2fa8c547","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2405-r8036"],"url":"https://museum.vlsi.kr/objects/cw-d62adc1e2fa8c547"},{"id":"cw-d63505c00ab55e8a","name":"Gen7","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2011,"process":"22 nm","aliases":["Intel microarchitectures gen7"],"fields":[{"key":"Architecture name","value":"Gen7","unit":"","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 4, 2011","unit":"","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen6","unit":"","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen7.5","unit":"","sourceId":"chipswiki-15964-r52699","location":"Intel/microarchitectures/gen7 · revision 52699 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d63505c00ab55e8a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15964-r52699"],"url":"https://museum.vlsi.kr/objects/cw-d63505c00ab55e8a"},{"id":"cw-d63a8b6cd417a20a","name":"Xeon Gold 6242R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6242r"],"fields":[{"key":"Model name","value":"Xeon Gold 6242R","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6242R","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1264-r4098","location":"Intel/xeon gold/6242r · revision 4098 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-d63a8b6cd417a20a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1264-r4098"],"url":"https://museum.vlsi.kr/objects/cw-d63a8b6cd417a20a"},{"id":"cw-d67924552f8df76d","name":"AMD-K6/300BDZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Mobile K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 300bdz"],"fields":[{"key":"Model name","value":"AMD-K6/300BDZ","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/300BDZ","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/300BDZ","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1012-r2863","location":"Amd/k6/amd-k6/300bdz · revision 2863 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":360,"unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.78,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-d67924552f8df76d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1012-r2863","chipswiki-31128-r91600"],"url":"https://museum.vlsi.kr/objects/cw-d67924552f8df76d"},{"id":"cw-d69200bd1a5dab71","name":"Snapdragon 845","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"800","year":2018,"architecture":"Cortex-A75","process":"10 nm","aliases":["Qualcomm snapdragon 800 845"],"fields":[{"key":"Model name","value":"Snapdragon 845","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM845","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SDM845","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 6, 2017","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2018","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 800","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2800,"unit":"MHz","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 385 Gold","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 385 Silver","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":5300000000,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":95,"unit":"mm²","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":10,"unit":"GiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","alternatives":[{"value":"8 GiB","sourceId":"chipswiki-331-r673","reason":"Qualcomm/snapdragon 800/845 · revision 673 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":1,"unit":"MiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x256 KiB","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"2-way set associative","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3833","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":29.87,"unit":"GiB/s","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 630 GPU","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":"2 (256x2 ALU)","unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":710,"unit":"MHz","sourceId":"chipswiki-331-r673","location":"Qualcomm/snapdragon 800/845 · revision 673 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-20. Not an independent measurement.","entityId":"cw-d69200bd1a5dab71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","sourceDate":"2022-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-331-r673"],"url":"https://museum.vlsi.kr/objects/cw-d69200bd1a5dab71"},{"id":"cw-d69d12513ca50009","name":"Xeon D-1632","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1632"],"fields":[{"key":"Model name","value":"Xeon D-1632","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1632","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":30,"unit":"W","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3687-r11016","location":"Intel/xeon d/d-1632 · revision 11016 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-d69d12513ca50009","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3687-r11016"],"url":"https://museum.vlsi.kr/objects/cw-d69d12513ca50009"},{"id":"cw-d6b3c9ac43dd4449","name":"Celeron B730","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"700","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b730"],"fields":[{"key":"Model name","value":"Celeron B730","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B730","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701084002","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701148002","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0QA","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2012","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2012","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":700,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-2218-r7506","location":"Intel/celeron/b730 · revision 7506 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","sourceDate":"2019-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-21. Not an independent measurement.","entityId":"cw-d6b3c9ac43dd4449","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2218-r7506","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d6b3c9ac43dd4449"},{"id":"cw-d6b88464d5ad1bc2","name":"K6-2/450AHX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-450ahx"],"fields":[{"key":"Model name","value":"K6-2/450AHX","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/450AHX","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/450AHX","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 11, 1999","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.4,"unit":"V","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8343-r26038","location":"Amd/k6-2/k6-2-450ahx · revision 26038 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d6b88464d5ad1bc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8343-r26038"],"url":"https://museum.vlsi.kr/objects/cw-d6b88464d5ad1bc2"},{"id":"cw-d6c5301c608b5d5d","name":"Core i5-9300H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-9300h"],"fields":[{"key":"Model name","value":"Core i5-9300H","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-9300H","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-9000","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake HR","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":42.6,"unit":"GiB/s","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-355-r749","location":"Intel/core i5/i5-9300h · revision 749 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-d6c5301c608b5d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-355-r749","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-d6c5301c608b5d5d"},{"id":"cw-d70d15b0d909568b","name":"Pentium J4205","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J Series","year":2016,"architecture":"Goldmont","process":"14 nm","aliases":["Intel pentium (2009) j4205"],"fields":[{"key":"Model name","value":"Pentium J4205","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J4205","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802986200","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J Series","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZA","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-7781-r25215","location":"Intel/pentium (2009)/j4205 · revision 25215 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d70d15b0d909568b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7781-r25215"],"url":"https://museum.vlsi.kr/objects/cw-d70d15b0d909568b"},{"id":"cw-d713c067ffcbdc4c","name":"Myriad 1 MA1100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","series":"1","year":2009,"architecture":"LEON3","process":"65 nm","aliases":["Movidius myriad ma1100"],"fields":[{"key":"Model name","value":"Myriad 1 MA1100","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MA1100","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2009,"unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2009,"unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Myriad","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":1,"unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"TSMC","unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-6971-r21758","location":"Movidius/myriad/ma1100 · revision 21758 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-d713c067ffcbdc4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6971-r21758"],"url":"https://museum.vlsi.kr/objects/cw-d713c067ffcbdc4c"},{"id":"cw-d714edb2f39bab27","name":"Core i5-2557M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2557m"],"fields":[{"key":"Model name","value":"Core i5-2557M","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2557M","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047204","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CS","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7947-r25495","location":"Intel/core i5/i5-2557m · revision 25495 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d714edb2f39bab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7947-r25495","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-d714edb2f39bab27"},{"id":"cw-d73f5ce877d6ff50","name":"Core i7-2860QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2860qm"],"fields":[{"key":"Model name","value":"Core i7-2860QM","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2860QM","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701065100","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701065200","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02X","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02Q","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-5186-r16929","location":"Intel/core i7/i7-2860qm · revision 16929 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","sourceDate":"2018-07-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2018-07-31. Not an independent measurement.","entityId":"cw-d73f5ce877d6ff50","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5186-r16929","chipswiki-31408-r92251","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d73f5ce877d6ff50"},{"id":"cw-d7455d471f067721","name":"Core i3-8130U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-8130u"],"fields":[{"key":"Model name","value":"Core i3-8130U","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8130U","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067703282227","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3W0","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 12, 2018","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 12, 2018","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6855-r21375","location":"Intel/core i3/i3-8130u · revision 21375 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-d7455d471f067721","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6855-r21375","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-d7455d471f067721"},{"id":"cw-d74a01ff89f922b3","name":"Am186ES–20VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–20vc\\w"],"fields":[{"key":"Model name","value":"Am186ES–20VC\\W","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–20VC\\W","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–20VC\\W","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14625-r44686","location":"Amd/am186ex/am186es–20vc\\w · revision 44686 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d74a01ff89f922b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14625-r44686"],"url":"https://museum.vlsi.kr/objects/cw-d74a01ff89f922b3"},{"id":"cw-d75dba14dda0bd52","name":"K6-2E+/450ACR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-450acr"],"fields":[{"key":"Model name","value":"K6-2E+/450ACR","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/450ACR","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/450ACR","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":450,"unit":"MHz","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17.5,"unit":"W","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1005-r2856","location":"Amd/k6-2+/k6-2e+-450acr · revision 2856 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-d75dba14dda0bd52","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1005-r2856","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-d75dba14dda0bd52"},{"id":"cw-d760fde0936452f5","name":"Core m7-6Y75","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"m-6Y","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core m m7-6y75"],"fields":[{"key":"Model name","value":"Core m7-6Y75","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"m7-6Y75","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8066201922875","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EH","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core m7","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"m-6Y","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake Y","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":5,"unit":"°C","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 515","unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-4983-r16105","location":"Intel/core m/m7-6y75 · revision 16105 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-d760fde0936452f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4983-r16105"],"url":"https://museum.vlsi.kr/objects/cw-d760fde0936452f5"},{"id":"cw-d7b1580f9c6dabb8","name":"EPYC 7601","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7601"],"fields":[{"key":"Model name","value":"EPYC 7601","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7601,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7601BDVIHAF","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x64 KiB","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3929-r12499","location":"Amd/epyc/7601 · revision 12499 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-d7b1580f9c6dabb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3929-r12499","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-d7b1580f9c6dabb8"},{"id":"cw-d7ddbdc31843c26c","name":"Ryzen 7 PRO 4750GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 pro 4750ge"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 4750GE","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4750GE","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000152","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000152MPK","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-703-r1704","location":"Amd/ryzen 7/pro 4750ge · revision 1704 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-d7ddbdc31843c26c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-703-r1704"],"url":"https://museum.vlsi.kr/objects/cw-d7ddbdc31843c26c"},{"id":"cw-d7e03dc2c908ab27","name":"Am2029","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 2","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2029"],"fields":[{"key":"Model name","value":"Am2029","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2029","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2029","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 15, 2007","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 15, 2007","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 2","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":216,"unit":"","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8665-r26864","location":"Ambric/am2000/am2029 · revision 26864 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d7e03dc2c908ab27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8665-r26864"],"url":"https://museum.vlsi.kr/objects/cw-d7e03dc2c908ab27"},{"id":"cw-d80adb7713fde6c2","name":"Ryzen 3 5400U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 3 5400u"],"fields":[{"key":"Model name","value":"Ryzen 3 5400U","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5400U","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000288","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-710-r1716","location":"Amd/ryzen 3/5400u · revision 1716 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-d80adb7713fde6c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-710-r1716"],"url":"https://museum.vlsi.kr/objects/cw-d80adb7713fde6c2"},{"id":"cw-d821ec9f8541b465","name":"Am186CH-50KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CH","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186ch-50kc\\w"],"fields":[{"key":"Model name","value":"Am186CH-50KC\\W","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CH-50KC\\W","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CH-50KC\\W","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CH","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14682-r44743","location":"Amd/am186cx/am186ch-50kc\\w · revision 44743 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-d821ec9f8541b465","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14682-r44743"],"url":"https://museum.vlsi.kr/objects/cw-d821ec9f8541b465"},{"id":"cw-d83b54c459b2c836","name":"EPYC 72F3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 72f3"],"fields":[{"key":"Model name","value":"EPYC 72F3","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"72F3","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000327","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000327WOF","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8 × 512 KiB","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-746-r1787","location":"Amd/epyc/72f3 · revision 1787 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-d83b54c459b2c836","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-746-r1787"],"url":"https://museum.vlsi.kr/objects/cw-d83b54c459b2c836"},{"id":"cw-d83d2836d171726d","name":"Core i3-8320T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8320t"],"fields":[{"key":"Model name","value":"Core i3-8320T","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8320T","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6424-r20049","location":"Intel/core i3/i3-8320t · revision 20049 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-d83d2836d171726d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6424-r20049"],"url":"https://museum.vlsi.kr/objects/cw-d83d2836d171726d"},{"id":"cw-d888d849e26d0835","name":"EPYC 7443","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7443"],"fields":[{"key":"Model name","value":"EPYC 7443","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7443,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000340","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000340WOF","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2850,"unit":"MHz","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24 × 512 KiB","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-732-r1753","location":"Amd/epyc/7443 · revision 1753 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-d888d849e26d0835","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-732-r1753"],"url":"https://museum.vlsi.kr/objects/cw-d888d849e26d0835"},{"id":"cw-d88fda4a88fc1610","name":"Hanguang 800","kind":"sku","entityType":"product-model","subtype":"sku","company":"T-Head","year":2019,"process":"12 nm","aliases":["T-head hanguang 800"],"fields":[{"key":"Model name","value":"Hanguang 800","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"T-Head","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2019","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2019","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Hanguang","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":17000000000,"unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1695-r5907","location":"T-head/hanguang 800 · revision 5907 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-12. Not an independent measurement.","entityId":"cw-d88fda4a88fc1610","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","sourceDate":"2019-10-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1695-r5907"],"url":"https://museum.vlsi.kr/objects/cw-d88fda4a88fc1610"},{"id":"cw-d892bfe818f991da","name":"EPYC 7261","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7261"],"fields":[{"key":"Model name","value":"EPYC 7261","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7261,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7261BEV8RAF","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 2018","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 2018","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-4493-r14595","location":"Amd/epyc/7261 · revision 14595 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","sourceDate":"2018-11-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-01. Not an independent measurement.","entityId":"cw-d892bfe818f991da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4493-r14595","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-d892bfe818f991da"},{"id":"cw-d8b318435a52851b","name":"Core i3-2394M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2394m"],"fields":[{"key":"Model name","value":"Core i3-2394M","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2394M","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701084501","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR09R","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7997-r25578","location":"Intel/core i3/i3-2394m · revision 25578 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b318435a52851b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7997-r25578","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d8b318435a52851b"},{"id":"cw-d8b7d8eea885997e","name":"CN5840-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5840-600 EXP","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-600 EXP","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-600BG1521-EXP","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8146-r25805","location":"Cavium/octeon plus/cn5840-600bg1521-exp · revision 25805 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8b7d8eea885997e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8146-r25805","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-d8b7d8eea885997e"},{"id":"cw-d8c5926fc5245944","name":"Core i7-3970X Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-3900","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7ee i7-3970x"],"fields":[{"key":"Model name","value":"Core i7-3970X Extreme Edition","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-3970X","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8061901281201","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80619I73970X","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2012","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 12, 2012","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-3900","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0WR","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"6 Series Chipset","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge E","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA2011","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":15,"unit":"MiB","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7825-r25284","location":"Intel/core i7ee/i7-3970x · revision 25284 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8c5926fc5245944","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7825-r25284"],"url":"https://museum.vlsi.kr/objects/cw-d8c5926fc5245944"},{"id":"cw-d8eaaf526ae26960","name":"Pentium P6000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P6000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel pentium (2009) p6000"],"fields":[{"key":"Model name","value":"Intel Pentium P6000","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P6000","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004170AF","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2010","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2010","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P6000","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBWB","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":667,"unit":"MHz","sourceId":"chipswiki-7779-r25211","location":"Intel/pentium (2009)/p6000 · revision 25211 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d8eaaf526ae26960","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7779-r25211","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-d8eaaf526ae26960"},{"id":"cw-d91083b178c58bef","name":"Gen6","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2010,"process":"32 nm","aliases":["Intel microarchitectures gen6"],"fields":[{"key":"Architecture name","value":"Gen6","unit":"","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 13, 2010","unit":"","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen5.75","unit":"","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen7","unit":"","sourceId":"chipswiki-15963-r52697","location":"Intel/microarchitectures/gen6 · revision 52697 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-d91083b178c58bef","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15963-r52697"],"url":"https://museum.vlsi.kr/objects/cw-d91083b178c58bef"},{"id":"cw-d91d6c7912b54074","name":"R-Car M3 (SiP)","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"3rd Gen","year":2016,"architecture":"Cortex-A53","process":"16 nm","aliases":["Renesas r-car m3 (sip)"],"fields":[{"key":"Model name","value":"R-Car M3 (SiP)","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M3 (SiP)","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8J77960","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2016","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2016","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"3rd Gen","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-R7","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":7,"unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":7,"unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x48+5x32 KiB","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":224,"unit":"KiB","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"7x32 KiB","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-3200","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GX6250","unit":"","sourceId":"chipswiki-7643-r24903","location":"Renesas/r-car/m3 (sip) · revision 24903 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1255","unit":"","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1255,"unit":"","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42.5,"unit":"mm","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":42.5,"unit":"mm","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91d6c7912b54074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7643-r24903","chipswiki-31420-r92284"],"url":"https://museum.vlsi.kr/objects/cw-d91d6c7912b54074"},{"id":"cw-d91dcd167bb88f99","name":"Atom 230","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"200","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom 230"],"fields":[{"key":"Model name","value":"Atom 230","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":230,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AU80586RE025D","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB6Z","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2008","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":200,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1599.99,"unit":"MHz","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Nettop 2008","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Calistoga","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Diamondville","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":112,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":25.9638,"unit":"mm²","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4,"unit":"W","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8075-r25726","location":"Intel/atom/230 · revision 25726 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d91dcd167bb88f99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8075-r25726","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-d91dcd167bb88f99"},{"id":"cw-d9363c2c63cb5e31","name":"Xeon Bronze 3204","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon bronze 3204"],"fields":[{"key":"Model name","value":"Xeon Bronze 3204","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3204,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069503956700","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBP","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Bronze","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3200,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R1","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x1 MiB","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-2565-r8962","location":"Intel/xeon bronze/3204 · revision 8962 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-d9363c2c63cb5e31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2565-r8962"],"url":"https://museum.vlsi.kr/objects/cw-d9363c2c63cb5e31"},{"id":"cw-d944da78ea9aa022","name":"K6-2E/333AFR-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-333afr-66"],"fields":[{"key":"Model name","value":"K6-2E/333AFR-66","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/333AFR-66","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/333AFR-66","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 1999","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 1999","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.33,"unit":"MHz","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8322-r26017","location":"Amd/k6-2/k6-2e-333afr-66 · revision 26017 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d944da78ea9aa022","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8322-r26017"],"url":"https://museum.vlsi.kr/objects/cw-d944da78ea9aa022"},{"id":"cw-d98020c0dc124725","name":"Core i7-2689M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2689m"],"fields":[{"key":"Model name","value":"Core i7-2689M","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2689M","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700850807","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04C","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7880-r25384","location":"Intel/core i7/i7-2689m · revision 25384 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d98020c0dc124725","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7880-r25384","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-d98020c0dc124725"},{"id":"cw-d9957bc3ae578461","name":"QorIQ P2010","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P2","year":2009,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p2010"],"fields":[{"key":"Model name","value":"P2010","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P2010","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 16, 2008","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2009,"unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P2","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":800,"unit":"MHz","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1000,"unit":"MHz","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1200,"unit":"MHz","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":1333,"unit":"MHz","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-1215-r3802","location":"Freescale/qoriq/p2010 · revision 3802 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA-II","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-d9957bc3ae578461","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1215-r3802","chipswiki-31374-r92168"],"url":"https://museum.vlsi.kr/objects/cw-d9957bc3ae578461"},{"id":"cw-d9ae8bd0daa9597a","name":"Xeon Platinum 8280M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8280m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8280M","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8280M","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504228101","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9Q","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1248-r4019","location":"Intel/xeon platinum/8280m · revision 4019 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-02. Not an independent measurement.","entityId":"cw-d9ae8bd0daa9597a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","sourceDate":"2020-03-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1248-r4019"],"url":"https://museum.vlsi.kr/objects/cw-d9ae8bd0daa9597a"},{"id":"cw-d9bf9e7196968142","name":"K6-2E/266AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-266amz"],"fields":[{"key":"Model name","value":"K6-2E/266AMZ","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/266AMZ","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/266AMZ","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8328-r26023","location":"Amd/k6-2/k6-2e-266amz · revision 26023 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-d9bf9e7196968142","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8328-r26023"],"url":"https://museum.vlsi.kr/objects/cw-d9bf9e7196968142"},{"id":"cw-d9e5fb98e5edf2cf","name":"Cortex-A75","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2017,"process":"16 nm","aliases":["Arm holdings microarchitectures cortex-a75"],"fields":[{"key":"Architecture name","value":"Cortex-A75","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 29, 2017","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / process 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 4","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"process 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"3-way","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"64-256-512 KiB","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"0-4 MiB","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A73","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A76","unit":"","sourceId":"chipswiki-1235-r3896","location":"Arm holdings/microarchitectures/cortex-a75 · revision 3896 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-d9e5fb98e5edf2cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1235-r3896"],"url":"https://museum.vlsi.kr/objects/cw-d9e5fb98e5edf2cf"},{"id":"cw-d9f061e501c3e3dd","name":"EPYC 7542","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7542"],"fields":[{"key":"Model name","value":"EPYC 7542","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7542,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000075","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000075WOF","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-864-r2248","location":"Amd/epyc/7542 · revision 2248 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-d9f061e501c3e3dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-864-r2248"],"url":"https://museum.vlsi.kr/objects/cw-d9f061e501c3e3dd"},{"id":"cw-d9f84899b251b38e","name":"Vector Engine Type 10A","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NEC","series":"Type 10","year":2018,"architecture":"SX-Aurora","process":"16 nm","aliases":["Nec vector engine type 10a"],"fields":[{"key":"Model name","value":"VE Type 10A","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Type 10A","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Oct 26, 2017","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2018,"unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vector Engine","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Type 10","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SX-Aurora TSUBASA","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":493.68,"unit":"mm²","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":48,"unit":"GiB","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-1600","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":48,"unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,229 GB/s","unit":"","sourceId":"chipswiki-1595-r5336","location":"Nec/vector engine/type 10a · revision 5336 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-d9f84899b251b38e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1595-r5336"],"url":"https://museum.vlsi.kr/objects/cw-d9f84899b251b38e"},{"id":"cw-da10d7a63ea2f177","name":"CN3110-300 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-300bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3110-300 EXP","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-300 EXP","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-300BG868-EXP","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8268-r25928","location":"Cavium/octeon/cn3110-300bg868-exp · revision 25928 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da10d7a63ea2f177","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8268-r25928","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-da10d7a63ea2f177"},{"id":"cw-da368f06eac91923","name":"Xeon Silver 4214Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4214y"],"fields":[{"key":"Model name","value":"Xeon Silver 4214Y","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4214Y","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504294401","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFDG","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1446-r4886","location":"Intel/xeon silver/4214y · revision 4886 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da368f06eac91923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1446-r4886"],"url":"https://museum.vlsi.kr/objects/cw-da368f06eac91923"},{"id":"cw-da503986ed241702","name":"Xeon E3-1240L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1240l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1240L v5","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1240L v5","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201935808","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2CW","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LN","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v5","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7768-r25161","location":"Intel/xeon e3/e3-1240l v5 · revision 25161 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da503986ed241702","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7768-r25161"],"url":"https://museum.vlsi.kr/objects/cw-da503986ed241702"},{"id":"cw-da556270d9599bcb","name":"Xeon Gold 6226","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6226"],"fields":[{"key":"Model name","value":"Xeon Gold 6226","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6226,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1491-r4943","location":"Intel/xeon gold/6226 · revision 4943 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-da556270d9599bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1491-r4943"],"url":"https://museum.vlsi.kr/objects/cw-da556270d9599bcb"},{"id":"cw-da62741c54da5da6","name":"CN5830-1000 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-1000bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5830-1000 NSP","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-1000 NSP","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-1000BG1521-NSP","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8160-r25819","location":"Cavium/octeon plus/cn5830-1000bg1521-nsp · revision 25819 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-da62741c54da5da6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8160-r25819","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-da62741c54da5da6"},{"id":"cw-da7b5468a3a08058","name":"Ryzen 3 4300GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 4300ge"],"fields":[{"key":"Model name","value":"Ryzen 3 4300GE","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4300GE","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000151","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-634-r1530","location":"Amd/ryzen 3/4300ge · revision 1530 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-da7b5468a3a08058","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-634-r1530"],"url":"https://museum.vlsi.kr/objects/cw-da7b5468a3a08058"},{"id":"cw-da8f153d13aba4a5","name":"Core i7-1068G7","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":null,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i7 i7-1068g7"],"fields":[{"key":"Model name","value":"Core i7-1068G7","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-1068G7","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":64,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-836-r2183","location":"Intel/core i7/i7-1068g7 · revision 2183 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-da8f153d13aba4a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-836-r2183"],"url":"https://museum.vlsi.kr/objects/cw-da8f153d13aba4a5"},{"id":"cw-dad1a7334bb8a697","name":"Atom C3708","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3708"],"fields":[{"key":"Model name","value":"Atom C3708","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3708","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502640002","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38F","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":448,"unit":"KiB","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x24 KiB","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-1866-r6402","location":"Intel/atom/c3708 · revision 6402 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-dad1a7334bb8a697","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1866-r6402","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-dad1a7334bb8a697"},{"id":"cw-dad5c9af5193c75f","name":"CN3830-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-500bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3830-500 NSP","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-500 NSP","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-500BG1521-NSP","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8225-r25884","location":"Cavium/octeon/cn3830-500bg1521-nsp · revision 25884 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dad5c9af5193c75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8225-r25884","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-dad5c9af5193c75f"},{"id":"cw-dadcdc30300ec105","name":"Exynos M3","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Samsung","year":2018,"process":"10 nm","aliases":["Samsung microarchitectures m3"],"fields":[{"key":"Architecture name","value":"Meerkat","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":16,"unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"6-way","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"M2","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"M4","unit":"","sourceId":"chipswiki-1290-r4302","location":"Samsung/microarchitectures/m3 · revision 4302 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-dadcdc30300ec105","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1290-r4302"],"url":"https://museum.vlsi.kr/objects/cw-dadcdc30300ec105"},{"id":"cw-db13f2ec2861169b","name":"KaiXian KX-U5580","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KX-5000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaixian kx-u5580"],"fields":[{"key":"Model name","value":"KaiXian KX-U5580","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KX-U5580","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KX-U5580","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaiXian","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KX-5000","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5650-r18548","location":"Zhaoxin/kaixian/kx-u5580 · revision 18548 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-db13f2ec2861169b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5650-r18548"],"url":"https://museum.vlsi.kr/objects/cw-db13f2ec2861169b"},{"id":"cw-db28fbea2d89e3ef","name":"Am186ED–20KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–20ki\\w"],"fields":[{"key":"Model name","value":"Am186ED–20KI\\W","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–20KI\\W","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–20KI\\W","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14671-r44732","location":"Amd/am186ex/am186ed–20ki\\w · revision 44732 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-db28fbea2d89e3ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14671-r44732"],"url":"https://museum.vlsi.kr/objects/cw-db28fbea2d89e3ef"},{"id":"cw-db8187b44241b51b","name":"P8086-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 p8086-1"],"fields":[{"key":"Model name","value":"AMD P8086-1","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P8086-1","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P8086-1","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P8086","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PDIP-40","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PDIP","unit":"","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8495-r26688","location":"Amd/am8086/p8086-1 · revision 26688 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db8187b44241b51b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8495-r26688"],"url":"https://museum.vlsi.kr/objects/cw-db8187b44241b51b"},{"id":"cw-db87ae47a8e2564f","name":"POWER9 02CY230","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy230"],"fields":[{"key":"Model name","value":"02CY230","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY230","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY230","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.9,"unit":"GHz","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":80,"unit":"MiB","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x10 MiB","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3946-r12589","location":"Ibm/power/02cy230 · revision 12589 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-db87ae47a8e2564f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3946-r12589"],"url":"https://museum.vlsi.kr/objects/cw-db87ae47a8e2564f"},{"id":"cw-db9f8007f73deab7","name":"Xeon E5-2689 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2689 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2689 v4","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2689 v4","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002648200","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2T7","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":25,"unit":"MiB","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7724-r25099","location":"Intel/xeon e5/e5-2689 v4 · revision 25099 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-db9f8007f73deab7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7724-r25099"],"url":"https://museum.vlsi.kr/objects/cw-db9f8007f73deab7"},{"id":"cw-dbb461ac0f407825","name":"Atom x5-Z8350","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z8000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x5 x5-z8350"],"fields":[{"key":"Model name","value":"Intel Atom x5-Z8350","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-Z8350","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401836620","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KT","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z8000","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1440,"unit":"MHz","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1920,"unit":"MHz","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Cherry Trail","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA592","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-587-r1358","location":"Intel/atom x5/x5-z8350 · revision 1358 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-13. Not an independent measurement.","entityId":"cw-dbb461ac0f407825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","sourceDate":"2021-10-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-587-r1358"],"url":"https://museum.vlsi.kr/objects/cw-dbb461ac0f407825"},{"id":"cw-dbd0bd6f4c914881","name":"Mobile Pentium II 266PE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1999,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 266pe"],"fields":[{"key":"Model name","value":"Mobile Pentium II 266PE","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"266PE","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMG26602002AA","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KP80524KX266256","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KC80524KX266256","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1998,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 25, 1999","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266,"unit":"MHz","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3HH","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL32Q","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3DR","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL32M","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dixon","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdpA0","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdbA0","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdbA0","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdxA0","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27400000,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":180,"unit":"mm²","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10.3,"unit":"W","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7806-r25245","location":"Intel/mobile pentium ii/266pe · revision 25245 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd0bd6f4c914881","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7806-r25245"],"url":"https://museum.vlsi.kr/objects/cw-dbd0bd6f4c914881"},{"id":"cw-dbd51a38b4761aaf","name":"Am486DX4-75SV8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4S","year":1996,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-75sv8b"],"fields":[{"key":"Model name","value":"Am486DX4-75SV8B","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-75SV8B","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-75SV8B","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"S80486DX4-75SV8B","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1995,"unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1996","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":75,"unit":"MHz","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8548-r26744","location":"Amd/am486/am486dx4-75sv8b · revision 26744 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd51a38b4761aaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8548-r26744"],"url":"https://museum.vlsi.kr/objects/cw-dbd51a38b4761aaf"},{"id":"cw-dbd7b3862dc87b6d","name":"Core i7-2677M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2677m"],"fields":[{"key":"Model name","value":"Core i7-2677M","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2677M","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701041005","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0D2","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7882-r25386","location":"Intel/core i7/i7-2677m · revision 25386 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dbd7b3862dc87b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7882-r25386","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-dbd7b3862dc87b6d"},{"id":"cw-dbef507626f5f913","name":"Exynos M1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Samsung","year":2015,"process":"14 nm","aliases":["Samsung microarchitectures m1"],"fields":[{"key":"Architecture name","value":"Mongoose 1","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 12, 2015","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":14,"unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"M2","unit":"","sourceId":"chipswiki-3826-r12084","location":"Samsung/microarchitectures/m1 · revision 12084 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-dbef507626f5f913","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3826-r12084"],"url":"https://museum.vlsi.kr/objects/cw-dbef507626f5f913"},{"id":"cw-dc026d0028a77574","name":"Am186EM–40KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–40kc\\w"],"fields":[{"key":"Model name","value":"Am186EM–40KC\\W","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–40KC\\W","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–40KC\\W","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14650-r44711","location":"Amd/am186ex/am186em–40kc\\w · revision 44711 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-dc026d0028a77574","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14650-r44711"],"url":"https://museum.vlsi.kr/objects/cw-dc026d0028a77574"},{"id":"cw-dc06adbd51fef2ca","name":"Amber Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2018,"process":"14 nm","aliases":["Intel microarchitectures amber lake"],"fields":[{"key":"Architecture name","value":"Amber Lake","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"Q4, 2018","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Kaby Lake","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Ice Lake","unit":"","sourceId":"chipswiki-2471-r8392","location":"Intel/microarchitectures/amber lake · revision 8392 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-dc06adbd51fef2ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2471-r8392"],"url":"https://museum.vlsi.kr/objects/cw-dc06adbd51fef2ca"},{"id":"cw-dc13336d65b5bb37","name":"Goldmont","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2016,"process":"14 nm","aliases":["Intel microarchitectures goldmont"],"fields":[{"key":"Architecture name","value":"Goldmont","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 30, 2016","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"1-2 MiB","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"2 Cores","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"2 Cores","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Airmont","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-1234-r3880","location":"Intel/microarchitectures/goldmont · revision 3880 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-24. Not an independent measurement.","entityId":"cw-dc13336d65b5bb37","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","sourceDate":"2020-03-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1234-r3880"],"url":"https://museum.vlsi.kr/objects/cw-dc13336d65b5bb37"},{"id":"cw-dc155baf192a1ff6","name":"Godson-2B1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2004,"architecture":"GS464","process":"180 nm","aliases":["Loongson godson 2 2b1"],"fields":[{"key":"Model name","value":"Godson-2B1","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMICS","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2B1","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2004,"unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2004","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7684-r24979","location":"Loongson/godson 2/2b1 · revision 24979 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc155baf192a1ff6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7684-r24979"],"url":"https://museum.vlsi.kr/objects/cw-dc155baf192a1ff6"},{"id":"cw-dc15de4fde7f1f6a","name":"Core i5-8500B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8500b"],"fields":[{"key":"Model name","value":"Core i5-8500B","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8500B","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-976-r2766","location":"Intel/core i5/i5-8500b · revision 2766 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-22. Not an independent measurement.","entityId":"cw-dc15de4fde7f1f6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","sourceDate":"2020-08-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-976-r2766"],"url":"https://museum.vlsi.kr/objects/cw-dc15de4fde7f1f6a"},{"id":"cw-dc29d9ad7f8e4477","name":"AMD-K6-III/350AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-350afk"],"fields":[{"key":"Model name","value":"AMD-K6-III/350AFK","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/350AFK","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/350AFK","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":349.99,"unit":"MHz","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8309-r25999","location":"Amd/k6-iii-p/amd-k6-iii-350afk · revision 25999 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc29d9ad7f8e4477","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8309-r25999"],"url":"https://museum.vlsi.kr/objects/cw-dc29d9ad7f8e4477"},{"id":"cw-dc3cd0d42379ef40","name":"Core i5-2467M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2467m"],"fields":[{"key":"Model name","value":"Core i5-2467M","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2467M","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047504","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047504","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0D4","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0D6","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7959-r25508","location":"Intel/core i5/i5-2467m · revision 25508 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc3cd0d42379ef40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7959-r25508","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-dc3cd0d42379ef40"},{"id":"cw-dc57dae19ef47c6b","name":"Core i7-660UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-660um"],"fields":[{"key":"Model name","value":"Intel Core i7-660UM","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-660UM","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005187AB","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSS","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7843-r25340","location":"Intel/core i7/i7-660um · revision 25340 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc57dae19ef47c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7843-r25340","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-dc57dae19ef47c6b"},{"id":"cw-dc77a25066812129","name":"Celeron G3902E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron g3902e"],"fields":[{"key":"Model name","value":"Celeron G3902E","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3902E","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202400204","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2GJ","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8029-r25633","location":"Intel/celeron/g3902e · revision 25633 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dc77a25066812129","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8029-r25633","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-dc77a25066812129"},{"id":"cw-dcaae80ef2eaf5c2","name":"Ryzen 3 PRO 3200G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 3 pro 3200g"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 3200G","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3200G","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD320BC5M4MFH","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1250,"unit":"MHz","sourceId":"chipswiki-1554-r5095","location":"Amd/ryzen 3/pro 3200g · revision 5095 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-dcaae80ef2eaf5c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1554-r5095"],"url":"https://museum.vlsi.kr/objects/cw-dcaae80ef2eaf5c2"},{"id":"cw-dcc5650be55962c3","name":"Xeon Gold 6230R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6230r"],"fields":[{"key":"Model name","value":"Xeon Gold 6230R","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6230R","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":26,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":52,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.625,"unit":"MiB","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":832,"unit":"KiB","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":832,"unit":"KiB","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":26,"unit":"MiB","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"26x1 MiB","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1266-r4101","location":"Intel/xeon gold/6230r · revision 4101 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-dcc5650be55962c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1266-r4101"],"url":"https://museum.vlsi.kr/objects/cw-dcc5650be55962c3"},{"id":"cw-dd3879437f59bc98","name":"CN3120-300 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-300bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3120-300 NSP","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-300 NSP","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-300BG868-NSP","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8251-r25911","location":"Cavium/octeon/cn3120-300bg868-nsp · revision 25911 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd3879437f59bc98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8251-r25911","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-dd3879437f59bc98"},{"id":"cw-dd5643a1807498eb","name":"ThunderX CN8890","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","year":2016,"architecture":"ThunderX1","process":"28 nm","aliases":["Cavium thunderx cn8890"],"fields":[{"key":"Model name","value":"ThunderX CN8890","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN8890","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN8890-1900BG2601-AAP-Y-G","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2014","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 31, 2016","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"CCPI","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ThunderX1","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","alternatives":[{"value":"0.5 TiB","sourceId":"chipswiki-4330-r13921","reason":"Cavium/thunderx/cn8890 · revision 13921 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"L1 cache","value":5280,"unit":"KiB","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":3744,"unit":"KiB","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48x78KiB","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"39-way set associative","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1536,"unit":"KiB","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48x32KiB","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-2133","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4330-r13921","location":"Cavium/thunderx/cn8890 · revision 13921 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-dd5643a1807498eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4330-r13921"],"url":"https://museum.vlsi.kr/objects/cw-dd5643a1807498eb"},{"id":"cw-dd61744d86dad369","name":"Embedded G-Series T48N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t48n"],"fields":[{"key":"Model name","value":"Embedded G-Series T48N","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T48N","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET48NGBB22GVE","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2011","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6310","unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":520,"unit":"MHz","sourceId":"chipswiki-417-r889","location":"Amd/embedded/t48n · revision 889 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-dd61744d86dad369","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-417-r889","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-dd61744d86dad369"},{"id":"cw-dd6995fbb71cf93e","name":"N80L286-16","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80L286","year":1989,"architecture":"80286","aliases":["Amd am286 n80l286-16"],"fields":[{"key":"Model name","value":"N80L286-16","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80L286-16","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N80L286-16","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80L286","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":16,"unit":"MHz","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"16 MT/s","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8588-r26786","location":"Amd/am286/n80l286-16 · revision 26786 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dd6995fbb71cf93e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8588-r26786"],"url":"https://museum.vlsi.kr/objects/cw-dd6995fbb71cf93e"},{"id":"cw-dd70834428162091","name":"z15","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2019,"process":"14 nm","aliases":["Ibm microarchitectures z15"],"fields":[{"key":"Architecture name","value":"z15","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 12, 2019","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":9,"unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":17,"unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"6-way","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"chip","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"chip","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z14","unit":"","sourceId":"chipswiki-1168-r3641","location":"Ibm/microarchitectures/z15 · revision 3641 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-07. Not an independent measurement.","entityId":"cw-dd70834428162091","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","sourceDate":"2020-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1168-r3641"],"url":"https://museum.vlsi.kr/objects/cw-dd70834428162091"},{"id":"cw-ddb07a79ebb60fe2","name":"Duron 600 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d600ast1b"],"fields":[{"key":"Model name","value":"Duron 600","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 600","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D600AST1B","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":22.7,"unit":"W","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8442-r26150","location":"Amd/duron/d600ast1b · revision 26150 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ddb07a79ebb60fe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8442-r26150"],"url":"https://museum.vlsi.kr/objects/cw-ddb07a79ebb60fe2"},{"id":"cw-ddb8fc697b4de9cf","name":"Carmel","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"NVIDIA","year":2018,"process":"12 nm","aliases":["Nvidia microarchitectures carmel"],"fields":[{"key":"Architecture name","value":"Carmel","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Nvidia","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January 7, 2018","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":8,"unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"complex","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"complex","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Denver 2","unit":"","sourceId":"chipswiki-2930-r9794","location":"Nvidia/microarchitectures/carmel · revision 9794 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-30. Not an independent measurement.","entityId":"cw-ddb8fc697b4de9cf","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","sourceDate":"2019-04-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2930-r9794"],"url":"https://museum.vlsi.kr/objects/cw-ddb8fc697b4de9cf"},{"id":"cw-ddef1633f4f5c39c","name":"AMD-X5-150ADZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-150adz"],"fields":[{"key":"Model name","value":"AMD-X5-150ADZ","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-150ADZ","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-150ADZ","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":150,"unit":"MHz","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-801-r2027","location":"Amd/am5x86/amd-x5-150adz · revision 2027 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-16. Not an independent measurement.","entityId":"cw-ddef1633f4f5c39c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","sourceDate":"2021-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-801-r2027"],"url":"https://museum.vlsi.kr/objects/cw-ddef1633f4f5c39c"},{"id":"cw-ddf2fdf2fa59cfe6","name":"Whiskey Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2018,"process":"14 nm++","aliases":["Intel microarchitectures whiskey lake"],"fields":[{"key":"Architecture name","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"Q4, 2018","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"14 nm++","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Kaby Lake","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Comet Lake","unit":"","sourceId":"chipswiki-1393-r4690","location":"Intel/microarchitectures/whiskey lake · revision 4690 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-09. Not an independent measurement.","entityId":"cw-ddf2fdf2fa59cfe6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","sourceDate":"2020-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1393-r4690"],"url":"https://museum.vlsi.kr/objects/cw-ddf2fdf2fa59cfe6"},{"id":"cw-ddf66963fb3c7e26","name":"Xeon Phi 7295","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"x205","year":2017,"architecture":"Knights Mill","process":"14 nm","aliases":["Intel xeon phi 7295"],"fields":[{"key":"Model name","value":"Xeon Phi 7295","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7295,"unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HJ8068303823700","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3VD","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 18, 2017","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 18, 2017","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Phi","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"x205","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Knights Mill","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A0","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":72,"unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":288,"unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":384,"unit":"GiB","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":320,"unit":"W","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4.5,"unit":"MiB","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2.25,"unit":"MiB","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"72x32 KiB","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2.25,"unit":"MiB","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"72x32 KiB","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":36,"unit":"MiB","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"36x1 MiB","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-2548-r8774","location":"Intel/xeon phi/7295 · revision 8774 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-ddf66963fb3c7e26","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2548-r8774"],"url":"https://museum.vlsi.kr/objects/cw-ddf66963fb3c7e26"},{"id":"cw-de10be51c6eaae7f","name":"Am486DX2-66V8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-66v8b"],"fields":[{"key":"Model name","value":"Am486DX2-66V8B","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-66V8B","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-66V8B","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-946-r2646","location":"Amd/am486/am486dx2-66v8b · revision 2646 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-28. Not an independent measurement.","entityId":"cw-de10be51c6eaae7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","sourceDate":"2020-09-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-946-r2646"],"url":"https://museum.vlsi.kr/objects/cw-de10be51c6eaae7f"},{"id":"cw-de3415594157868d","name":"Xeon Silver 4108","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon silver 4108"],"fields":[{"key":"Model name","value":"Xeon Silver 4108","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4108,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806734108","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303561500","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GJ","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1453-r4897","location":"Intel/xeon silver/4108 · revision 4897 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-de3415594157868d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1453-r4897"],"url":"https://museum.vlsi.kr/objects/cw-de3415594157868d"},{"id":"cw-de378e0357ce141b","name":"Godson-2G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2010,"architecture":"GS464","process":"65 nm","aliases":["Loongson godson 2 2g"],"fields":[{"key":"Model name","value":"Godson-2G","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2G","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2009","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2010","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"HyperTransport 1.0","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":100000000,"unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":53.54,"unit":"mm²","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-741","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-741","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7678-r24973","location":"Loongson/godson 2/2g · revision 24973 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de378e0357ce141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7678-r24973"],"url":"https://museum.vlsi.kr/objects/cw-de378e0357ce141b"},{"id":"cw-de4b6679b71b7c73","name":"CN3630-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-400bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3630-400 SCP","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-400 SCP","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-400BG1521-SCP","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8236-r25895","location":"Cavium/octeon/cn3630-400bg1521-scp · revision 25895 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de4b6679b71b7c73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8236-r25895","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-de4b6679b71b7c73"},{"id":"cw-de58b3594b45f5a9","name":"Duron 1100 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2002,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm1100ahq1b"],"fields":[{"key":"Model name","value":"Duron 1100","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1100","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM1100AHQ1B","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2002","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 30, 2002","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.55,"unit":"V","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8410-r26118","location":"Amd/duron/dhm1100ahq1b · revision 26118 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de58b3594b45f5a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8410-r26118"],"url":"https://museum.vlsi.kr/objects/cw-de58b3594b45f5a9"},{"id":"cw-de5a64a91fa4f747","name":"EPYC 73F3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 73f3"],"fields":[{"key":"Model name","value":"EPYC 73F3","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"73F3","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000321","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000321WOF","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-747-r1788","location":"Amd/epyc/73f3 · revision 1788 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-de5a64a91fa4f747","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-747-r1788"],"url":"https://museum.vlsi.kr/objects/cw-de5a64a91fa4f747"},{"id":"cw-de5ae012b94e5f2b","name":"Pentium Gold G5420T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel pentium gold g5420t"],"fields":[{"key":"Model name","value":"Pentium Gold G5420T","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G5420T","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403360213","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3XC","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2850-r9563","location":"Intel/pentium gold/g5420t · revision 9563 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-de5ae012b94e5f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2850-r9563"],"url":"https://museum.vlsi.kr/objects/cw-de5ae012b94e5f2b"},{"id":"cw-de659f428da6bffc","name":"Am186ED–40VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–40vc\\w"],"fields":[{"key":"Model name","value":"Am186ED–40VC\\W","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–40VC\\W","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–40VC\\W","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14663-r44724","location":"Amd/am186ex/am186ed–40vc\\w · revision 44724 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-de659f428da6bffc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14663-r44724"],"url":"https://museum.vlsi.kr/objects/cw-de659f428da6bffc"},{"id":"cw-de6b897db5034289","name":"Spring Crest","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Nervana","year":2019,"process":"16 nm","aliases":["Nervana microarchitectures spring crest"],"fields":[{"key":"Architecture name","value":"Spring Crest","unit":"","sourceId":"chipswiki-1181-r3688","location":"Nervana/microarchitectures/spring crest · revision 3688 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-de6b897db5034289","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Nervana","unit":"","sourceId":"chipswiki-1181-r3688","location":"Nervana/microarchitectures/spring crest · revision 3688 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-de6b897db5034289","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1181-r3688","location":"Nervana/microarchitectures/spring crest · revision 3688 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-de6b897db5034289","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-1181-r3688","location":"Nervana/microarchitectures/spring crest · revision 3688 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-de6b897db5034289","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1181-r3688","location":"Nervana/microarchitectures/spring crest · revision 3688 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-de6b897db5034289","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Lake Crest","unit":"","sourceId":"chipswiki-1181-r3688","location":"Nervana/microarchitectures/spring crest · revision 3688 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-de6b897db5034289","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1181-r3688"],"url":"https://museum.vlsi.kr/objects/cw-de6b897db5034289"},{"id":"cw-de7a7d6df31345b5","name":"Core i5-2540M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2540m"],"fields":[{"key":"Model name","value":"Core i5-2540M","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2540M","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700839209","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700839411","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR044","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR046","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7949-r25497","location":"Intel/core i5/i5-2540m · revision 25497 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-de7a7d6df31345b5","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7949-r25497","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-de7a7d6df31345b5"},{"id":"cw-deac052791a668dd","name":"Core i5-5575R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i5 i5-5575r"],"fields":[{"key":"Model name","value":"Intel Core i5-5575R","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-5575R","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802483402","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5500,"unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2AK","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"G0","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7933-r25477","location":"Intel/core i5/i5-5575r · revision 25477 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-deac052791a668dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7933-r25477","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-deac052791a668dd"},{"id":"cw-df05da15dc2191e9","name":"R-Car E1","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"1st Gen","year":2012,"architecture":"Cortex-A9","process":"40 nm","aliases":["Renesas r-car e1"],"fields":[{"key":"Model name","value":"R-Car E1","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E1","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"μPD35004","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 25, 2011","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2012","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"1st Gen","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":533,"unit":"MHz","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.1,"unit":"V","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.99,"unit":"GiB/s","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX531","unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":1,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":177,"unit":"MHz","sourceId":"chipswiki-7653-r24914","location":"Renesas/r-car/e1 · revision 24914 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-429","unit":"","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":429,"unit":"","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":18,"unit":"mm","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":18,"unit":"mm","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-df05da15dc2191e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7653-r24914","chipswiki-31426-r92295"],"url":"https://museum.vlsi.kr/objects/cw-df05da15dc2191e9"},{"id":"cw-df210ae9f635961a","name":"Am186CU-40KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CU","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cu-40ki\\w"],"fields":[{"key":"Model name","value":"Am186CU-40KI\\W","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CU-40KI\\W","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CU-40KI\\W","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CU","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14678-r44739","location":"Amd/am186cx/am186cu-40ki\\w · revision 44739 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-df210ae9f635961a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14678-r44739"],"url":"https://museum.vlsi.kr/objects/cw-df210ae9f635961a"},{"id":"cw-dfc860fbaf7b4956","name":"Core i7-4860HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4860hq"],"fields":[{"key":"Model name","value":"Intel Core i7-4860HQ","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4860HQ","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701510800","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 19, 2014","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2014","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1BP","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7865-r25368","location":"Intel/core i7/i7-4860hq · revision 25368 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc860fbaf7b4956","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7865-r25368","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-dfc860fbaf7b4956"},{"id":"cw-dfc9e1976271437a","name":"K6-2/250AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-250afr"],"fields":[{"key":"Model name","value":"K6-2/250AFR","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/250AFR","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/250AFR","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":249.99,"unit":"MHz","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"83.33 MT/s","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8387-r26082","location":"Amd/k6-2/k6-2-250afr · revision 26082 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-dfc9e1976271437a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8387-r26082"],"url":"https://museum.vlsi.kr/objects/cw-dfc9e1976271437a"},{"id":"cw-e028fb4a1cc110ba","name":"Celeron 3955U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron 3955u"],"fields":[{"key":"Model name","value":"Celeron 3955U","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3955U","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201931006","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EW","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2015","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 27, 2015","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-8036-r25667","location":"Intel/celeron/3955u · revision 25667 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e028fb4a1cc110ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8036-r25667","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e028fb4a1cc110ba"},{"id":"cw-e032116ff65fa9be","name":"K6-2E+/450ICR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-450icr"],"fields":[{"key":"Model name","value":"K6-2E+/450ICR","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/450ICR","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/450ICR","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":450,"unit":"MHz","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17.5,"unit":"W","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1007-r2858","location":"Amd/k6-2+/k6-2e+-450icr · revision 2858 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OBGA-349","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":349,"unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.47,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-e032116ff65fa9be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1007-r2858","chipswiki-31127-r91599"],"url":"https://museum.vlsi.kr/objects/cw-e032116ff65fa9be"},{"id":"cw-e0350b854f2f729d","name":"R-Car M1A","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"1st Gen","year":2012,"architecture":"Cortex-A9","process":"40 nm","aliases":["Renesas r-car m1a"],"fields":[{"key":"Model name","value":"R-Car M1A","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M1A","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A77781","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 16, 2011","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2012","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"1st Gen","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SH-4A","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":7.95,"unit":"GiB/s","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX540","unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":200,"unit":"MHz","sourceId":"chipswiki-7647-r24907","location":"Renesas/r-car/m1a · revision 24907 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-472","unit":"","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":472,"unit":"","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":21,"unit":"mm","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":21,"unit":"mm","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0350b854f2f729d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7647-r24907","chipswiki-31427-r92297"],"url":"https://museum.vlsi.kr/objects/cw-e0350b854f2f729d"},{"id":"cw-e06468e925b3e6c1","name":"Ryzen 7 4800U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4800u"],"fields":[{"key":"Model name","value":"Ryzen 7 4800U","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4800U","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000082","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1750,"unit":"MHz","sourceId":"chipswiki-695-r1690","location":"Amd/ryzen 7/4800u · revision 1690 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e06468e925b3e6c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-695-r1690"],"url":"https://museum.vlsi.kr/objects/cw-e06468e925b3e6c1"},{"id":"cw-e0a589309b3da582","name":"z12","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2012,"process":"32 nm","aliases":["Ibm microarchitectures z12"],"fields":[{"key":"Architecture name","value":"z12","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 28, 2012","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z196","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z13","unit":"","sourceId":"chipswiki-13214-r38677","location":"Ibm/microarchitectures/z12 · revision 38677 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-e0a589309b3da582","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13214-r38677"],"url":"https://museum.vlsi.kr/objects/cw-e0a589309b3da582"},{"id":"cw-e0adf92e6bfda2cb","name":"Core i3-2332M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2332m"],"fields":[{"key":"Model name","value":"Core i3-2332M","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2332M","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701084501","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR09R","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2011","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2011","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8012-r25593","location":"Intel/core i3/i3-2332m · revision 25593 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0adf92e6bfda2cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8012-r25593","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-e0adf92e6bfda2cb"},{"id":"cw-e0b8be927e8a582f","name":"CN5830-900 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-900bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5830-900 EXP","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-900 EXP","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-900BG1521-EXP","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8152-r25811","location":"Cavium/octeon plus/cn5830-900bg1521-exp · revision 25811 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e0b8be927e8a582f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8152-r25811","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-e0b8be927e8a582f"},{"id":"cw-e0c32d94360ab396","name":"Core i7-8709G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-8709g"],"fields":[{"key":"Model name","value":"Core i7-8709G","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8709G","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake G","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","alternatives":[{"value":"DDR4-2400","sourceId":"chipswiki-5287-r17293","reason":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / type 2. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-e0c32d94360ab396","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory ECC — Memory controller (section 1)","value":"No","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 1)","value":64,"unit":"GiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":1,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":2,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller / HBM 2 (section 2)","value":"HBM2","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller / HBM 2 (section 2)","value":4,"unit":"GiB","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller / HBM 2 (section 2)","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Integrated graphics (section 1)","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Integrated graphics (section 1)","value":24,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Integrated graphics (section 1)","value":3,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Integrated graphics (section 1)","value":350,"unit":"MHz","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Integrated graphics (section 1)","value":1100,"unit":"MHz","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Discrete graphics (section 2)","value":"Radeon RX Vega M GH","unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Discrete graphics (section 2)","value":24,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Discrete graphics (section 2)","value":1063,"unit":"MHz","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Discrete graphics (section 2)","value":1190,"unit":"MHz","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Discrete graphics (section 2)","value":6,"unit":"","sourceId":"chipswiki-5287-r17293","location":"Intel/core i7/i7-8709g · revision 17293 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-e0c32d94360ab396","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5287-r17293"],"url":"https://museum.vlsi.kr/objects/cw-e0c32d94360ab396"},{"id":"cw-e0ec1c8eca252c9d","name":"Am186EM–25VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–25vc\\w"],"fields":[{"key":"Model name","value":"Am186EM–25VC\\W","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–25VC\\W","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–25VC\\W","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14653-r44714","location":"Amd/am186ex/am186em–25vc\\w · revision 44714 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e0ec1c8eca252c9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14653-r44714"],"url":"https://museum.vlsi.kr/objects/cw-e0ec1c8eca252c9d"},{"id":"cw-e10be546efafbfe8","name":"Celeron 3865U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3800","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron 3865u"],"fields":[{"key":"Model name","value":"Celeron 3865U","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3865U","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR349","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3800,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-3891-r12302","location":"Intel/celeron/3865u · revision 12302 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","sourceDate":"2019-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-11. Not an independent measurement.","entityId":"cw-e10be546efafbfe8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3891-r12302","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e10be546efafbfe8"},{"id":"cw-e12f05ef86b9bd51","name":"Xeon E5-1620 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-1000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-1620 v4"],"fields":[{"key":"Model name","value":"Xeon E5-1620 v4","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-1620 v4","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002044103","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80660E51620V4","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-1000","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P6","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP Workstation","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2.5 MiB","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7592-r24676","location":"Intel/xeon e5/e5-1620 v4 · revision 24676 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-e12f05ef86b9bd51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7592-r24676"],"url":"https://museum.vlsi.kr/objects/cw-e12f05ef86b9bd51"},{"id":"cw-e17115b645c2bf8c","name":"Athlon MP 2400+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2002,"architecture":"K7","process":"130 nm","aliases":["Amd athlon mp amsn2400dut3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2400+","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2400+","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2400DUT3C","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 10, 2002","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 10, 2002","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":85,"unit":"mm²","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8448-r26641","location":"Amd/athlon mp/amsn2400dut3c · revision 26641 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e17115b645c2bf8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8448-r26641","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-e17115b645c2bf8c"},{"id":"cw-e18dfbda38b6fc2e","name":"Core i7-2669M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2669m"],"fields":[{"key":"Model name","value":"Core i7-2669M","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2669M","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700851205","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04E","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7885-r25389","location":"Intel/core i7/i7-2669m · revision 25389 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e18dfbda38b6fc2e","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7885-r25389","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-e18dfbda38b6fc2e"},{"id":"cw-e198ca3d58bfe042","name":"Core i5-8365U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2019,"architecture":"Whiskey Lake","process":"14 nm","aliases":["Intel core i5 i5-8365u"],"fields":[{"key":"Model name","value":"Core i5-8365U","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8365U","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-2925-r9783","location":"Intel/core i5/i5-8365u · revision 9783 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-e198ca3d58bfe042","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2925-r9783"],"url":"https://museum.vlsi.kr/objects/cw-e198ca3d58bfe042"},{"id":"cw-e1edb5b3947bd230","name":"CN3005-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3005-400bg350-scp"],"fields":[{"key":"Model name","value":"Cavium CN3005-400 SCP","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3005-400 SCP","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3005-400BG350-SCP","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-350","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,017 MiB/s","unit":"","sourceId":"chipswiki-8278-r25938","location":"Cavium/octeon/cn3005-400bg350-scp · revision 25938 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1edb5b3947bd230","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8278-r25938"],"url":"https://museum.vlsi.kr/objects/cw-e1edb5b3947bd230"},{"id":"cw-e1f2b2ad340e6c27","name":"Celeron J4105","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Goldmont Plus","process":"14 nm","aliases":["Intel celeron j4105"],"fields":[{"key":"Model name","value":"Celeron J4105","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J4105","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068003067403","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3S4","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","alternatives":[{"value":"16 GiB","sourceId":"chipswiki-1016-r2874","reason":"Intel/celeron/j4105 · revision 2874 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 600","unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":250,"unit":"MHz","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":750,"unit":"MHz","sourceId":"chipswiki-1016-r2874","location":"Intel/celeron/j4105 · revision 2874 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","sourceDate":"2020-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1090","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1090,"unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-23. Not an independent measurement.","entityId":"cw-e1f2b2ad340e6c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1016-r2874","chipswiki-31338-r92075"],"url":"https://museum.vlsi.kr/objects/cw-e1f2b2ad340e6c27"},{"id":"cw-e1f755376ca8863c","name":"Xeon E5-4627 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4627 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4627 v4","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4627 v4","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002330800","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SN","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":25,"unit":"MiB","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7714-r25086","location":"Intel/xeon e5/e5-4627 v4 · revision 25086 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e1f755376ca8863c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7714-r25086"],"url":"https://museum.vlsi.kr/objects/cw-e1f755376ca8863c"},{"id":"cw-e2400082a0c02232","name":"Core i3-6157U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6157u"],"fields":[{"key":"Model name","value":"Core i3-6157U","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6157U","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202498907","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2XA","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2016","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2016","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 550","unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7981-r25558","location":"Intel/core i3/i3-6157u · revision 25558 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2400082a0c02232","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7981-r25558","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e2400082a0c02232"},{"id":"cw-e240313bd1d0d088","name":"Am186CC-40KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CC","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cc-40ki\\w"],"fields":[{"key":"Model name","value":"Am186CC-40KI\\W","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CC-40KI\\W","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CC-40KI\\W","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CC","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14688-r44749","location":"Amd/am186cx/am186cc-40ki\\w · revision 44749 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e240313bd1d0d088","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14688-r44749"],"url":"https://museum.vlsi.kr/objects/cw-e240313bd1d0d088"},{"id":"cw-e25b615ebe3b853d","name":"CN5750-1000 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5750-1000bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5750-1000 SP","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5750-1000 SP","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5750-1000BG1217-SP","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8169-r25828","location":"Cavium/octeon plus/cn5750-1000bg1217-sp · revision 25828 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e25b615ebe3b853d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8169-r25828","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-e25b615ebe3b853d"},{"id":"cw-e2891764ae1db65c","name":"Ryzen 9 5980HX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 9 5980hx"],"fields":[{"key":"Model name","value":"Ryzen 9 5980HX","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5980HX","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000474","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-552-r1142","location":"Amd/ryzen 9/5980hx · revision 1142 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-31. Not an independent measurement.","entityId":"cw-e2891764ae1db65c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","sourceDate":"2021-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-552-r1142"],"url":"https://museum.vlsi.kr/objects/cw-e2891764ae1db65c"},{"id":"cw-e2ca1cf43c36b4ea","name":"Celeron P4600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P4000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel celeron p4600"],"fields":[{"key":"Model name","value":"Intel Celeron P4600","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P4600","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617005307AB","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2010","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2010","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P4000","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZY","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":667,"unit":"MHz","sourceId":"chipswiki-8024-r25606","location":"Intel/celeron/p4600 · revision 25606 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2ca1cf43c36b4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8024-r25606","chipswiki-31578-r92969"],"url":"https://museum.vlsi.kr/objects/cw-e2ca1cf43c36b4ea"},{"id":"cw-e2e6b9814501cf00","name":"CN3110-400 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-400bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3110-400 CP","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-400 CP","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-400BG868-CP","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8265-r25925","location":"Cavium/octeon/cn3110-400bg868-cp · revision 25925 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e2e6b9814501cf00","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8265-r25925","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-e2e6b9814501cf00"},{"id":"cw-e307e4ce0503e7e7","name":"CN3120-500 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-500bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3120-500 CP","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-500 CP","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-500BG868-CP","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8245-r25905","location":"Cavium/octeon/cn3120-500bg868-cp · revision 25905 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e307e4ce0503e7e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8245-r25905","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-e307e4ce0503e7e7"},{"id":"cw-e31179fe1fc9acac","name":"K6-2E/233AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-233amz"],"fields":[{"key":"Model name","value":"K6-2E/233AMZ","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/233AMZ","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/233AMZ","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8330-r26025","location":"Amd/k6-2/k6-2e-233amz · revision 26025 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e31179fe1fc9acac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8330-r26025"],"url":"https://museum.vlsi.kr/objects/cw-e31179fe1fc9acac"},{"id":"cw-e314b2c2146274d5","name":"Xeon E3-1275 v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1275 v5"],"fields":[{"key":"Model name","value":"Xeon E3-1275 v5","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1275 v5","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201934909","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662E31275V5","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2CT","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LK","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v5","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P530","unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-6443-r20141","location":"Intel/xeon e3/e3-1275 v5 · revision 20141 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-e314b2c2146274d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6443-r20141"],"url":"https://museum.vlsi.kr/objects/cw-e314b2c2146274d5"},{"id":"cw-e36ca09b5382c0ab","name":"Helio X25 (MT6797T)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2016,"architecture":"Cortex-A53","process":"20 nm","aliases":["Mediatek helio mt6797t"],"fields":[{"key":"Model name","value":"MediaTek Helio X25","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X25","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6797T","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6797T","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 12, 2015","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2016","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2500,"unit":"MHz","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1550,"unit":"MHz","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","alternatives":[{"value":"4 GiB","sourceId":"chipswiki-1849-r6279","reason":"Mediatek/helio/mt6797t · revision 6279 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory type","value":"LPDDR3-1600","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"12.8 GB/s (11.92 GiB/s)","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":850,"unit":"MHz","sourceId":"chipswiki-1849-r6279","location":"Mediatek/helio/mt6797t · revision 6279 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-12. Not an independent measurement.","entityId":"cw-e36ca09b5382c0ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","sourceDate":"2019-09-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1849-r6279"],"url":"https://museum.vlsi.kr/objects/cw-e36ca09b5382c0ab"},{"id":"cw-e36f83f130cef89c","name":"ET-Minion","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Esperanto","year":2018,"process":"7 nm","aliases":["Esperanto microarchitectures et-minion"],"fields":[{"key":"Architecture name","value":"ET-Minion","unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Esperanto","unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"RV64","unit":"","sourceId":"chipswiki-7135-r22516","location":"Esperanto/microarchitectures/et-minion · revision 22516 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-09. Not an independent measurement.","entityId":"cw-e36f83f130cef89c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","sourceDate":"2018-02-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7135-r22516"],"url":"https://museum.vlsi.kr/objects/cw-e36f83f130cef89c"},{"id":"cw-e372ac0260c94bb7","name":"Knights Mill","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2017,"process":"14 nm","aliases":["Intel microarchitectures knights mill"],"fields":[{"key":"Architecture name","value":"Knights Mill","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"December 18, 2017","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-16","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Knights Corner","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Knights Hill","unit":"","sourceId":"chipswiki-2490-r8521","location":"Intel/microarchitectures/knights mill · revision 8521 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-20. Not an independent measurement.","entityId":"cw-e372ac0260c94bb7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","sourceDate":"2019-05-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2490-r8521"],"url":"https://museum.vlsi.kr/objects/cw-e372ac0260c94bb7"},{"id":"cw-e3770248e2bf62c1","name":"Xeon D-1622","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1622"],"fields":[{"key":"Model name","value":"Xeon D-1622","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1622","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":40,"unit":"W","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3685-r11013","location":"Intel/xeon d/d-1622 · revision 11013 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e3770248e2bf62c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3685-r11013"],"url":"https://museum.vlsi.kr/objects/cw-e3770248e2bf62c1"},{"id":"cw-e396e354ce1c8f2b","name":"EPYC 7742","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7742"],"fields":[{"key":"Model name","value":"EPYC 7742","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7742,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000053","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000053WOF","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2250,"unit":"MHz","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64x512 KiB","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x16 MiB","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-869-r2253","location":"Amd/epyc/7742 · revision 2253 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-e396e354ce1c8f2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-869-r2253"],"url":"https://museum.vlsi.kr/objects/cw-e396e354ce1c8f2b"},{"id":"cw-e3aa6bd377ba503a","name":"J8086-2B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 j8086-2b"],"fields":[{"key":"Model name","value":"AMD J8086-2B","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J8086-2B","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J8086-2B","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J8086","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8504-r26697","location":"Amd/am8086/j8086-2b · revision 26697 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3aa6bd377ba503a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8504-r26697"],"url":"https://museum.vlsi.kr/objects/cw-e3aa6bd377ba503a"},{"id":"cw-e3ae9cbe3a110213","name":"Am486DX-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dx-33"],"fields":[{"key":"Model name","value":"Am486DX-33","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX-33","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-33","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 1993","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":89,"unit":"mm²","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8574-r26772","location":"Amd/am486/am486dx-33 · revision 26772 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3ae9cbe3a110213","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8574-r26772"],"url":"https://museum.vlsi.kr/objects/cw-e3ae9cbe3a110213"},{"id":"cw-e3d21517b1379b17","name":"Ryzen 7 2700U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 7 2700u"],"fields":[{"key":"Model name","value":"Ryzen 7 2700U","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2700U","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 26, 2017","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 26, 2017","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 10","unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":10,"unit":"","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-2534-r8710","location":"Amd/ryzen 7/2700u · revision 8710 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-e3d21517b1379b17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2534-r8710","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-e3d21517b1379b17"},{"id":"cw-e3de770b18a92b93","name":"Core i3-1000G4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i3 i3-1000g4"],"fields":[{"key":"Model name","value":"Core i3-1000G4","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-1000G4","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-10000","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake Y","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9,"unit":"W","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x48 KiB","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":32,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-1238-r3947","location":"Intel/core i3/i3-1000g4 · revision 3947 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-e3de770b18a92b93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1238-r3947"],"url":"https://museum.vlsi.kr/objects/cw-e3de770b18a92b93"},{"id":"cw-e3f91104e1d338de","name":"Am486DX4-90NV8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4V","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-90nv8t"],"fields":[{"key":"Model name","value":"Am486DX4-90NV8T","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-90NV8T","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX4-90NV8T","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4V","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":90,"unit":"MHz","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"30 MT/s","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8546-r26742","location":"Amd/am486/am486dx4-90nv8t · revision 26742 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e3f91104e1d338de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8546-r26742"],"url":"https://museum.vlsi.kr/objects/cw-e3f91104e1d338de"},{"id":"cw-e404e85acd149042","name":"Rosetta","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Cray","year":2019,"process":"16 nm","aliases":["Cray microarchitectures rosetta"],"fields":[{"key":"Architecture name","value":"Rosetta","unit":"","sourceId":"chipswiki-961-r2714","location":"Cray/microarchitectures/rosetta · revision 2714 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-e404e85acd149042","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cray%2Fmicroarchitectures%2Frosetta&oldid=2714","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cray","unit":"","sourceId":"chipswiki-961-r2714","location":"Cray/microarchitectures/rosetta · revision 2714 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-e404e85acd149042","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cray%2Fmicroarchitectures%2Frosetta&oldid=2714","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-961-r2714","location":"Cray/microarchitectures/rosetta · revision 2714 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-e404e85acd149042","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cray%2Fmicroarchitectures%2Frosetta&oldid=2714","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-961-r2714","location":"Cray/microarchitectures/rosetta · revision 2714 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-e404e85acd149042","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cray%2Fmicroarchitectures%2Frosetta&oldid=2714","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-961-r2714","location":"Cray/microarchitectures/rosetta · revision 2714 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-e404e85acd149042","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cray%2Fmicroarchitectures%2Frosetta&oldid=2714","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-961-r2714"],"url":"https://museum.vlsi.kr/objects/cw-e404e85acd149042"},{"id":"cw-e40e4099fdc3efb3","name":"Xeon Gold 5218","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5218"],"fields":[{"key":"Model name","value":"Xeon Gold 5218","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5218,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504193301","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806955218","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF8T","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1523-r4975","location":"Intel/xeon gold/5218 · revision 4975 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e40e4099fdc3efb3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1523-r4975"],"url":"https://museum.vlsi.kr/objects/cw-e40e4099fdc3efb3"},{"id":"cw-e4245971cf891c66","name":"Helio P15 (MT6755T)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2017,"architecture":"Cortex-A53","process":"28 nm","aliases":["Mediatek helio mt6755t"],"fields":[{"key":"Model name","value":"Helio P15","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P15","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6755T","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 17, 2016","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2017","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1200,"unit":"MHz","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":6.95,"unit":"GiB/s","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T860","unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":800,"unit":"MHz","sourceId":"chipswiki-1636-r5644","location":"Mediatek/helio/mt6755t · revision 5644 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-04. Not an independent measurement.","entityId":"cw-e4245971cf891c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","sourceDate":"2019-11-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1636-r5644"],"url":"https://museum.vlsi.kr/objects/cw-e4245971cf891c66"},{"id":"cw-e47bfadd27403292","name":"Xeon D-1627","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1627"],"fields":[{"key":"Model name","value":"Xeon D-1627","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1627","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3682-r11010","location":"Intel/xeon d/d-1627 · revision 11010 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-e47bfadd27403292","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3682-r11010"],"url":"https://museum.vlsi.kr/objects/cw-e47bfadd27403292"},{"id":"cw-e49ab618b51d27dd","name":"CN5830-1000 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-1000bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5830-1000 SCP","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-1000 SCP","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-1000BG1521-SCP","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8159-r25818","location":"Cavium/octeon plus/cn5830-1000bg1521-scp · revision 25818 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e49ab618b51d27dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8159-r25818","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-e49ab618b51d27dd"},{"id":"cw-e4b001adf7ea08d9","name":"AMD-K5-PR166ABX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1997,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr166abx"],"fields":[{"key":"Model name","value":"AMD-K5-PR166ABX","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR166ABX","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR166ABX","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":116.66,"unit":"MHz","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":2,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8395-r26091","location":"Amd/k5/amd-k5-pr166abx · revision 26091 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4b001adf7ea08d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8395-r26091"],"url":"https://museum.vlsi.kr/objects/cw-e4b001adf7ea08d9"},{"id":"cw-e4d0e0d368f56537","name":"Gen11","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2018,"process":"10 nm","aliases":["Intel microarchitectures gen11"],"fields":[{"key":"Architecture name","value":"Gen11","unit":"","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen10","unit":"","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen12","unit":"","sourceId":"chipswiki-5102-r16631","location":"Intel/microarchitectures/gen11 · revision 16631 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-09. Not an independent measurement.","entityId":"cw-e4d0e0d368f56537","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","sourceDate":"2018-08-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5102-r16631"],"url":"https://museum.vlsi.kr/objects/cw-e4d0e0d368f56537"},{"id":"cw-e4d2bd693102c931","name":"Ryzen 7 PRO 1700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen PRO","year":null,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 7 pro 1700"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 1700","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 1700","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD170BBBM88AE","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen PRO","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Summit Ridge","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-7352-r23747","location":"Amd/ryzen 7/pro 1700 · revision 23747 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-e4d2bd693102c931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7352-r23747","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-e4d2bd693102c931"},{"id":"cw-e4d7cf992ca8ff80","name":"Exynos 9810","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2018,"architecture":"Exynos M3","process":"10 nm","aliases":["Samsung exynos 9810"],"fields":[{"key":"Model name","value":"Exynos 9810","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9810,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2018","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 25, 2018","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2886,"unit":"MHz","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2002,"unit":"MHz","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2704,"unit":"MHz","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","alternatives":[{"value":"2886 MHz","sourceId":"chipswiki-288-r579","reason":"Samsung/exynos/9810 · revision 579 · {{chip}} / turbo frequency. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-e4d7cf992ca8ff80","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Exynos M3","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Meerkat","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118.94,"unit":"mm²","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":384,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x512 KiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"16-way set associative","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 1)","value":4,"unit":"MiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 1)","value":"1x4 MiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"2-way set associative","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"1x256 KiB","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"16-way set associative","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G72","unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":18,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":600,"unit":"MHz","sourceId":"chipswiki-288-r579","location":"Samsung/exynos/9810 · revision 579 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-16. Not an independent measurement.","entityId":"cw-e4d7cf992ca8ff80","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","sourceDate":"2022-07-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-288-r579"],"url":"https://museum.vlsi.kr/objects/cw-e4d7cf992ca8ff80"},{"id":"cw-e4e8553290a604be","name":"i486SX-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SX","year":1992,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486sx-33"],"fields":[{"key":"Model name","value":"Intel i486SX-33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SX-33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX-33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SB80486SX-33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FA80486SX-33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SX-33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FA80486SX33","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 21, 1992","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SX","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK798","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK903","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX680","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX789","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX797","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX847","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX902","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX931","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX684","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX724","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 10","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 10","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 10","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX780","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 11","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 11","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 11","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX781","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 12","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 12","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 12","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX791","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 13","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 13","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 13","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX799","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 14","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 14","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 14","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX834","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 15","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 15","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 15","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX849","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 16","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 16","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 16","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX853","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 17","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 17","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 17","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX855","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 18","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 18","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 18","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX935","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / s-spec 19","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 19","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"s-spec 19","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1185000,"unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8078-r25729","location":"Intel/80486/486sx-33 · revision 25729 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e4e8553290a604be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8078-r25729"],"url":"https://museum.vlsi.kr/objects/cw-e4e8553290a604be"},{"id":"cw-e4fa4ed035bb6186","name":"ARM9","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":1997,"aliases":["Arm holdings microarchitectures arm9"],"fields":[{"key":"Architecture name","value":"ARM9","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 16, 1997","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM8","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM10","unit":"","sourceId":"chipswiki-934-r2600","location":"Arm holdings/microarchitectures/arm9 · revision 2600 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-09. Not an independent measurement.","entityId":"cw-e4fa4ed035bb6186","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","sourceDate":"2020-10-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-934-r2600"],"url":"https://museum.vlsi.kr/objects/cw-e4fa4ed035bb6186"},{"id":"cw-e526ca22ff138b70","name":"Ryzen 7 4800HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4800hs"],"fields":[{"key":"Model name","value":"Ryzen 7 4800HS","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4800HS","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-686-r1680","location":"Amd/ryzen 7/4800hs · revision 1680 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-e526ca22ff138b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-686-r1680"],"url":"https://museum.vlsi.kr/objects/cw-e526ca22ff138b70"},{"id":"cw-e529da258687f1a6","name":"Pentium 907","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) 907"],"fields":[{"key":"Model name","value":"Pentium 907","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":907,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148301","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085200","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085201","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FG","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08Y","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F5","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V8","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-7799-r25237","location":"Intel/pentium (2009)/907 · revision 25237 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e529da258687f1a6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7799-r25237","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-e529da258687f1a6"},{"id":"cw-e5517eb7fc34b559","name":"Am186EDLV–25VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186edlv–25vc\\w"],"fields":[{"key":"Model name","value":"Am186EDLV–20VC\\W","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EDLV–20VC\\W","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EDLV–20VC\\W","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14673-r44734","location":"Amd/am186ex/am186edlv–25vc\\w · revision 44734 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e5517eb7fc34b559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14673-r44734"],"url":"https://museum.vlsi.kr/objects/cw-e5517eb7fc34b559"},{"id":"cw-e59a781ce5e5141b","name":"Xeon E5-4650 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4650 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4650 v4","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4650 v4","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002028621","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SA","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x256 KiB","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35,"unit":"MiB","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x2.5 MiB","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7712-r25083","location":"Intel/xeon e5/e5-4650 v4 · revision 25083 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e59a781ce5e5141b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7712-r25083"],"url":"https://museum.vlsi.kr/objects/cw-e59a781ce5e5141b"},{"id":"cw-e5cd15de7515385a","name":"Xeon E7-8850","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-8800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-8850"],"fields":[{"key":"Model name","value":"Xeon E7-8850","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8850","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007446AA","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8800","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3D","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.56,"unit":"MiB","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.4 MiB","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7694-r25064","location":"Intel/xeon e7/e7-8850 · revision 25064 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5cd15de7515385a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7694-r25064","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-e5cd15de7515385a"},{"id":"cw-e5daf5e6c1799226","name":"AM9080ADC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080adc"],"fields":[{"key":"Model name","value":"AMD AM9080ADC","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080ADC","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080ADC","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8469-r26662","location":"Amd/am9080/am9080adc · revision 26662 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5daf5e6c1799226","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8469-r26662"],"url":"https://museum.vlsi.kr/objects/cw-e5daf5e6c1799226"},{"id":"cw-e5f4bc7eef621081","name":"Ryzen Embedded V2516","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V2000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen embedded v2516"],"fields":[{"key":"Model name","value":"Ryzen Embedded V2516","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V2516","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000243","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 10, 2020","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 10, 2020","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V2000","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3950,"unit":"MHz","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Grey Hawk","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6 × 32 KiB","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6 × 32 KiB","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6 × 512 KiB","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 4 MiB","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-882-r2293","location":"Amd/ryzen embedded/v2516 · revision 2293 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-e5f4bc7eef621081","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-882-r2293"],"url":"https://museum.vlsi.kr/objects/cw-e5f4bc7eef621081"},{"id":"cw-e5fa854edffd80bc","name":"CN3110-500 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-500bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3110-500 CP","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-500 CP","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-500BG868-CP","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8261-r25921","location":"Cavium/octeon/cn3110-500bg868-cp · revision 25921 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e5fa854edffd80bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8261-r25921","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-e5fa854edffd80bc"},{"id":"cw-e63796f00ca22744","name":"Core i5-6400T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6400t"],"fields":[{"key":"Model name","value":"Core i5-6400T","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6400T","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2BS","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7922-r25461","location":"Intel/core i5/i5-6400t · revision 25461 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e63796f00ca22744","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7922-r25461","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-e63796f00ca22744"},{"id":"cw-e63b9b603517275f","name":"EPYC 7453","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7453"],"fields":[{"key":"Model name","value":"EPYC 7453","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7453,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000319","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000319WOF","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2750,"unit":"MHz","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3450,"unit":"MHz","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1792,"unit":"KiB","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28 × 32 KiB","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28 × 32 KiB","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28 × 512 KiB","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 16 MiB","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-733-r1754","location":"Amd/epyc/7453 · revision 1754 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-e63b9b603517275f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-733-r1754"],"url":"https://museum.vlsi.kr/objects/cw-e63b9b603517275f"},{"id":"cw-e6439389d5831825","name":"EPYC Embedded 3101","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3101"],"fields":[{"key":"Model name","value":"EPYC Embedded 3101","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3101,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3101BIR4KAF","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 8 MiB","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"42.67 GB/s","unit":"","sourceId":"chipswiki-411-r881","location":"Amd/epyc embedded/3101 · revision 881 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4r2","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-e6439389d5831825","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-411-r881","chipswiki-31098-r91557"],"url":"https://museum.vlsi.kr/objects/cw-e6439389d5831825"},{"id":"cw-e6752a949c1f2e62","name":"Core i3-7100U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2016,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7100u"],"fields":[{"key":"Model name","value":"Intel Core i3-7100U","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7100U","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067702739738","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZW","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR343","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7974-r25548","location":"Intel/core i3/i3-7100u · revision 25548 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6752a949c1f2e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7974-r25548","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e6752a949c1f2e62"},{"id":"cw-e69fab95099e406d","name":"Core i3-7130U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7130u"],"fields":[{"key":"Model name","value":"Core i3-7130U","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7130U","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7969-r25541","location":"Intel/core i3/i3-7130u · revision 25541 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e69fab95099e406d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7969-r25541","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e69fab95099e406d"},{"id":"cw-e6b074bcd2ca1c27","name":"POWER8+","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2016,"process":"22 nm","aliases":["Ibm microarchitectures power8+"],"fields":[{"key":"Architecture name","value":"POWER8+","unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2016,"unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER8","unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER9","unit":"","sourceId":"chipswiki-184-r369","location":"Ibm/microarchitectures/power8+ · revision 369 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-26. Not an independent measurement.","entityId":"cw-e6b074bcd2ca1c27","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","sourceDate":"2022-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-184-r369"],"url":"https://museum.vlsi.kr/objects/cw-e6b074bcd2ca1c27"},{"id":"cw-e6b5d85b325b2380","name":"Core i3-2370M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2370m"],"fields":[{"key":"Model name","value":"Core i3-2370M","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2370M","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700996006","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700996206","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0DP","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0DR","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2012","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2012","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-8002-r25583","location":"Intel/core i3/i3-2370m · revision 25583 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6b5d85b325b2380","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8002-r25583","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-e6b5d85b325b2380"},{"id":"cw-e6daf9661623251b","name":"Core i7-4750HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2013,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4750hq"],"fields":[{"key":"Model name","value":"Intel Core i7-4750HQ","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4750HQ","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701510101","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 4, 2013","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 2, 2013","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR18J","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7872-r25375","location":"Intel/core i7/i7-4750hq · revision 25375 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e6daf9661623251b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7872-r25375","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-e6daf9661623251b"},{"id":"cw-e70d69a302b5ea3a","name":"Core i3-7110U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7110u"],"fields":[{"key":"Model name","value":"Intel Core i3-7110U","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7110U","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34H","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34J","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 2017","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","alternatives":[{"value":"64 GiB","sourceId":"chipswiki-7972-r25544","reason":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7972-r25544","location":"Intel/core i3/i3-7110u · revision 25544 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e70d69a302b5ea3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7972-r25544","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e70d69a302b5ea3a"},{"id":"cw-e721d8f0c8b53c61","name":"Xeon Platinum 8160T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8160t"],"fields":[{"key":"Model name","value":"Xeon Platinum 8160T","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8160T","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303592800","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J6","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1473-r4920","location":"Intel/xeon platinum/8160t · revision 4920 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-e721d8f0c8b53c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1473-r4920"],"url":"https://museum.vlsi.kr/objects/cw-e721d8f0c8b53c61"},{"id":"cw-e7282d3a8a5b6cdc","name":"Am486DX2-100V8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-100v8b"],"fields":[{"key":"Model name","value":"Am486DX2-100V8B","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-100V8B","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-100V8B","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8570-r26768","location":"Amd/am486/am486dx2-100v8b · revision 26768 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7282d3a8a5b6cdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8570-r26768"],"url":"https://museum.vlsi.kr/objects/cw-e7282d3a8a5b6cdc"},{"id":"cw-e73e34ca4ddcd658","name":"Core i3-7320T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7000","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7320t"],"fields":[{"key":"Model name","value":"Core i3-7320T","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7320T","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35N","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7000","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":92,"unit":"°C","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7964-r25534","location":"Intel/core i3/i3-7320t · revision 25534 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e73e34ca4ddcd658","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7964-r25534"],"url":"https://museum.vlsi.kr/objects/cw-e73e34ca4ddcd658"},{"id":"cw-e760c27727e81139","name":"Exynos 5260","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 5","year":2014,"architecture":"Cortex-A15","process":"28 nm","aliases":["Samsung exynos 5260"],"fields":[{"key":"Model name","value":"Exynos 5260","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5260,"unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 2014","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 2014","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 5","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1700,"unit":"MHz","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1300,"unit":"MHz","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6851-r21347","location":"Samsung/exynos/5260 · revision 21347 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-e760c27727e81139","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6851-r21347"],"url":"https://museum.vlsi.kr/objects/cw-e760c27727e81139"},{"id":"cw-e769a3c267edb260","name":"i486DX4-100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX4","year":1994,"architecture":"80486","process":"600 nm","aliases":["Intel 80486 486dx4-100"],"fields":[{"key":"Model name","value":"Intel i486DX4-100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX4-100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4WB100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MA80486DX4-100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"TQ80486DX4100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX4-100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX4100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FC80486DX4-100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FC80486DX4WB100","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / part number 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"part number 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 7, 1994","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX4","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK050","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK051","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK096","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK851","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX877","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX900","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX908","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK053","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK063","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK099","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 10","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 10","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 10","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2M9","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 11","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 11","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 11","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX876","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 12","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 12","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 12","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX906","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / s-spec 13","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 13","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"s-spec 13","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":600,"unit":"nm","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8087-r25738","location":"Intel/80486/486dx4-100 · revision 25738 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e769a3c267edb260","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8087-r25738"],"url":"https://museum.vlsi.kr/objects/cw-e769a3c267edb260"},{"id":"cw-e76c08dd3c22ca3d","name":"R-Car H3","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"3rd Gen","year":2018,"architecture":"Cortex-A53","process":"16 nm","aliases":["Renesas r-car h3"],"fields":[{"key":"Model name","value":"R-Car H3","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"H3","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A77950","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2, 2015","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2018","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"3rd Gen","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-R7","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":111.36,"unit":"mm²","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.8,"unit":"V","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x48 KiB","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x2 MiB","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"1x512 KiB","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-3200","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GX6650","unit":"","sourceId":"chipswiki-4178-r13355","location":"Renesas/r-car/h3 · revision 13355 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1384","unit":"","sourceId":"chipswiki-31422-r92286","location":"Template:Packages/renesas/fcbga-1384 · revision 92286 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31422-r92286","location":"Template:Packages/renesas/fcbga-1384 · revision 92286 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1384,"unit":"","sourceId":"chipswiki-31422-r92286","location":"Template:Packages/renesas/fcbga-1384 · revision 92286 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31422-r92286","location":"Template:Packages/renesas/fcbga-1384 · revision 92286 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":21,"unit":"mm","sourceId":"chipswiki-31422-r92286","location":"Template:Packages/renesas/fcbga-1384 · revision 92286 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":21,"unit":"mm","sourceId":"chipswiki-31422-r92286","location":"Template:Packages/renesas/fcbga-1384 · revision 92286 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-e76c08dd3c22ca3d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4178-r13355","chipswiki-31422-r92286"],"url":"https://museum.vlsi.kr/objects/cw-e76c08dd3c22ca3d"},{"id":"cw-e77a416ee1cd4a7f","name":"Xeon E7-4820","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-4800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-4820"],"fields":[{"key":"Model name","value":"Xeon E7-4820","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-4820","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615005772AC","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-4800","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5.86,"unit":"GT/s","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3G","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":18,"unit":"MiB","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2.25 MiB","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7701-r25071","location":"Intel/xeon e7/e7-4820 · revision 25071 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e77a416ee1cd4a7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7701-r25071","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-e77a416ee1cd4a7f"},{"id":"cw-e77fd1e2e33330d7","name":"Core m3-6Y30","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"m-6Y","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core m m3-6y30"],"fields":[{"key":"Model name","value":"Core m3-6Y30","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"m3-6Y30","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8066201930521","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EN","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core m3","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"m-6Y","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake Y","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":5,"unit":"°C","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 515","unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":850,"unit":"MHz","sourceId":"chipswiki-4980-r16102","location":"Intel/core m/m3-6y30 · revision 16102 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-e77fd1e2e33330d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4980-r16102"],"url":"https://museum.vlsi.kr/objects/cw-e77fd1e2e33330d7"},{"id":"cw-e7c28ec7184503d1","name":"Pentium B940","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) b940"],"fields":[{"key":"Model name","value":"Pentium B940","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B940","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700847801","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07S","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2011","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 13, 2011","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7791-r25229","location":"Intel/pentium (2009)/b940 · revision 25229 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7c28ec7184503d1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7791-r25229","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-e7c28ec7184503d1"},{"id":"cw-e7dda5ff9a1cd3b7","name":"K6-2/400ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400ack"],"fields":[{"key":"Model name","value":"K6-2/400ACK","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400ACK","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400ACK","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8358-r26053","location":"Amd/k6-2/k6-2-400ack · revision 26053 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e7dda5ff9a1cd3b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8358-r26053"],"url":"https://museum.vlsi.kr/objects/cw-e7dda5ff9a1cd3b7"},{"id":"cw-e7f532db9b0fc117","name":"Xeon W-3225","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3225"],"fields":[{"key":"Model name","value":"Xeon W-3225","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3225","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504152705","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFB","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1708-r5942","location":"Intel/xeon w/w-3225 · revision 5942 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-e7f532db9b0fc117","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1708-r5942"],"url":"https://museum.vlsi.kr/objects/cw-e7f532db9b0fc117"},{"id":"cw-e7fb2bebc9e5f2b1","name":"Logan","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2024,"aliases":["Arm holdings microarchitectures chaberton-elp"],"fields":[{"key":"Architecture name","value":"Logan","unit":"","sourceId":"chipswiki-216-r442","location":"Arm holdings/microarchitectures/chaberton-elp · revision 442 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-31. Not an independent measurement.","entityId":"cw-e7fb2bebc9e5f2b1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton-elp&oldid=442","sourceDate":"2022-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-216-r442","location":"Arm holdings/microarchitectures/chaberton-elp · revision 442 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-31. Not an independent measurement.","entityId":"cw-e7fb2bebc9e5f2b1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton-elp&oldid=442","sourceDate":"2022-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-216-r442","location":"Arm holdings/microarchitectures/chaberton-elp · revision 442 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-31. Not an independent measurement.","entityId":"cw-e7fb2bebc9e5f2b1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton-elp&oldid=442","sourceDate":"2022-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2024,"unit":"","sourceId":"chipswiki-216-r442","location":"Arm holdings/microarchitectures/chaberton-elp · revision 442 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-31. Not an independent measurement.","entityId":"cw-e7fb2bebc9e5f2b1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton-elp&oldid=442","sourceDate":"2022-08-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Hunter-ELP","unit":"","sourceId":"chipswiki-216-r442","location":"Arm holdings/microarchitectures/chaberton-elp · revision 442 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-31. Not an independent measurement.","entityId":"cw-e7fb2bebc9e5f2b1","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton-elp&oldid=442","sourceDate":"2022-08-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-216-r442"],"url":"https://museum.vlsi.kr/objects/cw-e7fb2bebc9e5f2b1"},{"id":"cw-e80090fffb5fbbe6","name":"Core i7-4980HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4980hq"],"fields":[{"key":"Model name","value":"Intel Core i7-4980HQ","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4980HQ","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701956300","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 20, 2014","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 1, 2014","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1ZY","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7863-r25364","location":"Intel/core i7/i7-4980hq · revision 25364 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e80090fffb5fbbe6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7863-r25364","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-e80090fffb5fbbe6"},{"id":"cw-e82ccc9cad150854","name":"CG80286-8","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"CG80286","year":1984,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 cg80286-8"],"fields":[{"key":"Model name","value":"CG80286-8","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CG80286-8","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CG80286","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8 MT/s","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8600-r26798","location":"Amd/am286/cg80286-8 · revision 26798 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e82ccc9cad150854","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8600-r26798"],"url":"https://museum.vlsi.kr/objects/cw-e82ccc9cad150854"},{"id":"cw-e845f1bf0b441cb1","name":"Xeon E3-1505L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1505l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1505L v5","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1505L v5","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202399804","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2E0","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P530","unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7760-r25146","location":"Intel/xeon e3/e3-1505l v5 · revision 25146 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e845f1bf0b441cb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7760-r25146","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-e845f1bf0b441cb1"},{"id":"cw-e85d01f3b9bfacef","name":"Xeon E-2244G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2244g"],"fields":[{"key":"Model name","value":"Xeon E-2244G","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2244G","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404175105","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFAY","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":71,"unit":"W","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2410-r8046","location":"Intel/xeon e/e-2244g · revision 8046 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-e85d01f3b9bfacef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2410-r8046"],"url":"https://museum.vlsi.kr/objects/cw-e85d01f3b9bfacef"},{"id":"cw-e86449332eef5f53","name":"Core i5-2537M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2537m"],"fields":[{"key":"Model name","value":"Core i5-2537M","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2537M","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047107","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR03W","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-7951-r25499","location":"Intel/core i5/i5-2537m · revision 25499 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e86449332eef5f53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7951-r25499","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-e86449332eef5f53"},{"id":"cw-e88e918cfd5bf71b","name":"AMD-K6-2/333BNZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333bnz-66"],"fields":[{"key":"Model name","value":"K6-2/333BNZ-66","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333BNZ-66","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333BNZ-66","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.33,"unit":"MHz","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-360","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8368-r26063","location":"Amd/k6-2/k6-2-333bnz-66 · revision 26063 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e88e918cfd5bf71b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8368-r26063"],"url":"https://museum.vlsi.kr/objects/cw-e88e918cfd5bf71b"},{"id":"cw-e8934b87c61c61d2","name":"Vanilla-5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"University of Michigan","year":null,"process":"16 nm","aliases":["Umich microarchitectures vanilla-5"],"fields":[{"key":"Architecture name","value":"Vanilla-5","unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"University of Michigan","unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":5,"unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":1,"unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"RISC-V","unit":"","sourceId":"chipswiki-1380-r4623","location":"Umich/microarchitectures/vanilla-5 · revision 4623 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-20. Not an independent measurement.","entityId":"cw-e8934b87c61c61d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","sourceDate":"2020-01-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1380-r4623"],"url":"https://museum.vlsi.kr/objects/cw-e8934b87c61c61d2"},{"id":"cw-e8a3fe74ceaab018","name":"CN5745-900 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-900bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5745-900 SSP","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-900 SSP","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-900BG1217-SSP","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8170-r25829","location":"Cavium/octeon plus/cn5745-900bg1217-ssp · revision 25829 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8a3fe74ceaab018","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8170-r25829","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-e8a3fe74ceaab018"},{"id":"cw-e8c8b63a6a5c5745","name":"R-Car L1","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"1st Gen","year":null,"architecture":"Cortex-A9","process":"40 nm","aliases":["Renesas r-car l1"],"fields":[{"key":"Model name","value":"R-Car L1","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"L1","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"1st Gen","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.99,"unit":"GiB/s","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX531","unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":1,"unit":"","sourceId":"chipswiki-7648-r24908","location":"Renesas/r-car/l1 · revision 24908 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-429","unit":"","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":429,"unit":"","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":18,"unit":"mm","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":18,"unit":"mm","sourceId":"chipswiki-31426-r92295","location":"Template:Packages/renesas/fcbga-429 · revision 92295 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8c8b63a6a5c5745","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7648-r24908","chipswiki-31426-r92295"],"url":"https://museum.vlsi.kr/objects/cw-e8c8b63a6a5c5745"},{"id":"cw-e8ff00a15f5f0876","name":"Core i5-6360U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6360u"],"fields":[{"key":"Model name","value":"Core i5-6360U","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6360U","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202499208","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JM","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 540","unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7924-r25463","location":"Intel/core i5/i5-6360u · revision 25463 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-e8ff00a15f5f0876","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7924-r25463","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-e8ff00a15f5f0876"},{"id":"cw-e92a3b04ffe7b50c","name":"Core i5-6440HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6440hq"],"fields":[{"key":"Model name","value":"Core i5-6440HQ","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6440HQ","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202194729","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FS","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 27, 2015","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-3975-r12662","location":"Intel/core i5/i5-6440hq · revision 12662 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-e92a3b04ffe7b50c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3975-r12662","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-e92a3b04ffe7b50c"},{"id":"cw-e9528c94e39959ad","name":"Am186EM–25KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–25ki\\w"],"fields":[{"key":"Model name","value":"Am186EM–25KI\\W","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–25KI\\W","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–25KI\\W","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14654-r44715","location":"Amd/am186ex/am186em–25ki\\w · revision 44715 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e9528c94e39959ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14654-r44715"],"url":"https://museum.vlsi.kr/objects/cw-e9528c94e39959ad"},{"id":"cw-e97a86feb9611ce7","name":"Gracemont","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2021,"process":"10 nm","aliases":["Intel microarchitectures gracemont"],"fields":[{"key":"Architecture name","value":"Gracemont","unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2021,"unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Tremont","unit":"","sourceId":"chipswiki-633-r1521","location":"Intel/microarchitectures/gracemont · revision 1521 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-21. Not an independent measurement.","entityId":"cw-e97a86feb9611ce7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","sourceDate":"2021-08-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-633-r1521"],"url":"https://museum.vlsi.kr/objects/cw-e97a86feb9611ce7"},{"id":"cw-e97ee614e1cfa22f","name":"Xeon Gold 6226R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6226r"],"fields":[{"key":"Model name","value":"Xeon Gold 6226R","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6226R","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1263-r4097","location":"Intel/xeon gold/6226r · revision 4097 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-e97ee614e1cfa22f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1263-r4097"],"url":"https://museum.vlsi.kr/objects/cw-e97ee614e1cfa22f"},{"id":"cw-e983d7fcba03fded","name":"Am186ESLV–20KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1997,"architecture":"80186","aliases":["Amd am186ex am186eslv–20kc\\w"],"fields":[{"key":"Model name","value":"Am186ESLV–20KC\\W","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ESLV–20KC\\W","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ESLV–20KC\\W","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14631-r44692","location":"Amd/am186ex/am186eslv–20kc\\w · revision 44692 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-e983d7fcba03fded","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14631-r44692"],"url":"https://museum.vlsi.kr/objects/cw-e983d7fcba03fded"},{"id":"cw-e9b3f7de0be06811","name":"Modified Pentium M","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2006,"process":"65 nm","aliases":["Intel microarchitectures modified pentium m"],"fields":[{"key":"Architecture name","value":"Modified Pentium M","unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2006,"unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-16","unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Pentium M","unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Core","unit":"","sourceId":"chipswiki-8774-r27271","location":"Intel/microarchitectures/modified pentium m · revision 27271 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-e9b3f7de0be06811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8774-r27271"],"url":"https://museum.vlsi.kr/objects/cw-e9b3f7de0be06811"},{"id":"cw-ea0fa0ee0ad6279e","name":"MSM6575","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2006,"architecture":"ARM9","process":"65 nm","aliases":["Qualcomm msm6xxx msm6575"],"fields":[{"key":"Model name","value":"Qualcomm MSM6575","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6575","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2005,"unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2006,"unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":270,"unit":"MHz","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7657-r24918","location":"Qualcomm/msm6xxx/msm6575 · revision 24918 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea0fa0ee0ad6279e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7657-r24918"],"url":"https://museum.vlsi.kr/objects/cw-ea0fa0ee0ad6279e"},{"id":"cw-ea2638b42b81b691","name":"Alchemy Au1250-700MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":null,"architecture":"Au1","aliases":["Alchemy au1250-700mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1250-700MGD","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1250-700MGD","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1250-700MGD","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.867 GB/s","unit":"","sourceId":"chipswiki-440-r921","location":"Alchemy/au1250-700mgd · revision 921 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-ea2638b42b81b691","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-440-r921"],"url":"https://museum.vlsi.kr/objects/cw-ea2638b42b81b691"},{"id":"cw-ea4188d958a841e5","name":"CN3110-500 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-500bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3110-500 EXP","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-500 EXP","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-500BG868-EXP","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8260-r25920","location":"Cavium/octeon/cn3110-500bg868-exp · revision 25920 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea4188d958a841e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8260-r25920","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-ea4188d958a841e5"},{"id":"cw-ea640190f9832df1","name":"MSM6275","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2004,"architecture":"ARM9","process":"90 nm","aliases":["Qualcomm msm6xxx msm6275"],"fields":[{"key":"Model name","value":"Qualcomm MSM6275","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6275","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2003","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December, 2004","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":225,"unit":"MHz","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7660-r24923","location":"Qualcomm/msm6xxx/msm6275 · revision 24923 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea640190f9832df1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7660-r24923"],"url":"https://museum.vlsi.kr/objects/cw-ea640190f9832df1"},{"id":"cw-ea71611bdb9fcb66","name":"Xeon Gold 6212U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6212u"],"fields":[{"key":"Model name","value":"Xeon Gold 6212U","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6212U","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504198002","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9A","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-594-r1388","location":"Intel/xeon gold/6212u · revision 1388 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-ea71611bdb9fcb66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-594-r1388"],"url":"https://museum.vlsi.kr/objects/cw-ea71611bdb9fcb66"},{"id":"cw-ea730aa608dcf562","name":"Am486SE-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SE","year":null,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486se-33"],"fields":[{"key":"Model name","value":"Am486SE-33","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486SE-33","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486SE-33","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SE","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8540-r26736","location":"Amd/am486/am486se-33 · revision 26736 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea730aa608dcf562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8540-r26736"],"url":"https://museum.vlsi.kr/objects/cw-ea730aa608dcf562"},{"id":"cw-ea918a15fda8199f","name":"Am486SXLV-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SXLV","year":null,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486sxlv-33"],"fields":[{"key":"Model name","value":"Am486SXLV-33","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486SXLV-33","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SXLV-33","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SXLV","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SXLV","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8535-r26731","location":"Amd/am486/am486sxlv-33 · revision 26731 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ea918a15fda8199f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8535-r26731"],"url":"https://museum.vlsi.kr/objects/cw-ea918a15fda8199f"},{"id":"cw-eab4a4c274bbb274","name":"Ryzen Threadripper PRO 5965WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5900","year":2022,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen threadripper pro 5965wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 5965WX","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5965WX","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000446","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 8, 2022","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5900,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chagall","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24 × 512 KiB","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-393-r839","location":"Amd/ryzen threadripper/pro 5965wx · revision 839 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-eab4a4c274bbb274","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-393-r839","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-eab4a4c274bbb274"},{"id":"cw-ead3f4b985e8026c","name":"PEZY-SC4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"PEZY","year":2020,"process":"5 nm","aliases":["Pezy pezy-scx pezy-sc4"],"fields":[{"key":"Model name","value":"PEZY-SC4","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"PEZY","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PEZY-SC4","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Supercomputer","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2016,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2020,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PEZY-SCx","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":740,"unit":"mm²","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16384,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":131072,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.55,"unit":"V","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR5-4000","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":4,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":4,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":119.2,"unit":"GiB/s","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":8,"unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":"22.35 TiB/s","unit":"","sourceId":"chipswiki-6357-r19743","location":"Pezy/pezy-scx/pezy-sc4 · revision 19743 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2018-04-21. Not an independent measurement.","entityId":"cw-ead3f4b985e8026c","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","sourceDate":"2018-04-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6357-r19743"],"url":"https://museum.vlsi.kr/objects/cw-ead3f4b985e8026c"},{"id":"cw-eaf0477f6623925e","name":"AMD-K6-2/333ANZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333anz-66"],"fields":[{"key":"Model name","value":"K6-2/333ANZ-66","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333ANZ-66","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333ANZ-66","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.33,"unit":"MHz","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8370-r26065","location":"Amd/k6-2/k6-2-333anz-66 · revision 26065 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eaf0477f6623925e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8370-r26065"],"url":"https://museum.vlsi.kr/objects/cw-eaf0477f6623925e"},{"id":"cw-eaf2c40c34f6aa5c","name":"Xeon D-1531","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1531"],"fields":[{"key":"Model name","value":"Xeon D-1531","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1531","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402568900","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DG","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3732-r11437","location":"Intel/xeon d/d-1531 · revision 11437 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-eaf2c40c34f6aa5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3732-r11437"],"url":"https://museum.vlsi.kr/objects/cw-eaf2c40c34f6aa5c"},{"id":"cw-eb28b9c5c9389074","name":"Atom x7-Z8750","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8700","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x7 z8750"],"fields":[{"key":"Model name","value":"Atom x7-Z8750","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x7-Z8750","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715827","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2015","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2015","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x7","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8700,"unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2560,"unit":"MHz","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KG","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1380","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8039-r25671","location":"Intel/atom x7/z8750 · revision 25671 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb28b9c5c9389074","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8039-r25671"],"url":"https://museum.vlsi.kr/objects/cw-eb28b9c5c9389074"},{"id":"cw-eb60cf187b748495","name":"Xeon E5-2699R v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2699r v4"],"fields":[{"key":"Model name","value":"Xeon E5-2699R v4","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2699R v4","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066003216500","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 25, 2016","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 25, 2016","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR31X","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":145,"unit":"W","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x256 KiB","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":55,"unit":"MiB","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x2.5 MiB","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7717-r25089","location":"Intel/xeon e5/e5-2699r v4 · revision 25089 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb60cf187b748495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7717-r25089"],"url":"https://museum.vlsi.kr/objects/cw-eb60cf187b748495"},{"id":"cw-eb85474c5ee6485c","name":"CN3830-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3830-600 EXP","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-600 EXP","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-600BG1521-EXP","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8223-r25882","location":"Cavium/octeon/cn3830-600bg1521-exp · revision 25882 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-eb85474c5ee6485c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8223-r25882","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-eb85474c5ee6485c"},{"id":"cw-ec4b53923979edb5","name":"Celeron P4505","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P4000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel celeron p4505"],"fields":[{"key":"Model name","value":"Intel Celeron P4505","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P4505","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004545AF","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2010","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2010","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P4000","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBQB","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":667,"unit":"MHz","sourceId":"chipswiki-8025-r25607","location":"Intel/celeron/p4505 · revision 25607 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec4b53923979edb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8025-r25607","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-ec4b53923979edb5"},{"id":"cw-ec71db0d5c9f8fee","name":"AMD-K6-2/300ANZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300anz"],"fields":[{"key":"Model name","value":"K6-2/300ANZ","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300ANZ","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300ANZ","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8379-r26074","location":"Amd/k6-2/k6-2-300anz · revision 26074 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec71db0d5c9f8fee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8379-r26074"],"url":"https://museum.vlsi.kr/objects/cw-ec71db0d5c9f8fee"},{"id":"cw-ec86c22c424393e6","name":"Atom x5-Z8550","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z8000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x5 x5-z8550"],"fields":[{"key":"Model name","value":"Intel Atom x5-Z8550","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-Z8550","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715843","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715844","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z8000","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1440,"unit":"MHz","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KH","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KJ","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1380","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8042-r25674","location":"Intel/atom x5/x5-z8550 · revision 25674 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ec86c22c424393e6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8042-r25674"],"url":"https://museum.vlsi.kr/objects/cw-ec86c22c424393e6"},{"id":"cw-eca7ddb30da0dcb8","name":"MN-Core","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Preferred Networks","year":2020,"process":"12 nm","aliases":["Preferred networks microarchitectures mn-core"],"fields":[{"key":"Architecture name","value":"MN-Core","unit":"","sourceId":"chipswiki-1603-r5376","location":"Preferred networks/microarchitectures/mn-core · revision 5376 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-27. Not an independent measurement.","entityId":"cw-eca7ddb30da0dcb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Preferred%20networks%2Fmicroarchitectures%2Fmn-core&oldid=5376","sourceDate":"2019-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Preferred Networks","unit":"","sourceId":"chipswiki-1603-r5376","location":"Preferred networks/microarchitectures/mn-core · revision 5376 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-27. Not an independent measurement.","entityId":"cw-eca7ddb30da0dcb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Preferred%20networks%2Fmicroarchitectures%2Fmn-core&oldid=5376","sourceDate":"2019-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1603-r5376","location":"Preferred networks/microarchitectures/mn-core · revision 5376 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-27. Not an independent measurement.","entityId":"cw-eca7ddb30da0dcb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Preferred%20networks%2Fmicroarchitectures%2Fmn-core&oldid=5376","sourceDate":"2019-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2020,"unit":"","sourceId":"chipswiki-1603-r5376","location":"Preferred networks/microarchitectures/mn-core · revision 5376 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-27. Not an independent measurement.","entityId":"cw-eca7ddb30da0dcb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Preferred%20networks%2Fmicroarchitectures%2Fmn-core&oldid=5376","sourceDate":"2019-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1603-r5376","location":"Preferred networks/microarchitectures/mn-core · revision 5376 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-27. Not an independent measurement.","entityId":"cw-eca7ddb30da0dcb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Preferred%20networks%2Fmicroarchitectures%2Fmn-core&oldid=5376","sourceDate":"2019-11-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1603-r5376"],"url":"https://museum.vlsi.kr/objects/cw-eca7ddb30da0dcb8"},{"id":"cw-ecd029036bb1e732","name":"Xeon E3-1535M V5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1535m v5"],"fields":[{"key":"Model name","value":"Xeon E3-1535M V5","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1535M V5","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202191412","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FM","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"f","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P530","unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7758-r25141","location":"Intel/xeon e3/e3-1535m v5 · revision 25141 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd029036bb1e732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7758-r25141","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ecd029036bb1e732"},{"id":"cw-ecd161adf4e67a62","name":"AMD-K6-2/266AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-266amz"],"fields":[{"key":"Model name","value":"K6-2/266AMZ","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/266AMZ","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/266AMZ","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8385-r26080","location":"Amd/k6-2/k6-2-266amz · revision 26080 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ecd161adf4e67a62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8385-r26080"],"url":"https://museum.vlsi.kr/objects/cw-ecd161adf4e67a62"},{"id":"cw-ece829d34ed9cd2f","name":"ARM10","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":1998,"aliases":["Arm holdings microarchitectures arm10"],"fields":[{"key":"Architecture name","value":"ARM10","unit":"","sourceId":"chipswiki-4167-r13321","location":"Arm holdings/microarchitectures/arm10 · revision 13321 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-30. Not an independent measurement.","entityId":"cw-ece829d34ed9cd2f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","sourceDate":"2018-12-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4167-r13321","location":"Arm holdings/microarchitectures/arm10 · revision 13321 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-30. Not an independent measurement.","entityId":"cw-ece829d34ed9cd2f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","sourceDate":"2018-12-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4167-r13321","location":"Arm holdings/microarchitectures/arm10 · revision 13321 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-30. Not an independent measurement.","entityId":"cw-ece829d34ed9cd2f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","sourceDate":"2018-12-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 15, 1998","unit":"","sourceId":"chipswiki-4167-r13321","location":"Arm holdings/microarchitectures/arm10 · revision 13321 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-30. Not an independent measurement.","entityId":"cw-ece829d34ed9cd2f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","sourceDate":"2018-12-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM9","unit":"","sourceId":"chipswiki-4167-r13321","location":"Arm holdings/microarchitectures/arm10 · revision 13321 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-30. Not an independent measurement.","entityId":"cw-ece829d34ed9cd2f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","sourceDate":"2018-12-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM11","unit":"","sourceId":"chipswiki-4167-r13321","location":"Arm holdings/microarchitectures/arm10 · revision 13321 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-30. Not an independent measurement.","entityId":"cw-ece829d34ed9cd2f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","sourceDate":"2018-12-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4167-r13321"],"url":"https://museum.vlsi.kr/objects/cw-ece829d34ed9cd2f"},{"id":"cw-ed04ec106fb15e56","name":"AMD-K6-233AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-233afr"],"fields":[{"key":"Model name","value":"AMD-K6-233AFR","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-233AFR","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-233AFR","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8295-r25983","location":"Amd/k6/amd-k6-233afr · revision 25983 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed04ec106fb15e56","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8295-r25983"],"url":"https://museum.vlsi.kr/objects/cw-ed04ec106fb15e56"},{"id":"cw-ed3993145095a58f","name":"Am186ES–33VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–33vc\\w"],"fields":[{"key":"Model name","value":"Am186ES–33VC\\W","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–33VC\\W","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–3VC\\W","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14620-r44681","location":"Amd/am186ex/am186es–33vc\\w · revision 44681 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-ed3993145095a58f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14620-r44681"],"url":"https://museum.vlsi.kr/objects/cw-ed3993145095a58f"},{"id":"cw-ed5e2819461f10c3","name":"Alchemy Au1100-500MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-500mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1100-500MBC","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-500MBC","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBCBA","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBCBC","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBCBD","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBCBE","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBCBF","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BA","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BC","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BD","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BE","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BF","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.22,"unit":"V","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.500 GB/s","unit":"","sourceId":"chipswiki-469-r950","location":"Alchemy/au1100-500mbc · revision 950 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-ed5e2819461f10c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-469-r950"],"url":"https://museum.vlsi.kr/objects/cw-ed5e2819461f10c3"},{"id":"cw-ed86094bafaf9e6c","name":"Core i3-6100E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6100e"],"fields":[{"key":"Model name","value":"Core i3-6100E","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6100E","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066201939604","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DV","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7986-r25564","location":"Intel/core i3/i3-6100e · revision 25564 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed86094bafaf9e6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7986-r25564","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ed86094bafaf9e6c"},{"id":"cw-ed8f3a33b8d171e9","name":"MD8086-2B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 md8086-2b"],"fields":[{"key":"Model name","value":"AMD MD8086-2B","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MD8086-2B","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MD8086-2B","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M8086","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8500-r26693","location":"Amd/am8086/md8086-2b · revision 26693 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ed8f3a33b8d171e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8500-r26693"],"url":"https://museum.vlsi.kr/objects/cw-ed8f3a33b8d171e9"},{"id":"cw-eda5c49d7e7f8ee9","name":"Xeon E3-1501M v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1501m v6"],"fields":[{"key":"Model name","value":"Xeon E3-1501M v6","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1501M v6","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3FO","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P630","unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6411-r20010","location":"Intel/xeon e3/e3-1501m v6 · revision 20010 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-eda5c49d7e7f8ee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6411-r20010","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-eda5c49d7e7f8ee9"},{"id":"cw-edcc3b84b85a4809","name":"Ryzen 5 PRO 3500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 pro 3500u"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 3500U","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3500U","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM350BC4T4MFG","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2185-r7374","location":"Amd/ryzen 5/pro 3500u · revision 7374 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-edcc3b84b85a4809","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2185-r7374"],"url":"https://museum.vlsi.kr/objects/cw-edcc3b84b85a4809"},{"id":"cw-edd6349f89884b76","name":"Gen2","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2002,"aliases":["Intel microarchitectures gen2"],"fields":[{"key":"Architecture name","value":"Gen2","unit":"","sourceId":"chipswiki-15960-r52687","location":"Intel/microarchitectures/gen2 · revision 52687 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-edd6349f89884b76","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15960-r52687","location":"Intel/microarchitectures/gen2 · revision 52687 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-edd6349f89884b76","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15960-r52687","location":"Intel/microarchitectures/gen2 · revision 52687 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-edd6349f89884b76","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2002,"unit":"","sourceId":"chipswiki-15960-r52687","location":"Intel/microarchitectures/gen2 · revision 52687 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-edd6349f89884b76","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen1","unit":"","sourceId":"chipswiki-15960-r52687","location":"Intel/microarchitectures/gen2 · revision 52687 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-edd6349f89884b76","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen3","unit":"","sourceId":"chipswiki-15960-r52687","location":"Intel/microarchitectures/gen2 · revision 52687 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-edd6349f89884b76","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15960-r52687"],"url":"https://museum.vlsi.kr/objects/cw-edd6349f89884b76"},{"id":"cw-edfa54d0def0eacc","name":"Alchemy Au1200-500MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-500mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1200-500MGD","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-500MGD","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-500MGD","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2005","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1600 mW","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"2 GB/s","unit":"","sourceId":"chipswiki-451-r932","location":"Alchemy/au1200-500mgd · revision 932 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-edfa54d0def0eacc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-451-r932"],"url":"https://museum.vlsi.kr/objects/cw-edfa54d0def0eacc"},{"id":"cw-ee017689a167e8ea","name":"K6-2/475AFX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-475afx"],"fields":[{"key":"Model name","value":"K6-2/475AFX","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/475AFX","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/475AFX","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 15, 1999","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 1999","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":475,"unit":"MHz","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8340-r26035","location":"Amd/k6-2/k6-2-475afx · revision 26035 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee017689a167e8ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8340-r26035"],"url":"https://museum.vlsi.kr/objects/cw-ee017689a167e8ea"},{"id":"cw-ee1861b210a5e687","name":"Core i5-8250U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-8250u"],"fields":[{"key":"Model name","value":"Core i5-8250U","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8250U","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067703282221","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LA","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 21, 2017","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 21, 2017","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake R","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":123,"unit":"mm²","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-783-r1922","location":"Intel/core i5/i5-8250u · revision 1922 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-ee1861b210a5e687","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-783-r1922","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-ee1861b210a5e687"},{"id":"cw-ee2f47327a9896d8","name":"Duron 850 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm0850avs1bm"],"fields":[{"key":"Model name","value":"Duron 850","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 850","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0850AVS1BM","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2001,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2001,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":850,"unit":"MHz","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8414-r26122","location":"Amd/duron/dhm0850avs1bm · revision 26122 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ee2f47327a9896d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8414-r26122"],"url":"https://museum.vlsi.kr/objects/cw-ee2f47327a9896d8"},{"id":"cw-ee818d733d722ab1","name":"Xeon Gold 6152","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6152"],"fields":[{"key":"Model name","value":"Xeon Gold 6152","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6152,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736152","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303406000","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B4","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x1 MiB","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30.25,"unit":"MiB","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x1.375 MiB","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1494-r4946","location":"Intel/xeon gold/6152 · revision 4946 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ee818d733d722ab1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1494-r4946"],"url":"https://museum.vlsi.kr/objects/cw-ee818d733d722ab1"},{"id":"cw-ee9166b22660c2c3","name":"Core i7-4870HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4870hq"],"fields":[{"key":"Model name","value":"Intel Core i7-4870HQ","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4870HQ","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701956200","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1ZX","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 20, 2014","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 20, 2014","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7563-r24569","location":"Intel/core i7/i7-4870hq · revision 24569 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","sourceDate":"2017-12-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-26. Not an independent measurement.","entityId":"cw-ee9166b22660c2c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7563-r24569","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-ee9166b22660c2c3"},{"id":"cw-ef00d780f05676d9","name":"Core i3-7340","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7000","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7340"],"fields":[{"key":"Model name","value":"Core i3-7340","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7340","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35A","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7000","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4200,"unit":"MHz","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7963-r25533","location":"Intel/core i3/i3-7340 · revision 25533 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef00d780f05676d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7963-r25533"],"url":"https://museum.vlsi.kr/objects/cw-ef00d780f05676d9"},{"id":"cw-ef0449a69d543d0b","name":"Xeon W-2145","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2145"],"fields":[{"key":"Model name","value":"Xeon W-2145","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2145","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303533601","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LQ","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2529-r8685","location":"Intel/xeon w/w-2145 · revision 8685 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-ef0449a69d543d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2529-r8685"],"url":"https://museum.vlsi.kr/objects/cw-ef0449a69d543d0b"},{"id":"cw-ef2e1f1ae72153ea","name":"Core i7-2620M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2620m"],"fields":[{"key":"Model name","value":"Core i7-2620M","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2620M","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700838809","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700839009","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR03F","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR041","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7898-r25402","location":"Intel/core i7/i7-2620m · revision 25402 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef2e1f1ae72153ea","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7898-r25402","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-ef2e1f1ae72153ea"},{"id":"cw-ef3e9abdbe20d6a0","name":"Ryzen Embedded R1305G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"R1000","year":2020,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded r1305g"],"fields":[{"key":"Model name","value":"Ryzen Embedded R1305G","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"R1305G","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1305C9T2OFG","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 25, 2020","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 25, 2020","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"R1000","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":8,"unit":"W","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 64 KiB","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-920-r2542","location":"Amd/ryzen embedded/r1305g · revision 2542 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-ef3e9abdbe20d6a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-920-r2542"],"url":"https://museum.vlsi.kr/objects/cw-ef3e9abdbe20d6a0"},{"id":"cw-ef4c73d802ab5024","name":"Core i5-2477M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2477m"],"fields":[{"key":"Model name","value":"Core i5-2477M","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2477M","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047503","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047605","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0BG","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CU","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0D7","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-1101-r3263","location":"Intel/core i5/i5-2477m · revision 3263 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-ef4c73d802ab5024","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1101-r3263","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-ef4c73d802ab5024"},{"id":"cw-ef600270677f021c","name":"Xeon Platinum 8163","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8163"],"fields":[{"key":"Model name","value":"Xeon Platinum 8163","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8163,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2017,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2558-r8824","location":"Intel/xeon platinum/8163 · revision 8824 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-ef600270677f021c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2558-r8824"],"url":"https://museum.vlsi.kr/objects/cw-ef600270677f021c"},{"id":"cw-ef74e96e8eda7ad3","name":"Core i3-6167U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6167u"],"fields":[{"key":"Model name","value":"Core i3-6167U","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6167U","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202498901","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JF","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 550","unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7980-r25557","location":"Intel/core i3/i3-6167u · revision 25557 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ef74e96e8eda7ad3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7980-r25557","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-ef74e96e8eda7ad3"},{"id":"cw-ef898ce44e0d20b6","name":"Xeon Silver 4209T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4209t"],"fields":[{"key":"Model name","value":"Xeon Silver 4209T","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4209T","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069503956900","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBQ","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R1","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":70,"unit":"W","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1448-r4889","location":"Intel/xeon silver/4209t · revision 4889 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-ef898ce44e0d20b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1448-r4889"],"url":"https://museum.vlsi.kr/objects/cw-ef898ce44e0d20b6"},{"id":"cw-ef96e6b5b65ab3ec","name":"Core i5-7440EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7400","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7440eq"],"fields":[{"key":"Model name","value":"Core i5-7440EQ","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7440EQ","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8067702998810","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34T","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7400","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-6419-r20019","reason":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6419-r20019","location":"Intel/core i5/i5-7440eq · revision 20019 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-ef96e6b5b65ab3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6419-r20019","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-ef96e6b5b65ab3ec"},{"id":"cw-efa38ed374e70c9a","name":"Xeon Gold 5118","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5118"],"fields":[{"key":"Model name","value":"Xeon Gold 5118","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5118,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303536100","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GF","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1530-r4985","location":"Intel/xeon gold/5118 · revision 4985 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-efa38ed374e70c9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1530-r4985"],"url":"https://museum.vlsi.kr/objects/cw-efa38ed374e70c9a"},{"id":"cw-efaca8c0a64eb56e","name":"Am186ED–40KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–40kc\\w"],"fields":[{"key":"Model name","value":"Am186ED–40KC\\W","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–40KC\\W","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–40KC\\W","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14664-r44725","location":"Amd/am186ex/am186ed–40kc\\w · revision 44725 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-efaca8c0a64eb56e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14664-r44725"],"url":"https://museum.vlsi.kr/objects/cw-efaca8c0a64eb56e"},{"id":"cw-efc2fc6b1cc34039","name":"Ryzen 3 4300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 4300u"],"fields":[{"key":"Model name","value":"Ryzen 3 4300U","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4300U","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000085","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 5","unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":5,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-689-r1683","location":"Amd/ryzen 3/4300u · revision 1683 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efc2fc6b1cc34039","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-689-r1683"],"url":"https://museum.vlsi.kr/objects/cw-efc2fc6b1cc34039"},{"id":"cw-efce7f6faa72d1cd","name":"Ryzen 7 4800H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4800h"],"fields":[{"key":"Model name","value":"Ryzen 7 4800H","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4800H","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000098","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-685-r1679","location":"Amd/ryzen 7/4800h · revision 1679 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-efce7f6faa72d1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-685-r1679"],"url":"https://museum.vlsi.kr/objects/cw-efce7f6faa72d1cd"},{"id":"cw-efeedbe6d8f2f3fd","name":"AMD-K6-200AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-200afr"],"fields":[{"key":"Model name","value":"AMD-K6-200AFR","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-200AFR","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-200AFR","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":199.99,"unit":"MHz","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8297-r25986","location":"Amd/k6/amd-k6-200afr · revision 25986 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-efeedbe6d8f2f3fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8297-r25986"],"url":"https://museum.vlsi.kr/objects/cw-efeedbe6d8f2f3fd"},{"id":"cw-f005391161f264f2","name":"Celeron G3930T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G3900","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron g3930t"],"fields":[{"key":"Model name","value":"Celeron G3930T","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3930T","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067703016211","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35V","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G3900","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6431-r20111","location":"Intel/celeron/g3930t · revision 20111 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f005391161f264f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6431-r20111"],"url":"https://museum.vlsi.kr/objects/cw-f005391161f264f2"},{"id":"cw-f0906750afbde0e8","name":"Xeon E5-4669 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4669 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4669 v4","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4669 v4","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002064800","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SG","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x256 KiB","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":55,"unit":"MiB","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x2.5 MiB","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7708-r25079","location":"Intel/xeon e5/e5-4669 v4 · revision 25079 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f0906750afbde0e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7708-r25079"],"url":"https://museum.vlsi.kr/objects/cw-f0906750afbde0e8"},{"id":"cw-f0b5036fc151ba50","name":"Core i3-7310U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7000","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7310u"],"fields":[{"key":"Model name","value":"Intel Core i3-7310U","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7310U","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 4, 2017","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7000","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","alternatives":[{"value":"64 GiB","sourceId":"chipswiki-6363-r19769","reason":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6363-r19769","location":"Intel/core i3/i3-7310u · revision 19769 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","sourceDate":"2018-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-19. Not an independent measurement.","entityId":"cw-f0b5036fc151ba50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6363-r19769","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-f0b5036fc151ba50"},{"id":"cw-f0bf433d558ecd12","name":"EPYC 7702P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7702p"],"fields":[{"key":"Model name","value":"EPYC 7702P","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7702P","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000047","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000047WOF","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64x512 KiB","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x16 MiB","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-868-r2252","location":"Amd/epyc/7702p · revision 2252 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0bf433d558ecd12","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-868-r2252"],"url":"https://museum.vlsi.kr/objects/cw-f0bf433d558ecd12"},{"id":"cw-f0f31afe2104fbf5","name":"EPYC 7402","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7402"],"fields":[{"key":"Model name","value":"EPYC 7402","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7402,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000046","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000046WOF","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-859-r2239","location":"Amd/epyc/7402 · revision 2239 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-f0f31afe2104fbf5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-859-r2239"],"url":"https://museum.vlsi.kr/objects/cw-f0f31afe2104fbf5"},{"id":"cw-f0f84530d3008300","name":"Ryzen 9 PRO 3900","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 9 pro 3900"],"fields":[{"key":"Model name","value":"Ryzen 9 PRO 3900","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3900","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000072","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Matisse","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x512 KiB","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x16 MiB","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-1549-r5056","location":"Amd/ryzen 9/pro 3900 · revision 5056 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-f0f84530d3008300","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1549-r5056","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-f0f84530d3008300"},{"id":"cw-f0fb38e92e5b4cce","name":"Chaberton","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2024,"process":"7 nm","aliases":["Arm holdings microarchitectures chaberton"],"fields":[{"key":"Architecture name","value":"Chaberton","unit":"","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2024,"unit":"","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Hunter","unit":"","sourceId":"chipswiki-304-r618","location":"Arm holdings/microarchitectures/chaberton · revision 618 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-f0fb38e92e5b4cce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-304-r618"],"url":"https://museum.vlsi.kr/objects/cw-f0fb38e92e5b4cce"},{"id":"cw-f10ae29176f08fe1","name":"Pentium P6100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P6000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel pentium (2009) p6100"],"fields":[{"key":"Model name","value":"Intel Pentium P6100","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P6100","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004125AL","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P6000","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUR","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3 12800s","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":667,"unit":"MHz","sourceId":"chipswiki-909-r2446","location":"Intel/pentium (2009)/p6100 · revision 2446 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","sourceDate":"2020-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-11-13. Not an independent measurement.","entityId":"cw-f10ae29176f08fe1","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-909-r2446","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-f10ae29176f08fe1"},{"id":"cw-f13006a6b81639ca","name":"KaisHeng KH-26800","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KH-20000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaisheng kh-26800"],"fields":[{"key":"Model name","value":"KaisHeng KH-26800","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KH-26800","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KH-26800","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaisHeng","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KH-20000","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7265-r23218","location":"Zhaoxin/kaisheng/kh-26800 · revision 23218 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-f13006a6b81639ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7265-r23218"],"url":"https://museum.vlsi.kr/objects/cw-f13006a6b81639ca"},{"id":"cw-f16730d0e111226e","name":"CN5840-900 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-900bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5840-900 NSP","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-900 NSP","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-900BG1521-NSP","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8139-r25798","location":"Cavium/octeon plus/cn5840-900bg1521-nsp · revision 25798 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f16730d0e111226e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8139-r25798","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-f16730d0e111226e"},{"id":"cw-f177e19d0535a93c","name":"Cortex-A78","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2020,"process":"10 nm","aliases":["Arm holdings microarchitectures cortex-a78"],"fields":[{"key":"Architecture name","value":"Cortex-A78","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 26, 2020","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":13,"unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"128-512 KiB","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"0-4 MiB","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A77","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Matterhorn","unit":"","sourceId":"chipswiki-427-r899","location":"Arm holdings/microarchitectures/cortex-a78 · revision 899 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-31. Not an independent measurement.","entityId":"cw-f177e19d0535a93c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","sourceDate":"2022-03-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-427-r899"],"url":"https://museum.vlsi.kr/objects/cw-f177e19d0535a93c"},{"id":"cw-f177fb788c6de17f","name":"Core i3-8121U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Cannon Lake","process":"10 nm","aliases":["Intel core i3 i3-8121u"],"fields":[{"key":"Model name","value":"Core i3-8121U","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8121U","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCVC","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 15, 2018","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 15, 2018","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cannon Lake","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cannon Lake U","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":102,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-2400","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-2400","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5568-r18075","location":"Intel/core i3/i3-8121u · revision 18075 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-22. Not an independent measurement.","entityId":"cw-f177fb788c6de17f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","sourceDate":"2018-06-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5568-r18075"],"url":"https://museum.vlsi.kr/objects/cw-f177fb788c6de17f"},{"id":"cw-f1bc75131a5e66f3","name":"AMD-K6-III/450ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-450ack"],"fields":[{"key":"Model name","value":"AMD-K6-III/450ACK","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/450ACK","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/450ACK","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4499-r14625","location":"Amd/k6-iii-p/amd-k6-iii-450ack · revision 14625 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-27. Not an independent measurement.","entityId":"cw-f1bc75131a5e66f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","sourceDate":"2018-10-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4499-r14625"],"url":"https://museum.vlsi.kr/objects/cw-f1bc75131a5e66f3"},{"id":"cw-f1fbdd7e1074f379","name":"Vega","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2017,"process":"12 nm","aliases":["Amd microarchitectures vega"],"fields":[{"key":"Architecture name","value":"Vega","unit":"","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2017,"unit":"","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Polaris","unit":"","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Navi","unit":"","sourceId":"chipswiki-1080-r3147","location":"Amd/microarchitectures/vega · revision 3147 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-16. Not an independent measurement.","entityId":"cw-f1fbdd7e1074f379","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","sourceDate":"2020-06-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1080-r3147"],"url":"https://museum.vlsi.kr/objects/cw-f1fbdd7e1074f379"},{"id":"cw-f2643837881e7845","name":"Core i5-8600T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8600t"],"fields":[{"key":"Model name","value":"Core i5-8600T","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8600T","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403358708","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3X3","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-4964-r16058","location":"Intel/core i5/i5-8600t · revision 16058 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-f2643837881e7845","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4964-r16058","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-f2643837881e7845"},{"id":"cw-f26801a6dbfc0b39","name":"Am186CH-40KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CH","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186ch-40kc\\w"],"fields":[{"key":"Model name","value":"Am186CH-40KC\\W","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CH-40KC\\W","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CH-40KC\\W","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CH","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14684-r44745","location":"Amd/am186cx/am186ch-40kc\\w · revision 44745 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f26801a6dbfc0b39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14684-r44745"],"url":"https://museum.vlsi.kr/objects/cw-f26801a6dbfc0b39"},{"id":"cw-f2755c7f2ded1008","name":"Xeon Platinum 8180M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8180m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8180M","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8180M","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303192101","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37T","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2555-r8811","location":"Intel/xeon platinum/8180m · revision 8811 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-f2755c7f2ded1008","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2555-r8811"],"url":"https://museum.vlsi.kr/objects/cw-f2755c7f2ded1008"},{"id":"cw-f2b680b40cee2bab","name":"CN5745-600 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-600bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5745-600 SSP","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-600 SSP","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-600BG1217-SSP","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8174-r25833","location":"Cavium/octeon plus/cn5745-600bg1217-ssp · revision 25833 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2b680b40cee2bab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8174-r25833","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-f2b680b40cee2bab"},{"id":"cw-f2d03f149c5b44d3","name":"Core i3-7300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7300"],"fields":[{"key":"Model name","value":"Core i3-7300","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7300","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677I37300","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677I37300","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR359","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7300","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-796-r2001","location":"Intel/core i3/i3-7300 · revision 2001 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-28. Not an independent measurement.","entityId":"cw-f2d03f149c5b44d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","sourceDate":"2021-03-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-796-r2001"],"url":"https://museum.vlsi.kr/objects/cw-f2d03f149c5b44d3"},{"id":"cw-f2e82dfca2ced2ee","name":"K6-2/350AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-350afr"],"fields":[{"key":"Model name","value":"K6-2/350AFR","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/350AFR","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/350AFR","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":349.99,"unit":"MHz","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8364-r26059","location":"Amd/k6-2/k6-2-350afr · revision 26059 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f2e82dfca2ced2ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8364-r26059"],"url":"https://museum.vlsi.kr/objects/cw-f2e82dfca2ced2ee"},{"id":"cw-f31ea892bd11a1d8","name":"Am486DX2-66V16B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1997,"architecture":"80486","process":"350 nm","aliases":["Amd am486 am486dx2-66v16b"],"fields":[{"key":"Model name","value":"Am486DX2-66V16B","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-66V16B","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX2-66V16BHC","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX2-66V16BGC","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX2-66V16BHI","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX2-66V16BGI","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1997","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8564-r26762","location":"Amd/am486/am486dx2-66v16b · revision 26762 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f31ea892bd11a1d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8564-r26762"],"url":"https://museum.vlsi.kr/objects/cw-f31ea892bd11a1d8"},{"id":"cw-f32a4e93cfc16798","name":"Xeon Gold 5215","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5215"],"fields":[{"key":"Model name","value":"Xeon Gold 5215","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5215,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504214002","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBC","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-90-r97047","location":"Intel/xeon gold/5215 · revision 97047 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-04. Not an independent measurement.","entityId":"cw-f32a4e93cfc16798","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","sourceDate":"2022-10-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-90-r97047"],"url":"https://museum.vlsi.kr/objects/cw-f32a4e93cfc16798"},{"id":"cw-f358f018c9804029","name":"Xeon E3-1268L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1268l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1268L v5","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1268L v5","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201937901","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LQ","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v5","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P530","unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6442-r20140","location":"Intel/xeon e3/e3-1268l v5 · revision 20140 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f358f018c9804029","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6442-r20140"],"url":"https://museum.vlsi.kr/objects/cw-f358f018c9804029"},{"id":"cw-f376073a3094c5ef","name":"Exynos 7880","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2017,"architecture":"Cortex-A53","process":"14 nm","aliases":["Samsung exynos 7880"],"fields":[{"key":"Model name","value":"Exynos 7880","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7880,"unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2017","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2017","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6840-r21322","location":"Samsung/exynos/7880 · revision 21322 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-f376073a3094c5ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6840-r21322"],"url":"https://museum.vlsi.kr/objects/cw-f376073a3094c5ef"},{"id":"cw-f391360ec809bc56","name":"Spring Hill","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2019,"process":"10 nm","aliases":["Intel microarchitectures spring hill"],"fields":[{"key":"Architecture name","value":"Spring Hill","unit":"","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May, 2019","unit":"","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1229-r3858","location":"Intel/microarchitectures/spring hill · revision 3858 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Slice","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-f391360ec809bc56","scope":"Slice","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1229-r3858"],"url":"https://museum.vlsi.kr/objects/cw-f391360ec809bc56"},{"id":"cw-f39434ffc32207e9","name":"FT-2000+/64","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Phytium","series":"FT-2000+","year":2019,"architecture":"Mars II","process":"16 nm","aliases":["Phytium feiteng ft-2000+-64"],"fields":[{"key":"Model name","value":"FT-2000+/64","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Phytium","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FT-2000+/64","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2019,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2019,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"FeiTeng","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"FT-2000+","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.0","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Mars II","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"FTC-662","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":6000000000,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":370,"unit":"mm²","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":96,"unit":"W","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x2 MiB","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":143.1,"unit":"GiB/s","sourceId":"chipswiki-3770-r11697","location":"Phytium/feiteng/ft-2000+-64 · revision 11697 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-f39434ffc32207e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3770-r11697"],"url":"https://museum.vlsi.kr/objects/cw-f39434ffc32207e9"},{"id":"cw-f3a30369c3c442b0","name":"Athlon MP 1200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp ahx1200dhs3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1200","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1200","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AHX1200DHS3C","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.55,"unit":"V","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8459-r26652","location":"Amd/athlon mp/ahx1200dhs3c · revision 26652 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3a30369c3c442b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8459-r26652","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-f3a30369c3c442b0"},{"id":"cw-f3b34f0684efb028","name":"Xeon E-2126G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2126g"],"fields":[{"key":"Model name","value":"Xeon E-2126G","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2126G","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403380219","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3WU","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake E","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-3033-r10101","location":"Intel/xeon e/e-2126g · revision 10101 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-f3b34f0684efb028","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3033-r10101"],"url":"https://museum.vlsi.kr/objects/cw-f3b34f0684efb028"},{"id":"cw-f3bd5126815245fc","name":"Core i3-2328M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2328m"],"fields":[{"key":"Model name","value":"Core i3-2328M","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2328M","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701275100","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0TC","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8015-r25596","location":"Intel/core i3/i3-2328m · revision 25596 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3bd5126815245fc","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8015-r25596","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-f3bd5126815245fc"},{"id":"cw-f3c14daf78904e9f","name":"Core i5-520UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-500","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-520um"],"fields":[{"key":"Model name","value":"Intel Core i5-520UM","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-520UM","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005352AA","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1066.66,"unit":"MHz","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBQP","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSQ","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7936-r25481","location":"Intel/core i5/i5-520um · revision 25481 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f3c14daf78904e9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7936-r25481","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-f3c14daf78904e9f"},{"id":"cw-f4101a68850f4266","name":"Atom Z510","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z510"],"fields":[{"key":"Model name","value":"Atom Z510","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z510","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UC005DE","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB2C","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2,"unit":"W","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8070-r25706","location":"Intel/atom/z510 · revision 25706 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4101a68850f4266","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8070-r25706","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-f4101a68850f4266"},{"id":"cw-f4469381937f07ae","name":"Helio A22 (MT6762M)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio A","year":2018,"architecture":"Cortex-A53","process":"12 nm","aliases":["Mediatek helio mt6762m"],"fields":[{"key":"Model name","value":"Helio A22","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio A22","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6762M","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 17, 2018","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 17, 2018","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio A","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.9,"unit":"GiB/s","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GE8320","unit":"","sourceId":"chipswiki-9-r96925","location":"Mediatek/helio/mt6762m · revision 96925 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-29. Not an independent measurement.","entityId":"cw-f4469381937f07ae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","sourceDate":"2022-11-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9-r96925"],"url":"https://museum.vlsi.kr/objects/cw-f4469381937f07ae"},{"id":"cw-f44ed71dcb5b0ee0","name":"Ryzen 5 2600H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000H","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 2600h"],"fields":[{"key":"Model name","value":"Ryzen 5 2600H","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2600H","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM2600C3T4MFB","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000H","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4834-r15632","location":"Amd/ryzen 5/2600h · revision 15632 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-f44ed71dcb5b0ee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4834-r15632","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-f44ed71dcb5b0ee0"},{"id":"cw-f45361332419ea5f","name":"Xeon E7-8894 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-8000","year":2017,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e7 e7-8894 v4"],"fields":[{"key":"Model name","value":"Xeon E7-8894 v4","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8894 v4","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Q1 2017","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Q1 2017","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8000","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":3,"unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EX","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"3.07 TiB","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x256 KiB","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":60,"unit":"MiB","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x2.5 MiB","unit":"","sourceId":"chipswiki-3955-r12634","location":"Intel/xeon e7/e7-8894 v4 · revision 12634 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f45361332419ea5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3955-r12634"],"url":"https://museum.vlsi.kr/objects/cw-f45361332419ea5f"},{"id":"cw-f45db0081b3a99f4","name":"AMD-K6-166ALR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-166alr"],"fields":[{"key":"Model name","value":"AMD-K6-166ALR","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-166ALR","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-166ALR","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":166.66,"unit":"MHz","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8299-r25988","location":"Amd/k6/amd-k6-166alr · revision 25988 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f45db0081b3a99f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8299-r25988"],"url":"https://museum.vlsi.kr/objects/cw-f45db0081b3a99f4"},{"id":"cw-f474376254043f7e","name":"Xeon E5-1660 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-1000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-1660 v4"],"fields":[{"key":"Model name","value":"Xeon E5-1660 v4","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-1660 v4","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002646401","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-1000","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2PK","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP Workstation","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":20,"unit":"MiB","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2.5 MiB","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7589-r24673","location":"Intel/xeon e5/e5-1660 v4 · revision 24673 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-f474376254043f7e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7589-r24673"],"url":"https://museum.vlsi.kr/objects/cw-f474376254043f7e"},{"id":"cw-f4af8d6c09768092","name":"Mobile Pentium II 300PE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1999,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 300pe"],"fields":[{"key":"Model name","value":"Mobile Pentium II 300PE","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"300PE","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMG30002002AA","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KP80524KX300256","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KC80524KX300256","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1998,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 25, 1999","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3HJ","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL32R","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL32N","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dixon","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdpA0","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdbA0","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdxA0","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27400000,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":180,"unit":"mm²","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":11.6,"unit":"W","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7804-r25243","location":"Intel/mobile pentium ii/300pe · revision 25243 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f4af8d6c09768092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7804-r25243"],"url":"https://museum.vlsi.kr/objects/cw-f4af8d6c09768092"},{"id":"cw-f4c984558f0bd5ea","name":"Kittson","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2017,"process":"22 nm","aliases":["Intel microarchitectures kittson"],"fields":[{"key":"Architecture name","value":"Kittson","unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2017,"unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Poulson","unit":"","sourceId":"chipswiki-8766-r27228","location":"Intel/microarchitectures/kittson · revision 27228 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-f4c984558f0bd5ea","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8766-r27228"],"url":"https://museum.vlsi.kr/objects/cw-f4c984558f0bd5ea"},{"id":"cw-f4d6939b1e8f929c","name":"SC2A11","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Socionext","year":2017,"architecture":"Cortex-A53","aliases":["Socionext sc2a11"],"fields":[{"key":"Model name","value":"Socionext SC2A11","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Socionext","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SC2A11","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 14, 2016","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":64,"unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x256 KiB","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3888-r12290","location":"Socionext/sc2a11 · revision 12290 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-15. Not an independent measurement.","entityId":"cw-f4d6939b1e8f929c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","sourceDate":"2019-02-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3888-r12290"],"url":"https://museum.vlsi.kr/objects/cw-f4d6939b1e8f929c"},{"id":"cw-f509591109615f32","name":"Samuel","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Centaur Technology","year":null,"process":"0.18 µm","aliases":["Centaur microarchitectures samuel"],"fields":[{"key":"Architecture name","value":"Samuel","unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Centaur Technology","unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":12,"unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Joshua","unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Samuel 2","unit":"","sourceId":"chipswiki-7383-r23870","location":"Centaur/microarchitectures/samuel · revision 23870 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-f509591109615f32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7383-r23870"],"url":"https://museum.vlsi.kr/objects/cw-f509591109615f32"},{"id":"cw-f517f07b3bc3667e","name":"Celeron 827E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 827e"],"fields":[{"key":"Model name","value":"Celeron 827E","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"827E","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701082300","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0C6","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2011","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2011","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6941-r21628","location":"Intel/celeron/827e · revision 21628 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-f517f07b3bc3667e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6941-r21628","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-f517f07b3bc3667e"},{"id":"cw-f5206d38ffa7b4ed","name":"Celeron G3900T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron g3900t"],"fields":[{"key":"Model name","value":"Celeron G3900T","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3900T","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8031-r25635","location":"Intel/celeron/g3900t · revision 25635 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5206d38ffa7b4ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8031-r25635","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-f5206d38ffa7b4ed"},{"id":"cw-f54799fe0a584d5d","name":"MG80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 mg80186-6"],"fields":[{"key":"Model name","value":"MG80186-6","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MG80186-6","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MG80186-6","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8635-r26834","location":"Amd/am186/mg80186-6 · revision 26834 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f54799fe0a584d5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8635-r26834"],"url":"https://museum.vlsi.kr/objects/cw-f54799fe0a584d5d"},{"id":"cw-f5542e5da732ed6e","name":"Xeon Platinum 9221","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"9200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 9221"],"fields":[{"key":"Model name","value":"Xeon Platinum 9221","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9221,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":9200,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Walker Pass","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake AP","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":250,"unit":"W","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":71.5,"unit":"MiB","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"52x1.375 MiB","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":12,"unit":"","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":262.26,"unit":"GiB/s","sourceId":"chipswiki-2234-r7703","location":"Intel/xeon platinum/9221 · revision 7703 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-04. Not an independent measurement.","entityId":"cw-f5542e5da732ed6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","sourceDate":"2019-06-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2234-r7703"],"url":"https://museum.vlsi.kr/objects/cw-f5542e5da732ed6e"},{"id":"cw-f5766a74fb048105","name":"Core i3-8300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8300"],"fields":[{"key":"Model name","value":"Core i3-8300","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8300","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80684I38300","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377111","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3XY","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":62,"unit":"W","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-6454-r20195","location":"Intel/core i3/i3-8300 · revision 20195 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-f5766a74fb048105","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6454-r20195"],"url":"https://museum.vlsi.kr/objects/cw-f5766a74fb048105"},{"id":"cw-f5a4cbd0507ca237","name":"Core i7-2649M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2649m"],"fields":[{"key":"Model name","value":"Core i7-2649M","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2649M","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700850010S","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04N","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7891-r25395","location":"Intel/core i7/i7-2649m · revision 25395 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5a4cbd0507ca237","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7891-r25395","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-f5a4cbd0507ca237"},{"id":"cw-f5be2949430e78c8","name":"Pentium U5400","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P6000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel pentium (2009) u5400"],"fields":[{"key":"Model name","value":"Intel Pentium U5400","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"U5400","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006042AC","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 25, 2010","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 25, 2010","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P6000","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1199.99,"unit":"MHz","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUH","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7776-r25207","location":"Intel/pentium (2009)/u5400 · revision 25207 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f5be2949430e78c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7776-r25207","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-f5be2949430e78c8"},{"id":"cw-f5ea682bf9350582","name":"Xeon D-1553N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2017,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1553n"],"fields":[{"key":"Model name","value":"Xeon D-1553N","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1553N","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068203255104","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KT","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2017","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3726-r11423","location":"Intel/xeon d/d-1553n · revision 11423 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-f5ea682bf9350582","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3726-r11423"],"url":"https://museum.vlsi.kr/objects/cw-f5ea682bf9350582"},{"id":"cw-f5fe2d6200b7e0b4","name":"Xeon Gold 6136","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6136"],"fields":[{"key":"Model name","value":"Xeon Gold 6136","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6136,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405800","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B2","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1508-r4960","location":"Intel/xeon gold/6136 · revision 4960 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f5fe2d6200b7e0b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1508-r4960"],"url":"https://museum.vlsi.kr/objects/cw-f5fe2d6200b7e0b4"},{"id":"cw-f6061f818b58ed7b","name":"i486SL-20","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SL","year":1992,"architecture":"80486","process":"800 nm","aliases":["Intel 80486 486sl-20"],"fields":[{"key":"Model name","value":"Intel i486SL-20","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SL-20","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SL-20","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 9, 1992","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SL","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"20 MT/s","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SL","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1400000,"unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8084-r25735","location":"Intel/80486/486sl-20 · revision 25735 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6061f818b58ed7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8084-r25735"],"url":"https://museum.vlsi.kr/objects/cw-f6061f818b58ed7b"},{"id":"cw-f63238795bb0379a","name":"X-Gene 1 APM883408-X1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AppliedMicro","series":"X-Gene 1","year":2012,"architecture":"Storm","process":"40 nm","aliases":["Apm x-gene apm883408-x1"],"fields":[{"key":"Model name","value":"APM883408-X1","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"APM883408-X1","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 28, 2011","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X-Gene","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"X-Gene 1","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Storm","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Potenza","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1866","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-4750-r15326","location":"Apm/x-gene/apm883408-x1 · revision 15326 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f63238795bb0379a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4750-r15326"],"url":"https://museum.vlsi.kr/objects/cw-f63238795bb0379a"},{"id":"cw-f65762738e74948e","name":"Atom Z610","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z610","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z610"],"fields":[{"key":"Model name","value":"Atom Z610","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z610","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609005793AA","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZQ","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z610","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":1.3,"unit":"W","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-25 °C","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8057-r25693","location":"Intel/atom/z610 · revision 25693 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f65762738e74948e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8057-r25693","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-f65762738e74948e"},{"id":"cw-f65addf272b32f3b","name":"Xeon E-2224","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2224"],"fields":[{"key":"Model name","value":"Xeon E-2224","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2224","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404174707","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFAV","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":71,"unit":"W","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2412-r8056","location":"Intel/xeon e/e-2224 · revision 8056 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-f65addf272b32f3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2412-r8056"],"url":"https://museum.vlsi.kr/objects/cw-f65addf272b32f3b"},{"id":"cw-f661f2dde2cde1d9","name":"Core i5-1030G4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i5 i5-1030g4"],"fields":[{"key":"Model name","value":"Core i5-1030G4","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-1030G4","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-10000","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake Y","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9,"unit":"W","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-1241-r3951","location":"Intel/core i5/i5-1030g4 · revision 3951 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-f661f2dde2cde1d9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1241-r3951"],"url":"https://museum.vlsi.kr/objects/cw-f661f2dde2cde1d9"},{"id":"cw-f67693ec7d5f98e2","name":"AMD-K5-PR133ABQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr133abq"],"fields":[{"key":"Model name","value":"AMD-K5-PR133ABQ","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR133ABQ","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR133ABQ","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":99.99,"unit":"MHz","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.666 MT/s","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8400-r26096","location":"Amd/k5/amd-k5-pr133abq · revision 26096 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f67693ec7d5f98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8400-r26096"],"url":"https://museum.vlsi.kr/objects/cw-f67693ec7d5f98e2"},{"id":"cw-f68555cd269d0e68","name":"Core i7-920XM Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-900","year":2009,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7ee i7-920xm"],"fields":[{"key":"Model name","value":"Core i7-920XM Extreme Edition","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-920XM","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BY80607002529AF","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2009","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Sep 23, 2009","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-900","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3199.99,"unit":"MHz","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBLW","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Clarksfield","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":30,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":774000000,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":296,"unit":"mm²","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G1","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-4726-r15149","location":"Intel/core i7ee/i7-920xm · revision 15149 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-05. Not an independent measurement.","entityId":"cw-f68555cd269d0e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","sourceDate":"2018-10-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4726-r15149"],"url":"https://museum.vlsi.kr/objects/cw-f68555cd269d0e68"},{"id":"cw-f6b522f4a6a07c20","name":"EPYC 7351P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7351p"],"fields":[{"key":"Model name","value":"EPYC 7351P","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7351P","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS735PBEVGPAF","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x64 KiB","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5072-r16544","location":"Amd/epyc/7351p · revision 16544 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-f6b522f4a6a07c20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5072-r16544","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-f6b522f4a6a07c20"},{"id":"cw-f6baaa25fcc21609","name":"Ryzen 5 5600GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 5600ge"],"fields":[{"key":"Model name","value":"Ryzen 5 5600GE","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5600GE","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000261","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 13, 2021","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-713-r1720","location":"Amd/ryzen 5/5600ge · revision 1720 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f6baaa25fcc21609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-713-r1720"],"url":"https://museum.vlsi.kr/objects/cw-f6baaa25fcc21609"},{"id":"cw-f6db8cc49bc14217","name":"Denver","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"NVIDIA","year":2014,"process":"28 nm","aliases":["Nvidia microarchitectures denver"],"fields":[{"key":"Architecture name","value":"Denver","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Nvidia","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2014,"unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"2-way","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Carmel","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x128 KiB","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1300-r4341","location":"Nvidia/microarchitectures/denver · revision 4341 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-11. Not an independent measurement.","entityId":"cw-f6db8cc49bc14217","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","sourceDate":"2020-02-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1300-r4341"],"url":"https://museum.vlsi.kr/objects/cw-f6db8cc49bc14217"},{"id":"cw-f6df8cac7f01502a","name":"A13 Bionic","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2019,"process":"7 nm (N7P)","aliases":["Apple ax a13"],"fields":[{"key":"Model name","value":"A13 Bionic","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A13 Bionic","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2019","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 2019","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.4","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lightning","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thunder","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm (N7P)","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8500000000,"unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.48,"unit":"mm²","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-186-r374","location":"Apple/ax/a13 · revision 374 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-24. Not an independent measurement.","entityId":"cw-f6df8cac7f01502a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","sourceDate":"2022-09-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-186-r374"],"url":"https://museum.vlsi.kr/objects/cw-f6df8cac7f01502a"},{"id":"cw-f6e669918d7f427e","name":"Core i5-2580M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2580m"],"fields":[{"key":"Model name","value":"Core i5-2580M","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2580M","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701122300","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0GD","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7944-r25492","location":"Intel/core i5/i5-2580m · revision 25492 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f6e669918d7f427e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7944-r25492","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-f6e669918d7f427e"},{"id":"cw-f7113c24b02b6c31","name":"AWS Graviton","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Annapurna Labs","year":2018,"architecture":"Cortex-A72","process":"16 nm","aliases":["Annapurna labs alpine al73400"],"fields":[{"key":"Model name","value":"AWS Graviton","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Annapurna Labs","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AL73400","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AL73400-00-A0","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 27, 2018","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 27, 2018","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alpine","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A72","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":5000000000,"unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x48 KiB","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-282-r567","location":"Annapurna labs/alpine/al73400 · revision 567 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-20. Not an independent measurement.","entityId":"cw-f7113c24b02b6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","sourceDate":"2022-07-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-282-r567"],"url":"https://museum.vlsi.kr/objects/cw-f7113c24b02b6c31"},{"id":"cw-f7119d85657fde17","name":"TMS1099","kind":"sku","entityType":"product-model","subtype":"sku","company":"Texas Instruments","year":null,"architecture":"TMS1000","process":"8 µm","aliases":["Ti tms1000 tms1099"],"fields":[{"key":"Model name","value":"TMS1099","unit":"","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Texas Instruments","unit":"","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Texas Instruments","unit":"","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"TMS1099","unit":"","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"TMS1000","unit":"","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"TMS1000","unit":"","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"µm","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"KiB","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":15,"unit":"V","sourceId":"chipswiki-8670-r26885","location":"Ti/tms1000/tms1099 · revision 26885 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"PDIP-64","unit":"","sourceId":"chipswiki-31332-r92062","location":"Template:Packages/pdip-64 · revision 92062 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"PDIP","unit":"","sourceId":"chipswiki-31332-r92062","location":"Template:Packages/pdip-64 · revision 92062 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":64,"unit":"","sourceId":"chipswiki-31332-r92062","location":"Template:Packages/pdip-64 · revision 92062 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"CDIP-64","unit":"","sourceId":"chipswiki-31333-r92063","location":"Template:Packages/cdip-64 · revision 92063 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"CDIP","unit":"","sourceId":"chipswiki-31333-r92063","location":"Template:Packages/cdip-64 · revision 92063 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":64,"unit":"","sourceId":"chipswiki-31333-r92063","location":"Template:Packages/cdip-64 · revision 92063 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7119d85657fde17","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8670-r26885","chipswiki-31332-r92062","chipswiki-31333-r92063"],"url":"https://museum.vlsi.kr/objects/cw-f7119d85657fde17"},{"id":"cw-f739f9f97f64fe0f","name":"Atom Z510P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2009,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z510p"],"fields":[{"key":"Model name","value":"Atom Z510P","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z510P","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CH80566EC005DW","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLGPQ","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2,"unit":"W","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8069-r25705","location":"Intel/atom/z510p · revision 25705 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f739f9f97f64fe0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8069-r25705","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-f739f9f97f64fe0f"},{"id":"cw-f741a1bdcae871f2","name":"Core i3-2312M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2312m"],"fields":[{"key":"Model name","value":"Core i3-2312M","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2312M","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701084601","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR09S","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8016-r25597","location":"Intel/core i3/i3-2312m · revision 25597 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f741a1bdcae871f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8016-r25597","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-f741a1bdcae871f2"},{"id":"cw-f7737dec2d5e92b7","name":"QorIQ P1015","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2012,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1015"],"fields":[{"key":"Model name","value":"QorIQ P1015","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1015","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":400,"unit":"MHz","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":533,"unit":"MHz","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8102-r25761","location":"Freescale/qoriq/p1015 · revision 25761 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-561","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":561,"unit":"","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":23,"unit":"mm","sourceId":"chipswiki-31376-r92171","location":"Template:Packages/freescale/te-pbga-561 · revision 92171 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7737dec2d5e92b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8102-r25761","chipswiki-31376-r92171"],"url":"https://museum.vlsi.kr/objects/cw-f7737dec2d5e92b7"},{"id":"cw-f7784bb26d8e2e05","name":"Ryzen 5 3580U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 3580u"],"fields":[{"key":"Model name","value":"Ryzen 5 3580U","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3580U","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 2019","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 2019","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":9,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-922-r2546","location":"Amd/ryzen 5/3580u · revision 2546 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-f7784bb26d8e2e05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-922-r2546"],"url":"https://museum.vlsi.kr/objects/cw-f7784bb26d8e2e05"},{"id":"cw-f78de43f4717aee0","name":"CN3120-300 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-300bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3120-300 SCP","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-300 SCP","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-300BG868-SCP","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8250-r25910","location":"Cavium/octeon/cn3120-300bg868-scp · revision 25910 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f78de43f4717aee0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8250-r25910","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-f78de43f4717aee0"},{"id":"cw-f7b18b0b50749775","name":"Cooper Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2020,"process":"14 nm","aliases":["Intel microarchitectures cooper lake"],"fields":[{"key":"Architecture name","value":"Cooper Lake","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"June 18, 2020","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cooper Lake X","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cooper Lake SP","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cooper Lake AP","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cascade Lake","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Ice Lake (Server)","unit":"","sourceId":"chipswiki-294-r591","location":"Intel/microarchitectures/cooper lake · revision 591 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-f7b18b0b50749775","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-294-r591"],"url":"https://museum.vlsi.kr/objects/cw-f7b18b0b50749775"},{"id":"cw-f7ce9b768671cb62","name":"Am186CH-25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CH","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186ch-25kc\\w"],"fields":[{"key":"Model name","value":"Am186CH-25KC\\W","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CH-25KC\\W","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CH-25KC\\W","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CH","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14686-r44747","location":"Amd/am186cx/am186ch-25kc\\w · revision 44747 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7ce9b768671cb62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14686-r44747"],"url":"https://museum.vlsi.kr/objects/cw-f7ce9b768671cb62"},{"id":"cw-f7d22399ebb8b102","name":"Xeon Platinum 8260Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8260y"],"fields":[{"key":"Model name","value":"Xeon Platinum 8260Y","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8260Y","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504200902","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9F","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1462-r4909","location":"Intel/xeon platinum/8260y · revision 4909 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-f7d22399ebb8b102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1462-r4909"],"url":"https://museum.vlsi.kr/objects/cw-f7d22399ebb8b102"},{"id":"cw-f7f1271956c4ae7b","name":"Am186ESLV–25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1997,"architecture":"80186","aliases":["Amd am186ex am186eslv–25kc\\w"],"fields":[{"key":"Model name","value":"Am186ESLV–25KC\\W","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ESLV–25KC\\W","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ESLV–25KC\\W","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14629-r44690","location":"Amd/am186ex/am186eslv–25kc\\w · revision 44690 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f1271956c4ae7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14629-r44690"],"url":"https://museum.vlsi.kr/objects/cw-f7f1271956c4ae7b"},{"id":"cw-f7f4ef68700e570f","name":"Core i7-620UE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-620ue"],"fields":[{"key":"Model name","value":"Intel Core i7-620UE","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-620UE","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004458AB","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1066.66,"unit":"MHz","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBXJ","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7853-r25352","location":"Intel/core i7/i7-620ue · revision 25352 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f7f4ef68700e570f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7853-r25352","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-f7f4ef68700e570f"},{"id":"cw-f7f9151508355c6b","name":"Am186ESLV–20VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1997,"architecture":"80186","aliases":["Amd am186ex am186eslv–20vc\\w"],"fields":[{"key":"Model name","value":"Am186ESLV–20VC\\W","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ESLV–20VC\\W","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ESLV–20VC\\W","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14630-r44691","location":"Amd/am186ex/am186eslv–20vc\\w · revision 44691 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-f7f9151508355c6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14630-r44691"],"url":"https://museum.vlsi.kr/objects/cw-f7f9151508355c6b"},{"id":"cw-f7fb3ffa3e30a553","name":"EPYC 7443P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7443p"],"fields":[{"key":"Model name","value":"EPYC 7443P","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7443P","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000342","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000342WOF","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2850,"unit":"MHz","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24 × 32 KiB","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24 × 512 KiB","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-752-r1794","location":"Amd/epyc/7443p · revision 1794 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-f7fb3ffa3e30a553","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-752-r1794"],"url":"https://museum.vlsi.kr/objects/cw-f7fb3ffa3e30a553"},{"id":"cw-f8009372e2f0789a","name":"Machine Learning Processor (MLP)","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2018,"process":"16 nm","aliases":["Arm holdings microarchitectures mlp"],"fields":[{"key":"Architecture name","value":"MLP","unit":"","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Arm Holdings","unit":"","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"UMC","unit":"","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1310-r4387","location":"Arm holdings/microarchitectures/mlp · revision 4387 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-02-07. Not an independent measurement.","entityId":"cw-f8009372e2f0789a","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","sourceDate":"2020-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1310-r4387"],"url":"https://museum.vlsi.kr/objects/cw-f8009372e2f0789a"},{"id":"cw-f8127b2a373406d3","name":"X-Gene 1 APM883208-X1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AppliedMicro","series":"X-Gene 1","year":2012,"architecture":"Storm","process":"40 nm","aliases":["Apm x-gene apm883208-x1"],"fields":[{"key":"Model name","value":"APM883208-X1","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"APM883208-X1","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 28, 2011","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X-Gene","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"X-Gene 1","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Storm","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Potenza","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1866","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.82,"unit":"GiB/s","sourceId":"chipswiki-4751-r15329","location":"Apm/x-gene/apm883208-x1 · revision 15329 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-f8127b2a373406d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4751-r15329"],"url":"https://museum.vlsi.kr/objects/cw-f8127b2a373406d3"},{"id":"cw-f8181dff76c008f9","name":"AM9080A-2DC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2dc"],"fields":[{"key":"Model name","value":"AMD AM9080A-2DC","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2DC","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2DC","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8482-r26675","location":"Amd/am9080/am9080a-2dc · revision 26675 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f8181dff76c008f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8482-r26675"],"url":"https://museum.vlsi.kr/objects/cw-f8181dff76c008f9"},{"id":"cw-f82449d183dcb2d7","name":"ARM8","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":1996,"aliases":["Arm holdings microarchitectures arm8"],"fields":[{"key":"Architecture name","value":"ARM8","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"July 8, 1996","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv4","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM7","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM9","unit":"","sourceId":"chipswiki-1668-r5834","location":"Arm holdings/microarchitectures/arm8 · revision 5834 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-f82449d183dcb2d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1668-r5834"],"url":"https://museum.vlsi.kr/objects/cw-f82449d183dcb2d7"},{"id":"cw-f882c42191e1045b","name":"POWER9 02CY417","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy417"],"fields":[{"key":"Model name","value":"02CY417","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY417","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY417","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.3,"unit":"GHz","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":80,"unit":"MiB","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x10 MiB","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3941-r12569","location":"Ibm/power/02cy417 · revision 12569 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-f882c42191e1045b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3941-r12569"],"url":"https://museum.vlsi.kr/objects/cw-f882c42191e1045b"},{"id":"cw-f8cf8363e356214f","name":"Core i5-7440HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7400","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7440hq"],"fields":[{"key":"Model name","value":"Core i5-7440HQ","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7440HQ","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32R","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7400","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6418-r20018","location":"Intel/core i5/i5-7440hq · revision 20018 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-f8cf8363e356214f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6418-r20018","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-f8cf8363e356214f"},{"id":"cw-f8e91c1ee25e0b1a","name":"Ryzen 5 5600HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 5600hs"],"fields":[{"key":"Model name","value":"Ryzen 5 5600HS","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5600HS","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000296","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1800,"unit":"MHz","sourceId":"chipswiki-715-r1722","location":"Amd/ryzen 5/5600hs · revision 1722 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-f8e91c1ee25e0b1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-715-r1722"],"url":"https://museum.vlsi.kr/objects/cw-f8e91c1ee25e0b1a"},{"id":"cw-f8f2d403ffe4c613","name":"KaiXian KX-U5680","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KX-5000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaixian kx-u5680"],"fields":[{"key":"Model name","value":"KaiXian KX-U5680","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KX-U5680","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KX-U5680","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaiXian","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KX-5000","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5648-r18546","location":"Zhaoxin/kaixian/kx-u5680 · revision 18546 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-f8f2d403ffe4c613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5648-r18546"],"url":"https://museum.vlsi.kr/objects/cw-f8f2d403ffe4c613"},{"id":"cw-f8f477ae8de51e68","name":"cnMIPS","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Cavium","year":2004,"process":"130 nm","aliases":["Cavium microarchitectures cnmips"],"fields":[{"key":"Architecture name","value":"cnMIPS","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 13, 2004","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":5,"unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"1-2 MiB","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"chip","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"chip","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"cnMIPS II","unit":"","sourceId":"chipswiki-14801-r46395","location":"Cavium/microarchitectures/cnmips · revision 46395 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-23. Not an independent measurement.","entityId":"cw-f8f477ae8de51e68","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14801-r46395"],"url":"https://museum.vlsi.kr/objects/cw-f8f477ae8de51e68"},{"id":"cw-f93c730e505b5ffa","name":"CG80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 cg80186-6"],"fields":[{"key":"Model name","value":"CG80186-6","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CG80186-6","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CG80186-6","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CG80186-6B","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8650-r26849","location":"Amd/am186/cg80186-6 · revision 26849 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93c730e505b5ffa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8650-r26849"],"url":"https://museum.vlsi.kr/objects/cw-f93c730e505b5ffa"},{"id":"cw-f93e2a8e6d3a7241","name":"Atom N270","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N200","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom n270"],"fields":[{"key":"Model name","value":"Atom N270","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N270","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AU80586GE025D","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB73","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2008","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N200","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1599.99,"unit":"MHz","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Nettop 2008","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Calistoga","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Diamondville","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":112,"unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":25.9638,"unit":"mm²","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.5,"unit":"W","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8073-r25709","location":"Intel/atom/n270 · revision 25709 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-f93e2a8e6d3a7241","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8073-r25709","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-f93e2a8e6d3a7241"},{"id":"cw-f94a554209a076f4","name":"Falkor","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Qualcomm","year":2017,"process":"10 nm","aliases":["Qualcomm microarchitectures falkor"],"fields":[{"key":"Architecture name","value":"Falkor","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 8, 2017","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":40,"unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"duplex","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"duplex","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":5,"unit":"MiB","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"block","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"block","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Saphira","unit":"","sourceId":"chipswiki-743-r1781","location":"Qualcomm/microarchitectures/falkor · revision 1781 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-f94a554209a076f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-743-r1781"],"url":"https://museum.vlsi.kr/objects/cw-f94a554209a076f4"},{"id":"cw-f99505405af2074d","name":"Atom C3950","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3950"],"fields":[{"key":"Model name","value":"Atom C3950","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3950","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502638901","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR383","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":24,"unit":"W","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x24 KiB","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1870-r6406","location":"Intel/atom/c3950 · revision 6406 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-f99505405af2074d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1870-r6406","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-f99505405af2074d"},{"id":"cw-f99874d30f1eef0f","name":"Alchemy Au1500-333MBF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1500-333mbf"],"fields":[{"key":"Model name","value":"Alchemy Au1500-333MBF","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-333MBF","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1500-333MBF","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2001","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AB","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AC","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AD","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-482-r966","location":"Alchemy/au1500-333mbf · revision 966 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-f99874d30f1eef0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-482-r966"],"url":"https://museum.vlsi.kr/objects/cw-f99874d30f1eef0f"},{"id":"cw-f99bb0e202eadc9f","name":"Ryzen 5 4680U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2021,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 4680u"],"fields":[{"key":"Model name","value":"Ryzen 5 4680U","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4680U","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 13, 2021","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-692-r1687","location":"Amd/ryzen 5/4680u · revision 1687 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-f99bb0e202eadc9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-692-r1687"],"url":"https://museum.vlsi.kr/objects/cw-f99bb0e202eadc9f"},{"id":"cw-fa113503207b9473","name":"Exynos 7870","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2016,"architecture":"Cortex-A53","process":"14 nm","aliases":["Samsung exynos 7870"],"fields":[{"key":"Model name","value":"Exynos 7870","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7870,"unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 17, 2016","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 17, 2016","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6842-r21325","location":"Samsung/exynos/7870 · revision 21325 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-fa113503207b9473","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6842-r21325"],"url":"https://museum.vlsi.kr/objects/cw-fa113503207b9473"},{"id":"cw-fa1c032fc8b22a15","name":"D8086-1B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 d8086-1b"],"fields":[{"key":"Model name","value":"AMD D8086-1B","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D8086-1B","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D8086-1B","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D8086","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8516-r26709","location":"Amd/am8086/d8086-1b · revision 26709 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa1c032fc8b22a15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8516-r26709"],"url":"https://museum.vlsi.kr/objects/cw-fa1c032fc8b22a15"},{"id":"cw-fa35b0b3e3c55825","name":"Cortex-A53","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2012,"process":"40 nm","aliases":["Arm holdings microarchitectures cortex-a53"],"fields":[{"key":"Architecture name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 30, 2012","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / process 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 4","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"process 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / process 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 5","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"process 5","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / process 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 6","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"process 6","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"In-order","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"2-way","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"128 KiB - 2 MiB","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A7","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A55","unit":"","sourceId":"chipswiki-493-r985","location":"Arm holdings/microarchitectures/cortex-a53 · revision 985 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-fa35b0b3e3c55825","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-493-r985"],"url":"https://museum.vlsi.kr/objects/cw-fa35b0b3e3c55825"},{"id":"cw-fa4101bd5d130aff","name":"EPYC Embedded 3251","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3251"],"fields":[{"key":"Model name","value":"EPYC Embedded 3251","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3251,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3251BGR88AF","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 64 KiB","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8 × 512 KiB","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 8 MiB","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"42.67 GB/s","unit":"","sourceId":"chipswiki-408-r878","location":"Amd/epyc embedded/3251 · revision 878 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4r2","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-fa4101bd5d130aff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-408-r878","chipswiki-31098-r91557"],"url":"https://museum.vlsi.kr/objects/cw-fa4101bd5d130aff"},{"id":"cw-fa445d253a932fbd","name":"Celeron 797","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"700","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 797"],"fields":[{"key":"Model name","value":"Celeron 797","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":797,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079601","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701345500","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0ED","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0VK","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2012","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2012","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":700,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6946-r21633","location":"Intel/celeron/797 · revision 21633 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fa445d253a932fbd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6946-r21633","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-fa445d253a932fbd"},{"id":"cw-fa56cc9bec3c73d8","name":"D8086-2B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 d8086-2b"],"fields":[{"key":"Model name","value":"AMD D8086-2B","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D8086-2B","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D8086-2B","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D8086","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8514-r26707","location":"Amd/am8086/d8086-2b · revision 26707 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa56cc9bec3c73d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8514-r26707"],"url":"https://museum.vlsi.kr/objects/cw-fa56cc9bec3c73d8"},{"id":"cw-fa59eadd4aa8bd7a","name":"MSM6000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2002,"architecture":"ARM7","process":"250 nm","aliases":["Qualcomm msm6xxx msm6000"],"fields":[{"key":"Model name","value":"Qualcomm MSM6000","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6000","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 12, 2001","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 2002","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM7","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM7TDMI","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FBGA-208","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FBGA","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":0,"unit":"KiB","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"No L1$","unit":"","sourceId":"chipswiki-553-r1149","location":"Qualcomm/msm6xxx/msm6000 · revision 1149 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-23. Not an independent measurement.","entityId":"cw-fa59eadd4aa8bd7a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","sourceDate":"2021-12-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-553-r1149"],"url":"https://museum.vlsi.kr/objects/cw-fa59eadd4aa8bd7a"},{"id":"cw-fa5f61e029d6393b","name":"Knights Ferry","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2010,"process":"45 nm","aliases":["Intel microarchitectures knights ferry"],"fields":[{"key":"Architecture name","value":"Knights Ferry","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 31, 2010","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":32,"unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Rock Creek","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Larrabee","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"predecessor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Knights Corner","unit":"","sourceId":"chipswiki-2502-r8585","location":"Intel/microarchitectures/knights ferry · revision 8585 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-fa5f61e029d6393b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2502-r8585"],"url":"https://museum.vlsi.kr/objects/cw-fa5f61e029d6393b"},{"id":"cw-fa939e5af9347364","name":"TSARLET","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"CEA-Leti","year":null,"process":"28 nm","aliases":["Cea-leti microarchitectures tsarlet"],"fields":[{"key":"Architecture name","value":"TSARLET","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"CEA-Leti","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":96,"unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Single-issue","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":5,"unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-way","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32v1","unit":"","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1227-r3846","location":"Cea-leti/microarchitectures/tsarlet · revision 3846 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2020-03-27. Not an independent measurement.","entityId":"cw-fa939e5af9347364","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","sourceDate":"2020-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1227-r3846"],"url":"https://museum.vlsi.kr/objects/cw-fa939e5af9347364"},{"id":"cw-fa93c2706c2dc837","name":"K6-2E/300AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-300afr"],"fields":[{"key":"Model name","value":"K6-2E/300AFR","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/300AFR","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/300AFR","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8327-r26022","location":"Amd/k6-2/k6-2e-300afr · revision 26022 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa93c2706c2dc837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8327-r26022"],"url":"https://museum.vlsi.kr/objects/cw-fa93c2706c2dc837"},{"id":"cw-fa97481df23ed252","name":"Duron 700 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d700ast1b"],"fields":[{"key":"Model name","value":"Duron 700","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 700","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D700AST1B","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25.5,"unit":"W","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8438-r26146","location":"Amd/duron/d700ast1b · revision 26146 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fa97481df23ed252","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8438-r26146"],"url":"https://museum.vlsi.kr/objects/cw-fa97481df23ed252"},{"id":"cw-faa3ae734c844f02","name":"Xeon Gold 5122","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 5122"],"fields":[{"key":"Model name","value":"Xeon Gold 5122","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5122,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806735122","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303330702","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AT","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5100,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1388-r4672","location":"Intel/xeon gold/5122 · revision 4672 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-12. Not an independent measurement.","entityId":"cw-faa3ae734c844f02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","sourceDate":"2020-01-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1388-r4672"],"url":"https://museum.vlsi.kr/objects/cw-faa3ae734c844f02"},{"id":"cw-faa7a91191bf26c1","name":"Am186ER–25VI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–25vi\\w"],"fields":[{"key":"Model name","value":"Am186ER–25VI\\W","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–25VI\\W","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–25VI\\W","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14645-r44706","location":"Amd/am186ex/am186er–25vi\\w · revision 44706 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-faa7a91191bf26c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14645-r44706"],"url":"https://museum.vlsi.kr/objects/cw-faa7a91191bf26c1"},{"id":"cw-fab1a8858343673f","name":"Xeon W-2195","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2195"],"fields":[{"key":"Model name","value":"Xeon W-2195","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2195","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303805901","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3RX","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2527-r8672","location":"Intel/xeon w/w-2195 · revision 8672 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-fab1a8858343673f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2527-r8672"],"url":"https://museum.vlsi.kr/objects/cw-fab1a8858343673f"},{"id":"cw-fac910a51854682e","name":"POWER11","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2020,"aliases":["Ibm microarchitectures power11"],"fields":[{"key":"Architecture name","value":"POWER11","unit":"","sourceId":"chipswiki-825-r2121","location":"Ibm/microarchitectures/power11 · revision 2121 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-06. Not an independent measurement.","entityId":"cw-fac910a51854682e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","sourceDate":"2021-02-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-825-r2121","location":"Ibm/microarchitectures/power11 · revision 2121 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-06. Not an independent measurement.","entityId":"cw-fac910a51854682e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","sourceDate":"2021-02-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TBD","unit":"","sourceId":"chipswiki-825-r2121","location":"Ibm/microarchitectures/power11 · revision 2121 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-06. Not an independent measurement.","entityId":"cw-fac910a51854682e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","sourceDate":"2021-02-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2020,"unit":"","sourceId":"chipswiki-825-r2121","location":"Ibm/microarchitectures/power11 · revision 2121 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-06. Not an independent measurement.","entityId":"cw-fac910a51854682e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","sourceDate":"2021-02-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-825-r2121","location":"Ibm/microarchitectures/power11 · revision 2121 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-06. Not an independent measurement.","entityId":"cw-fac910a51854682e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","sourceDate":"2021-02-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER10","unit":"","sourceId":"chipswiki-825-r2121","location":"Ibm/microarchitectures/power11 · revision 2121 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-06. Not an independent measurement.","entityId":"cw-fac910a51854682e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","sourceDate":"2021-02-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-825-r2121"],"url":"https://museum.vlsi.kr/objects/cw-fac910a51854682e"},{"id":"cw-fafff66916692a35","name":"Gen3.5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2005,"process":"90 nm","aliases":["Intel microarchitectures gen3.5"],"fields":[{"key":"Architecture name","value":"Gen3.5","unit":"","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2005,"unit":"","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen3","unit":"","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen4","unit":"","sourceId":"chipswiki-15958-r52681","location":"Intel/microarchitectures/gen3.5 · revision 52681 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-fafff66916692a35","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15958-r52681"],"url":"https://museum.vlsi.kr/objects/cw-fafff66916692a35"},{"id":"cw-fb0accf5187ae6e2","name":"CN3110-550 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-550bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3110-550 EXP","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-550 EXP","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-550BG868-EXP","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8256-r25916","location":"Cavium/octeon/cn3110-550bg868-exp · revision 25916 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb0accf5187ae6e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8256-r25916","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-fb0accf5187ae6e2"},{"id":"cw-fb2216f739cbcb83","name":"Alchemy Au1100-500MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-500mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1100-500MBD","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-500MBD","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBDBA","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBDBC","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBDBD","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBDBE","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-500MBDBF","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BA","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BC","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BD","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BE","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BF","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.22,"unit":"V","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.500 GB/s","unit":"","sourceId":"chipswiki-468-r949","location":"Alchemy/au1100-500mbd · revision 949 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-fb2216f739cbcb83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-468-r949"],"url":"https://museum.vlsi.kr/objects/cw-fb2216f739cbcb83"},{"id":"cw-fb238e8a695a894a","name":"Core i7-6770HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6770hq"],"fields":[{"key":"Model name","value":"Core i7-6770HQ","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6770HQ","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QY","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics 580","unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7839-r25332","location":"Intel/core i7/i7-6770hq · revision 25332 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb238e8a695a894a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7839-r25332","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-fb238e8a695a894a"},{"id":"cw-fb38dba9cd843fbc","name":"AMD-X5-150ADY","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-150ady"],"fields":[{"key":"Model name","value":"AMD-X5-150ADY","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-150ADY","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-150ADY","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":150,"unit":"MHz","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8522-r26716","location":"Amd/am5x86/amd-x5-150ady · revision 26716 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb38dba9cd843fbc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8522-r26716"],"url":"https://museum.vlsi.kr/objects/cw-fb38dba9cd843fbc"},{"id":"cw-fb6afc1904a7c590","name":"NVSwitch","kind":"sku","entityType":"product-model","subtype":"sku","company":"NVIDIA","year":2018,"aliases":["Nvidia nvswitch"],"fields":[{"key":"Model name","value":"NVSwitch","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Nvidia","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 27, 2018","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 27, 2018","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":20000000000,"unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4988-r16134","location":"Nvidia/nvswitch · revision 16134 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-fb6afc1904a7c590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4988-r16134"],"url":"https://museum.vlsi.kr/objects/cw-fb6afc1904a7c590"},{"id":"cw-fb7f8e2ff310021b","name":"POWER9 02CY415","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy415"],"fields":[{"key":"Model name","value":"02CY415","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY415","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY415","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.4,"unit":"GHz","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":80,"unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5,"unit":"MiB","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x512 KiB","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":100,"unit":"MiB","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x10 MiB","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-194-r389","location":"Ibm/power/02cy415 · revision 389 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-18. Not an independent measurement.","entityId":"cw-fb7f8e2ff310021b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","sourceDate":"2022-09-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-194-r389"],"url":"https://museum.vlsi.kr/objects/cw-fb7f8e2ff310021b"},{"id":"cw-fb8ade1a12eb9fc7","name":"P8086-1B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 p8086-1b"],"fields":[{"key":"Model name","value":"AMD P8086-1B","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P8086-1B","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P8086-1B","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P8086","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PDIP-40","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PDIP","unit":"","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8494-r26687","location":"Amd/am8086/p8086-1b · revision 26687 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fb8ade1a12eb9fc7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8494-r26687"],"url":"https://museum.vlsi.kr/objects/cw-fb8ade1a12eb9fc7"},{"id":"cw-fba993cd1b045608","name":"Core i7-6660U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6660u"],"fields":[{"key":"Model name","value":"Core i7-6660U","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6660U","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202499207","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JL","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 20, 2016","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 20, 2016","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 540","unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7841-r25338","location":"Intel/core i7/i7-6660u · revision 25338 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fba993cd1b045608","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7841-r25338","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-fba993cd1b045608"},{"id":"cw-fbbabc5413aeb483","name":"Core i3-9300T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-9300t"],"fields":[{"key":"Model name","value":"Core i3-9300T","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-9300T","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377222","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCZW","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-9000","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":82,"unit":"°C","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-2843-r9541","location":"Intel/core i3/i3-9300t · revision 9541 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-fbbabc5413aeb483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2843-r9541"],"url":"https://museum.vlsi.kr/objects/cw-fbbabc5413aeb483"},{"id":"cw-fbda1db096462556","name":"POWER9 02CY297","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy297"],"fields":[{"key":"Model name","value":"02CY297","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY297","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY297","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.2,"unit":"GHz","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":90,"unit":"W","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":40,"unit":"MiB","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x10 MiB","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3939-r12563","location":"Ibm/power/02cy297 · revision 12563 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-fbda1db096462556","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3939-r12563"],"url":"https://museum.vlsi.kr/objects/cw-fbda1db096462556"},{"id":"cw-fc0b4f1a0ca9c1da","name":"Duron 900 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron d900aut1b"],"fields":[{"key":"Model name","value":"Duron 900","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 900","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D900AUT1B","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0900AUT1B","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2001","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2001","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":39.5,"unit":"W","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8430-r26138","location":"Amd/duron/d900aut1b · revision 26138 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc0b4f1a0ca9c1da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8430-r26138"],"url":"https://museum.vlsi.kr/objects/cw-fc0b4f1a0ca9c1da"},{"id":"cw-fc5c6bbb7ef5e806","name":"Am486DXL2-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dxl2-66"],"fields":[{"key":"Model name","value":"Am486DXL2-66","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DXL2-66","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A8048DXL2-66","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 1993","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DXL2","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8544-r26740","location":"Amd/am486/am486dxl2-66 · revision 26740 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fc5c6bbb7ef5e806","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8544-r26740"],"url":"https://museum.vlsi.kr/objects/cw-fc5c6bbb7ef5e806"},{"id":"cw-fc6eb33b337ab96d","name":"QCS605","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"QCS600","year":2018,"process":"10 nm","aliases":["Qualcomm vision intelligence qcs605"],"fields":[{"key":"Model name","value":"QCS605","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"QCS605","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 11, 2018","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 11, 2018","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vision Intelligence","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"QCS600","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1600,"unit":"MHz","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2500,"unit":"MHz","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 300 Silver","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 300 Gold","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3732","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 615","unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6394-r19877","location":"Qualcomm/vision intelligence/qcs605 · revision 19877 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-13. Not an independent measurement.","entityId":"cw-fc6eb33b337ab96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","sourceDate":"2018-04-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6394-r19877"],"url":"https://museum.vlsi.kr/objects/cw-fc6eb33b337ab96d"},{"id":"cw-fc8f6757f0d98629","name":"Cortex-A510","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2021,"process":"7 nm","aliases":["Arm holdings microarchitectures cortex-a510"],"fields":[{"key":"Architecture name","value":"Cortex-A510","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMIC","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / manufacturer 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 4","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"manufacturer 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 25, 2021","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":6,"unit":"nm","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"In-order","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"3-way","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv9.0","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"0-512 KiB","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A55","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Hayes","unit":"","sourceId":"chipswiki-45-r96985","location":"Arm holdings/microarchitectures/cortex-a510 · revision 96985 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-25. Not an independent measurement.","entityId":"cw-fc8f6757f0d98629","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","sourceDate":"2022-10-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-45-r96985"],"url":"https://museum.vlsi.kr/objects/cw-fc8f6757f0d98629"},{"id":"cw-fcde3046394ec880","name":"CN3830-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3830-600 SCP","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-600 SCP","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-600BG1521-SCP","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8221-r25880","location":"Cavium/octeon/cn3830-600bg1521-scp · revision 25880 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fcde3046394ec880","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8221-r25880","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-fcde3046394ec880"},{"id":"cw-fce3f44a83de7498","name":"Core i5-5350H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5300","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i5 i5-5350h"],"fields":[{"key":"Model name","value":"Intel Core i5-5350H","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-5350H","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802491703","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5300,"unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2BK","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"G0","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7935-r25480","location":"Intel/core i5/i5-5350h · revision 25480 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce3f44a83de7498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7935-r25480","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-fce3f44a83de7498"},{"id":"cw-fce6c360a5d2403f","name":"Athlon MP 1500+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp amp1500dms3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1500+","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1500+","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMP1500DMS3C","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 15, 2001","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 2001","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333,"unit":"MHz","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8458-r26651","location":"Amd/athlon mp/amp1500dms3c · revision 26651 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fce6c360a5d2403f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8458-r26651","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-fce6c360a5d2403f"},{"id":"cw-fcf6bff7f72235e3","name":"A12X Bionic","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2018,"process":"7 nm","aliases":["Apple ax a12x"],"fields":[{"key":"Model name","value":"A12X Bionic","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A12X Bionic","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"T8027","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 30, 2018","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 7, 2018","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.3","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Vortex","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tempest","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chinook","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":10000000000,"unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1236-r3943","location":"Apple/ax/a12x · revision 3943 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-19. Not an independent measurement.","entityId":"cw-fcf6bff7f72235e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","sourceDate":"2020-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1236-r3943"],"url":"https://museum.vlsi.kr/objects/cw-fcf6bff7f72235e3"},{"id":"cw-fd0fb1531b0bdc58","name":"Am486DX2-50","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dx2-50"],"fields":[{"key":"Model name","value":"Am486DX2-50","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-50","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-50","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 1993","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 1993","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8568-r26766","location":"Amd/am486/am486dx2-50 · revision 26766 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd0fb1531b0bdc58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8568-r26766"],"url":"https://museum.vlsi.kr/objects/cw-fd0fb1531b0bdc58"},{"id":"cw-fd1987a464a1bde3","name":"Xeon E5-4620 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4620 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4620 v4","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4620 v4","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002883900","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SJ","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":25,"unit":"MiB","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7715-r25087","location":"Intel/xeon e5/e5-4620 v4 · revision 25087 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd1987a464a1bde3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7715-r25087"],"url":"https://museum.vlsi.kr/objects/cw-fd1987a464a1bde3"},{"id":"cw-fd2532e3b2002426","name":"Ryzen 7 5800","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 5800"],"fields":[{"key":"Model name","value":"Ryzen 7 5800","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5800,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000456","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Vermeer","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":33,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x32 MiB","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-725-r1739","location":"Amd/ryzen 7/5800 · revision 1739 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-fd2532e3b2002426","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-725-r1739"],"url":"https://museum.vlsi.kr/objects/cw-fd2532e3b2002426"},{"id":"cw-fd38c5f44282739b","name":"Bulldozer","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2011,"process":"32 nm","aliases":["Amd microarchitectures bulldozer"],"fields":[{"key":"Architecture name","value":"Bulldozer","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 12, 2011","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K10","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Piledriver","unit":"","sourceId":"chipswiki-2208-r7478","location":"Amd/microarchitectures/bulldozer · revision 7478 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-fd38c5f44282739b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2208-r7478"],"url":"https://museum.vlsi.kr/objects/cw-fd38c5f44282739b"},{"id":"cw-fd3b5f35e01a600d","name":"Atom C3750","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3750"],"fields":[{"key":"Model name","value":"Atom C3750","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3750","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639002","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR385","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":21,"unit":"W","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":448,"unit":"KiB","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x24 KiB","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-1868-r6404","location":"Intel/atom/c3750 · revision 6404 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-fd3b5f35e01a600d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1868-r6404","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-fd3b5f35e01a600d"},{"id":"cw-fd3febbcda2c8ac0","name":"Core i7-9700T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i7 i7-9700t"],"fields":[{"key":"Model name","value":"Core i7-9700T","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-9700T","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403874912","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRG17","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-9000","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":174,"unit":"mm²","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-741-r1767","location":"Intel/core i7/i7-9700t · revision 1767 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-23. Not an independent measurement.","entityId":"cw-fd3febbcda2c8ac0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","sourceDate":"2021-05-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-741-r1767"],"url":"https://museum.vlsi.kr/objects/cw-fd3febbcda2c8ac0"},{"id":"cw-fd4cc26f4cd8aba6","name":"Celeron 877","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 877"],"fields":[{"key":"Model name","value":"Celeron 877","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":877,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148001","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085500","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085501","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FD","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08U","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F8","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0VB","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2012","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2012","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6935-r21622","location":"Intel/celeron/877 · revision 21622 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-fd4cc26f4cd8aba6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6935-r21622","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-fd4cc26f4cd8aba6"},{"id":"cw-fd4d45773fb6d57c","name":"CN5850-1000 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-1000bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5850-1000 NSP","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-1000 NSP","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-1000BG1521-NSP","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8136-r25795","location":"Cavium/octeon plus/cn5850-1000bg1521-nsp · revision 25795 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd4d45773fb6d57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8136-r25795","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-fd4d45773fb6d57c"},{"id":"cw-fd4dc1cd77ce9e65","name":"A12 Bionic","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2018,"architecture":"Vortex","process":"7 nm","aliases":["Apple ax a12"],"fields":[{"key":"Model name","value":"A12 Bionic","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A12 Bionic","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"APL1W81","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"T8020","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 12, 2018","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 21, 2018","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.3","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vortex","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Vortex","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tempest","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chinook","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":6900000000,"unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":83.27,"unit":"mm²","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-618-r1450","location":"Apple/ax/a12 · revision 1450 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-08. Not an independent measurement.","entityId":"cw-fd4dc1cd77ce9e65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","sourceDate":"2021-09-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-618-r1450"],"url":"https://museum.vlsi.kr/objects/cw-fd4dc1cd77ce9e65"},{"id":"cw-fd56c932442751aa","name":"Core i7-4960X Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-4900","year":2013,"architecture":"Ivy Bridge","process":"22 nm","aliases":["Intel core i7ee i7-4960x"],"fields":[{"key":"Model name","value":"Core i7-4960X Extreme Edition","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4960X","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8063301292500","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80633I74960X","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1AS","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2013","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2013","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-4900","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"X79","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ivy Bridge E","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S1","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1860000000,"unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":256.5,"unit":"mm²","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA2011","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":15,"unit":"MiB","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3807-r11897","location":"Intel/core i7ee/i7-4960x · revision 11897 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-fd56c932442751aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3807-r11897"],"url":"https://museum.vlsi.kr/objects/cw-fd56c932442751aa"},{"id":"cw-fd62f68bcb1c04c6","name":"CN3830-400 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-400bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3830-400 NSP","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-400 NSP","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-400BG1521-NSP","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8228-r25887","location":"Cavium/octeon/cn3830-400bg1521-nsp · revision 25887 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd62f68bcb1c04c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8228-r25887","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-fd62f68bcb1c04c6"},{"id":"cw-fd774145ca0d2a04","name":"CN3110-300 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-300bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3110-300 SCP","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-300 SCP","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-300BG868-SCP","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8266-r25926","location":"Cavium/octeon/cn3110-300bg868-scp · revision 25926 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd774145ca0d2a04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8266-r25926","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-fd774145ca0d2a04"},{"id":"cw-fd79721f499c1446","name":"MSM6255A","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2006,"architecture":"ARM9","process":"65 nm","aliases":["Qualcomm msm6xxx msm6255a"],"fields":[{"key":"Model name","value":"Qualcomm MSM6255A","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6255A","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2005,"unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 2006","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":225,"unit":"MHz","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7662-r24925","location":"Qualcomm/msm6xxx/msm6255a · revision 24925 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd79721f499c1446","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7662-r24925"],"url":"https://museum.vlsi.kr/objects/cw-fd79721f499c1446"},{"id":"cw-fd8c5ae45d57c3b6","name":"Xeon Gold 6130","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6130"],"fields":[{"key":"Model name","value":"Xeon Gold 6130","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6130,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736130","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303409000","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B9","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1513-r4965","location":"Intel/xeon gold/6130 · revision 4965 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fd8c5ae45d57c3b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1513-r4965"],"url":"https://museum.vlsi.kr/objects/cw-fd8c5ae45d57c3b6"},{"id":"cw-fd9014c55a9c2ebc","name":"Xeon E5-4655 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4655 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4655 v4","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4655 v4","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002065000","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SH","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x3.75 MiB","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7711-r25082","location":"Intel/xeon e5/e5-4655 v4 · revision 25082 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9014c55a9c2ebc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7711-r25082"],"url":"https://museum.vlsi.kr/objects/cw-fd9014c55a9c2ebc"},{"id":"cw-fd9bfefe72048bbb","name":"QorIQ P1022","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2010,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1022"],"fields":[{"key":"Model name","value":"QorIQ P1022","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1022","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 9, 2009","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2010,"unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1067,"unit":"MHz","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8097-r25756","location":"Freescale/qoriq/p1022 · revision 25756 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA-II","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fd9bfefe72048bbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8097-r25756","chipswiki-31374-r92168"],"url":"https://museum.vlsi.kr/objects/cw-fd9bfefe72048bbb"},{"id":"cw-fda69a0582f14877","name":"Cortex-A76","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2018,"process":"12 nm","aliases":["Arm holdings microarchitectures cortex-a76"],"fields":[{"key":"Architecture name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 31, 2018","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":13,"unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"128-512 KiB","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"0-4 MiB","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A75","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A77","unit":"","sourceId":"chipswiki-926-r2550","location":"Arm holdings/microarchitectures/cortex-a76 · revision 2550 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-17. Not an independent measurement.","entityId":"cw-fda69a0582f14877","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","sourceDate":"2020-10-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-926-r2550"],"url":"https://museum.vlsi.kr/objects/cw-fda69a0582f14877"},{"id":"cw-fda98da270fa53fc","name":"N80L286-12","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80L286","year":1989,"architecture":"80286","aliases":["Amd am286 n80l286-12"],"fields":[{"key":"Model name","value":"N80L286-12","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80L286-12","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N80L286-12","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80L286","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":12.5,"unit":"MHz","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8589-r26787","location":"Amd/am286/n80l286-12 · revision 26787 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fda98da270fa53fc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8589-r26787"],"url":"https://museum.vlsi.kr/objects/cw-fda98da270fa53fc"},{"id":"cw-fe24cdde4415f8ab","name":"Mobile Pentium II 300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1998,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 300"],"fields":[{"key":"Model name","value":"Mobile Pentium II 300","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":300,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80523TX300512","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMD30005002AA","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PME30005002AA","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PME30005001AA","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1998,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 9, 1998","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2RS","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2Y7","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tonga","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":5,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdA0","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdB0","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdB0","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7500000,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":11.1,"unit":"W","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7805-r25244","location":"Intel/mobile pentium ii/300 · revision 25244 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe24cdde4415f8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7805-r25244"],"url":"https://museum.vlsi.kr/objects/cw-fe24cdde4415f8ab"},{"id":"cw-fe28c82c35601ca4","name":"MSM6150","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2004,"architecture":"ARM9","process":"130 nm","aliases":["Qualcomm msm6xxx msm6150"],"fields":[{"key":"Model name","value":"Qualcomm MSM6150","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6150","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 16, 2003","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2004","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":225,"unit":"MHz","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7665-r24931","location":"Qualcomm/msm6xxx/msm6150 · revision 24931 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe28c82c35601ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7665-r24931"],"url":"https://museum.vlsi.kr/objects/cw-fe28c82c35601ca4"},{"id":"cw-fe2c414c496a5c7b","name":"Atom Z625","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z600","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z625"],"fields":[{"key":"Model name","value":"Atom Z625","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z625","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609003987AB","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZD","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z600","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.2,"unit":"W","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8053-r25689","location":"Intel/atom/z625 · revision 25689 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe2c414c496a5c7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8053-r25689","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-fe2c414c496a5c7b"},{"id":"cw-fe3b0bc7254be487","name":"Am186ER–33VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–33vc\\w"],"fields":[{"key":"Model name","value":"Am186ER–33VC\\W","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–33VC\\W","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–33VC\\W","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14642-r44703","location":"Amd/am186ex/am186er–33vc\\w · revision 44703 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-fe3b0bc7254be487","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14642-r44703"],"url":"https://museum.vlsi.kr/objects/cw-fe3b0bc7254be487"},{"id":"cw-fe3f169b55bd2f6f","name":"K6-2/433ADK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-433adk"],"fields":[{"key":"Model name","value":"K6-2/433ADK","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/433ADK","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/433ADK","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":433.33,"unit":"MHz","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8348-r26043","location":"Amd/k6-2/k6-2-433adk · revision 26043 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe3f169b55bd2f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8348-r26043"],"url":"https://museum.vlsi.kr/objects/cw-fe3f169b55bd2f6f"},{"id":"cw-fe4867c9a653d842","name":"Core i7-2740QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2740qm"],"fields":[{"key":"Model name","value":"Core i7-2740QM","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2740QM","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700836100","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR00X","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7876-r25380","location":"Intel/core i7/i7-2740qm · revision 25380 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4867c9a653d842","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7876-r25380","chipswiki-31408-r92251","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-fe4867c9a653d842"},{"id":"cw-fe4fc11473eaae41","name":"Core i7-6500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6500u"],"fields":[{"key":"Model name","value":"Core i7-6500U","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6500U","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201930408","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EZ","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 520","unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7848-r25346","location":"Intel/core i7/i7-6500u · revision 25346 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe4fc11473eaae41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7848-r25346","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-fe4fc11473eaae41"},{"id":"cw-fe5aad934f7f45fd","name":"Am486DX2-80SV8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2S","year":1996,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-80sv8b"],"fields":[{"key":"Model name","value":"Am486DX2-80SV8B","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-80SV8B","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-80SV8B","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1995,"unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1996","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2S","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":80,"unit":"MHz","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am486DX2S","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8561-r26757","location":"Amd/am486/am486dx2-80sv8b · revision 26757 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fe5aad934f7f45fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8561-r26757"],"url":"https://museum.vlsi.kr/objects/cw-fe5aad934f7f45fd"},{"id":"cw-fe669abcc6187602","name":"Xeon W-3265M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3265m"],"fields":[{"key":"Model name","value":"Xeon W-3265M","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3265M","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504248601","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFJ","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1704-r5936","location":"Intel/xeon w/w-3265m · revision 5936 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-fe669abcc6187602","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1704-r5936"],"url":"https://museum.vlsi.kr/objects/cw-fe669abcc6187602"},{"id":"cw-fec37e9fd5723503","name":"Neoverse N1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2019,"process":"7 nm","aliases":["Arm holdings microarchitectures neoverse n1"],"fields":[{"key":"Architecture name","value":"Neoverse N1","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 20, 2019","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":11,"unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"512-1 MiB","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"2-4 MiB","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core duplex","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"core duplex","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cosmos","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Zeus","unit":"","sourceId":"chipswiki-657-r1592","location":"Arm holdings/microarchitectures/neoverse n1 · revision 1592 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-fec37e9fd5723503","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-657-r1592"],"url":"https://museum.vlsi.kr/objects/cw-fec37e9fd5723503"},{"id":"cw-feca9de6bb62f6ea","name":"Alchemy Au1210-400MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1210-400mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1210-400MGD","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1210-400MGD","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1210-400MGD","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1000 mW","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-447-r928","location":"Alchemy/au1210-400mgd · revision 928 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-feca9de6bb62f6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-447-r928"],"url":"https://museum.vlsi.kr/objects/cw-feca9de6bb62f6ea"},{"id":"cw-fed1d088342c876b","name":"Alchemy Au1200-333MGC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-333mgc"],"fields":[{"key":"Model name","value":"Alchemy Au1200-333MGC","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-333MGC","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-333MGC","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2005","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1500 mW","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-458-r939","location":"Alchemy/au1200-333mgc · revision 939 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-fed1d088342c876b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-458-r939"],"url":"https://museum.vlsi.kr/objects/cw-fed1d088342c876b"},{"id":"cw-fef73a022835aba5","name":"Xeon D-2142IT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2142it"],"fields":[{"key":"Model name","value":"Xeon D-2142IT","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2142IT","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303871000","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZZ","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7156-r22589","location":"Intel/xeon d/d-2142it · revision 22589 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-fef73a022835aba5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7156-r22589","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-fef73a022835aba5"},{"id":"cw-fefb26ae13e89d5a","name":"Athlon MP 1200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp ahx1200ans3b"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1200","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1200","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AHX1200ANS3B","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8460-r26653","location":"Amd/athlon mp/ahx1200ans3b · revision 26653 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-fefb26ae13e89d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8460-r26653"],"url":"https://museum.vlsi.kr/objects/cw-fefb26ae13e89d5a"},{"id":"cw-ff09c96e15fafabe","name":"Celeron 807UE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 807ue"],"fields":[{"key":"Model name","value":"Celeron 807UE","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"807UE","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701188200","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0NB","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December, 2011","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2012","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":9.93,"unit":"GiB/s","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6944-r21631","location":"Intel/celeron/807ue · revision 21631 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-ff09c96e15fafabe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6944-r21631","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-ff09c96e15fafabe"},{"id":"cw-ff1444b640032357","name":"CG80286-12","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"CG80286","year":1984,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 cg80286-12"],"fields":[{"key":"Model name","value":"CG80286-12","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CG80286-12","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CG80286","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":12.5,"unit":"MHz","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8601-r26799","location":"Amd/am286/cg80286-12 · revision 26799 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ff1444b640032357","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8601-r26799"],"url":"https://museum.vlsi.kr/objects/cw-ff1444b640032357"},{"id":"cw-ff36c786444f82e8","name":"Skylake (client)","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2015,"process":"14 nm","aliases":["Intel microarchitectures skylake (client)"],"fields":[{"key":"Architecture name","value":"Skylake (client)","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August 5, 2015","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake Y","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Broadwell","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Kaby Lake","unit":"","sourceId":"chipswiki-30-r96959","location":"Intel/microarchitectures/skylake (client) · revision 96959 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-11. Not an independent measurement.","entityId":"cw-ff36c786444f82e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","sourceDate":"2022-11-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-30-r96959"],"url":"https://museum.vlsi.kr/objects/cw-ff36c786444f82e8"},{"id":"cw-ff419465dc41d7dd","name":"Xeon D-2143IT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2143it"],"fields":[{"key":"Model name","value":"Xeon D-2143IT","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2143IT","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303782900","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZU","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7155-r22586","location":"Intel/xeon d/d-2143it · revision 22586 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-ff419465dc41d7dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7155-r22586","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-ff419465dc41d7dd"},{"id":"cw-ffab5aeaa60dae88","name":"Xeon E7-2803","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-2800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-2803"],"fields":[{"key":"Model name","value":"Xeon E7-2803","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-2803","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615006438AB","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-2800","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1733.33,"unit":"MHz","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4.8,"unit":"GT/s","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3M","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":18,"unit":"MiB","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x3 MiB","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7707-r25078","location":"Intel/xeon e7/e7-2803 · revision 25078 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-ffab5aeaa60dae88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7707-r25078","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-ffab5aeaa60dae88"},{"id":"cw-ffe3008dc6635d38","name":"7 Series","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"SiFive","year":2018,"aliases":["Sifive microarchitectures 7 series"],"fields":[{"key":"Architecture name","value":"7 Series","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"SiFive","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 21, 2018","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":2,"unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"RISC-V","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"E76","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"E76-MC","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"S76","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"S76-MC","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"U74","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"U74-MC","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"5 Series","unit":"","sourceId":"chipswiki-4352-r14046","location":"Sifive/microarchitectures/7 series · revision 14046 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-28. Not an independent measurement.","entityId":"cw-ffe3008dc6635d38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","sourceDate":"2018-11-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4352-r14046"],"url":"https://museum.vlsi.kr/objects/cw-ffe3008dc6635d38"},{"id":"cw-fff5076a78ec4a28","name":"Xeon Gold 6128","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6128"],"fields":[{"key":"Model name","value":"Xeon Gold 6128","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6128,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736128","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303592600","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J4","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":115,"unit":"W","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x1 MiB","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1514-r4966","location":"Intel/xeon gold/6128 · revision 4966 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-fff5076a78ec4a28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1514-r4966"],"url":"https://museum.vlsi.kr/objects/cw-fff5076a78ec4a28"},{"id":"dec-alpha-21164","name":"DEC Alpha 21164 (EV5)","kind":"silicon-design","entityType":"silicon-die","subtype":"cpu","company":"Digital Equipment Corporation","year":null,"aliases":["Alpha EV5","21164-CA"],"fields":[{"key":"Visual identification","value":"DEC Alpha 21164 (EV5)","unit":"","sourceId":"commons-alpha-ev5-die","location":"File description","variant":"photographed die","evidenceClass":"third-party-report","note":"Identity follows the Commons file description; this seed does not assert process, area, transistor count, or foundry.","entityId":"dec-alpha-21164","scope":"photographed die","sourceUrl":"https://commons.wikimedia.org/wiki/File:Alpha_EV5_die.JPG","sourceDate":"2013-06-28","retrievedAt":"2026-09-07","researchState":"sourced"}],"sources":["commons-alpha-ev5-die","wikichip-alpha-21164"],"url":"https://museum.vlsi.kr/objects/dec-alpha-21164"},{"id":"document-acorn-assembler-release-2","name":"Acorn Assembler Release 2 — Appendix D, ARM datasheet","kind":"document","entityType":"concept","subtype":"document","company":"Acorn Computers; original manual scan hosted by 4corn","year":null,"aliases":[],"fields":[],"sources":["acorn-assembler-release-2"],"url":"https://museum.vlsi.kr/objects/document-acorn-assembler-release-2"},{"id":"document-amd-3600","name":"AMD Ryzen 5 3600 — Specifications","kind":"document","entityType":"concept","subtype":"document","company":"AMD","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"AMD","sourceId":"amd-3600","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-amd-3600","scope":"concept","sourceUrl":"https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600.html","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["amd-3600"],"url":"https://museum.vlsi.kr/objects/document-amd-3600"},{"id":"document-amd-computex2019","name":"AMD Announces Next-Generation Leadership Products at Computex 2019 Keynote","kind":"document","entityType":"concept","subtype":"document","company":"AMD","year":2019,"aliases":[],"fields":[{"key":"Publisher","value":"AMD","sourceId":"amd-computex2019","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-amd-computex2019","scope":"concept","sourceUrl":"https://www.amd.com/en/newsroom/press-releases/2019-5-26-amd-announces-next-generation-leadership-products.html","sourceDate":"2019-05-26","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["amd-computex2019"],"url":"https://museum.vlsi.kr/objects/document-amd-computex2019"},{"id":"document-amd-zen-architecture-history","name":"AMD Zen Core Architecture","kind":"document","entityType":"concept","subtype":"document","company":"AMD","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"AMD","sourceId":"amd-zen-architecture-history","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-amd-zen-architecture-history","scope":"concept","sourceUrl":"https://www.amd.com/en/technologies/zen-core.html","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["amd-zen-architecture-history"],"url":"https://museum.vlsi.kr/objects/document-amd-zen-architecture-history"},{"id":"document-amd-zen2-hc31","name":"AMD ZEN 2 — Hot Chips 31","kind":"document","entityType":"concept","subtype":"document","company":"AMD / Hot Chips","year":2019,"aliases":[],"fields":[{"key":"Publisher","value":"AMD / Hot Chips","sourceId":"amd-zen2-hc31","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-amd-zen2-hc31","scope":"concept","sourceUrl":"https://old.hotchips.org/hc31/HC31_1.1_AMD_ZEN2.pdf","sourceDate":"2019-08-19","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["amd-zen2-hc31"],"url":"https://museum.vlsi.kr/objects/document-amd-zen2-hc31"},{"id":"document-amd-zen2-isscc-core","name":"Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core","kind":"document","entityType":"concept","subtype":"document","company":"AMD / ISSCC; uploaded by AMD","year":2020,"aliases":[],"fields":[{"key":"Publisher","value":"AMD / ISSCC; uploaded by AMD","sourceId":"amd-zen2-isscc-core","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-amd-zen2-isscc-core","scope":"concept","sourceUrl":"https://www.slideshare.net/slideshow/zen-2-the-amd-7nm-energyefficient-highperformance-x8664-microprocessor-core/229049506","sourceDate":"2020","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["amd-zen2-isscc-core"],"url":"https://museum.vlsi.kr/objects/document-amd-zen2-isscc-core"},{"id":"document-arm-cortex-m3-trm","name":"Cortex-M3 Technical Reference Manual, ARM DDI 0337H","kind":"document","entityType":"concept","subtype":"document","company":"Arm","year":2010,"aliases":[],"fields":[{"key":"Publisher","value":"Arm","sourceId":"arm-cortex-m3-trm","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-arm-cortex-m3-trm","scope":"concept","sourceUrl":"https://documentation-service.arm.com/static/5e8e107f88295d1e18d34714","sourceDate":"2010","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["arm-cortex-m3-trm"],"url":"https://museum.vlsi.kr/objects/document-arm-cortex-m3-trm"},{"id":"document-commons-photo-65929175","name":"NVIDIA GeForce 256 / NV10 — optical die specimen","kind":"document","entityType":"concept","subtype":"document","company":"Wikimedia Commons / Fritzchens Fritz","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"Wikimedia Commons / Fritzchens Fritz","sourceId":"commons-photo-65929175","location":"Document byline or publisher","evidenceClass":"third-party-report","entityId":"document-commons-photo-65929175","scope":"concept","sourceUrl":"https://commons.wikimedia.org/wiki/File:NVIDIA@220nm@Fixed-pipline@NV10@GeForce_256@T5A3202220008_S1_Taiwan_A_Stack-DSC04167-DSC04189_-_ZS-DMap-1_(30217645675).jpg","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["commons-photo-65929175"],"url":"https://museum.vlsi.kr/objects/document-commons-photo-65929175"},{"id":"document-furber-arm-history-1995","name":"Computing without Clocks: Micropipelining the ARM Processor","kind":"document","entityType":"concept","subtype":"document","company":"Steve Furber; Springer-Verlag London (1995); author copy hosted by ResearchGate","year":1995,"aliases":[],"fields":[],"sources":["furber-arm-history-1995"],"url":"https://museum.vlsi.kr/objects/document-furber-arm-history-1995"},{"id":"document-geometry-amd-ccd-isscc2020","name":"AMD Chiplet Architecture for High-Performance Server and Desktop Products","kind":"document","entityType":"concept","subtype":"document","company":"AMD / ISSCC; uploaded by AMD","year":2020,"aliases":[],"fields":[{"key":"Publisher","value":"AMD / ISSCC; uploaded by AMD","sourceId":"geometry-amd-ccd-isscc2020","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-geometry-amd-ccd-isscc2020","scope":"concept","sourceUrl":"https://www.slideshare.net/slideshow/amd-chiplet-architecture-for-highperformance-server-and-desktop-products/229049243","sourceDate":"2020","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["geometry-amd-ccd-isscc2020"],"url":"https://museum.vlsi.kr/objects/document-geometry-amd-ccd-isscc2020"},{"id":"document-gigadevice-gd32f103-datasheet-2-12","name":"GD32F103xx Datasheet, Revision 2.12","kind":"document","entityType":"concept","subtype":"document","company":"GigaDevice","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"GigaDevice","sourceId":"gigadevice-gd32f103-datasheet-2-12","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-gigadevice-gd32f103-datasheet-2-12","scope":"concept","sourceUrl":"https://www.gd32mcu.com/data/documents/datasheet/GD32F103xx_Datasheet_Rev2.12.pdf","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["gigadevice-gd32f103-datasheet-2-12"],"url":"https://museum.vlsi.kr/objects/document-gigadevice-gd32f103-datasheet-2-12"},{"id":"document-gigadevice-gd32f103cbt6","name":"GD32F103CBT6 Product Selector","kind":"document","entityType":"concept","subtype":"document","company":"GigaDevice","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"GigaDevice","sourceId":"gigadevice-gd32f103cbt6","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-gigadevice-gd32f103cbt6","scope":"concept","sourceUrl":"https://www.gigadevice.com/product/mcu/mcus-product-selector/gd32f103cbt6","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["gigadevice-gd32f103cbt6"],"url":"https://museum.vlsi.kr/objects/document-gigadevice-gd32f103cbt6"},{"id":"document-google-tpu-history","name":"TPU transformation: A look back at 10 years of our AI-specialized chips","kind":"document","entityType":"concept","subtype":"document","company":"Google Cloud","year":2024,"aliases":[],"fields":[{"key":"Publisher","value":"Google Cloud","sourceId":"google-tpu-history","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-google-tpu-history","scope":"concept","sourceUrl":"https://cloud.google.com/transform/ai-specialized-chips-tpu-history-gen-ai","sourceDate":"2024-07-31","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["google-tpu-history"],"url":"https://museum.vlsi.kr/objects/document-google-tpu-history"},{"id":"document-google-tpu-v1-explainer","name":"An in-depth look at Google’s first Tensor Processing Unit (TPU)","kind":"document","entityType":"concept","subtype":"document","company":"Google Cloud","year":2017,"aliases":[],"fields":[{"key":"Publisher","value":"Google Cloud","sourceId":"google-tpu-v1-explainer","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-google-tpu-v1-explainer","scope":"concept","sourceUrl":"https://cloud.google.com/blog/products/ai-machine-learning/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu","sourceDate":"2017-05-12","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["google-tpu-v1-explainer"],"url":"https://museum.vlsi.kr/objects/document-google-tpu-v1-explainer"},{"id":"document-google-tpu-v1-isca2017","name":"In-Datacenter Performance Analysis of a Tensor Processing Unit","kind":"document","entityType":"concept","subtype":"document","company":"Norman P. Jouppi et al. / Google; ISCA 2017","year":2017,"aliases":[],"fields":[{"key":"Publisher","value":"Norman P. Jouppi et al. / Google; ISCA 2017","sourceId":"google-tpu-v1-isca2017","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-google-tpu-v1-isca2017","scope":"concept","sourceUrl":"https://arxiv.org/pdf/1704.04760","sourceDate":"2017","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["google-tpu-v1-isca2017"],"url":"https://museum.vlsi.kr/objects/document-google-tpu-v1-isca2017"},{"id":"document-google-tpu-v2-announcement","name":"Build and train machine learning models on our new Google Cloud TPUs","kind":"document","entityType":"concept","subtype":"document","company":"Google","year":2017,"aliases":[],"fields":[{"key":"Publisher","value":"Google","sourceId":"google-tpu-v2-announcement","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-google-tpu-v2-announcement","scope":"concept","sourceUrl":"https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/google-cloud-offer-tpus-machine-learning/","sourceDate":"2017-05-17","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["google-tpu-v2-announcement"],"url":"https://museum.vlsi.kr/objects/document-google-tpu-v2-announcement"},{"id":"document-intel-14nm-disclosure-2014","name":"Intel 14 nm Technology Announcement (2014)","kind":"document","entityType":"concept","subtype":"document","company":"Intel","year":2014,"aliases":["Mark Bohr 14 nm announcement"],"fields":[],"sources":["intel-14nm-disclosure-2014"],"url":"https://museum.vlsi.kr/objects/document-intel-14nm-disclosure-2014"},{"id":"document-intel-8086-ap97a","name":"Memory Component Handbook 1983 — AP-97A","kind":"document","entityType":"concept","subtype":"document","company":"Intel; historical scan hosted by Bitsavers","year":1983,"aliases":[],"fields":[{"key":"Publisher","value":"Intel; historical scan hosted by Bitsavers","sourceId":"intel-8086-ap97a","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-intel-8086-ap97a","scope":"concept","sourceUrl":"https://www.bitsavers.org/components/intel/_dataBooks/1983_Memory_Component_Handbook.pdf","sourceDate":"1983","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["intel-8086-ap97a"],"url":"https://museum.vlsi.kr/objects/document-intel-8086-ap97a"},{"id":"document-intel-8086-ibm-history","name":"The Intel 8086 and the IBM PC","kind":"document","entityType":"concept","subtype":"document","company":"Intel","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"Intel","sourceId":"intel-8086-ibm-history","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-intel-8086-ibm-history","scope":"concept","sourceUrl":"https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-8086-and-the-ibm-pc.html","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["intel-8086-ibm-history"],"url":"https://museum.vlsi.kr/objects/document-intel-8086-ibm-history"},{"id":"document-intel-8086-manual-1979","name":"The 8086 Family Users Manual, October 1979","kind":"document","entityType":"concept","subtype":"document","company":"Intel; historical scan hosted by PUCRS","year":1979,"aliases":[],"fields":[{"key":"Publisher","value":"Intel; historical scan hosted by PUCRS","sourceId":"intel-8086-manual-1979","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-intel-8086-manual-1979","scope":"concept","sourceUrl":"https://www.inf.pucrs.br/~calazans/undergrad/orgcomp_EC/mat_microproc/intel-8086_family_Users_Manual.pdf","sourceDate":"1979-10","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["intel-8086-manual-1979"],"url":"https://museum.vlsi.kr/objects/document-intel-8086-manual-1979"},{"id":"document-intel-8086-manual-1985","name":"iAPX 86/88/186/188 User’s Manual, 210912-001","kind":"document","entityType":"concept","subtype":"document","company":"Intel; historical scan hosted by Bitsavers","year":1985,"aliases":[],"fields":[{"key":"Publisher","value":"Intel; historical scan hosted by Bitsavers","sourceId":"intel-8086-manual-1985","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-intel-8086-manual-1985","scope":"concept","sourceUrl":"https://www.bitsavers.org/components/intel/8086/210912-001_iAPX_86_88_186_188_Users_Manual_1985.pdf","sourceDate":"1985","retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["intel-8086-manual-1985"],"url":"https://museum.vlsi.kr/objects/document-intel-8086-manual-1985"},{"id":"document-intel-quickref","name":"Intel Microprocessor Quick Reference Guide — Product Family","kind":"document","entityType":"concept","subtype":"document","company":"Intel","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"Intel","sourceId":"intel-quickref","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-intel-quickref","scope":"concept","sourceUrl":"https://www.intel.com/pressroom/kits/quickreffam.htm","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["intel-quickref"],"url":"https://museum.vlsi.kr/objects/document-intel-quickref"},{"id":"document-intel-x86-primer","name":"What is x86 Architecture? A Primer to the Foundation of Modern Computing","kind":"document","entityType":"concept","subtype":"document","company":"Intel","year":null,"aliases":[],"fields":[{"key":"Publisher","value":"Intel","sourceId":"intel-x86-primer","location":"Document byline or publisher","evidenceClass":"official-disclosure","entityId":"document-intel-x86-primer","scope":"concept","sourceUrl":"https://www.intel.com/content/www/us/en/newsroom/tech101/client-computing/x86-architecture-foundation-of-modern-computing.html","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["intel-x86-primer"],"url":"https://museum.vlsi.kr/objects/document-intel-x86-primer"}],"sources":[{"id":"intel-quickref","title":"Intel Microprocessor Quick Reference Guide — Product Family","url":"https://www.intel.com/pressroom/kits/quickreffam.htm","publisher":"Intel","accessed":"2026-09-06","evidenceClass":"official-disclosure","originalEvidenceClass":"manufacturer-historical-reference","published":null,"language":"en","type":"documentation","status":"publicly-readable","verificationNote":""},{"id":"amd-3600","title":"AMD Ryzen 5 3600 — Specifications","url":"https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600.html","publisher":"AMD","accessed":"2026-09-06","evidenceClass":"official-disclosure","originalEvidenceClass":"manufacturer-primary","published":null,"language":"en","type":"documentation","status":"publicly-readable","verificationNote":""},{"id":"amd-computex2019","title":"AMD Announces Next-Generation Leadership Products at Computex 2019 Keynote","url":"https://www.amd.com/en/newsroom/press-releases/2019-5-26-amd-announces-next-generation-leadership-products.html","publisher":"AMD","accessed":"2026-09-06","evidenceClass":"official-disclosure","published":"2019-05-26","originalEvidenceClass":"manufacturer-primary","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Third-generation Ryzen family is identified as Zen 2; product table includes Ryzen 5 3600. No financial content used."},{"id":"amd-zen2-hc31","title":"AMD ZEN 2 — Hot Chips 31","url":"https://old.hotchips.org/hc31/HC31_1.1_AMD_ZEN2.pdf","publisher":"AMD / Hot Chips","accessed":"2026-09-06","evidenceClass":"official-disclosure","published":"2019-08-19","originalEvidenceClass":"manufacturer-conference-presentation","language":"en","type":"conference","status":"indexed-excerpt-verified","verificationNote":"Slide 12 indexed original text and visual-element description explicitly show two CCXs per CCD, 16 MB L3 per CCX, and Infinity Fabric die-to-die PHY. Full PDF viewer fails; only retrieved slide evidence used."},{"id":"geometry-amd-ccd-isscc2020","title":"AMD Chiplet Architecture for High-Performance Server and Desktop Products","url":"https://www.slideshare.net/slideshow/amd-chiplet-architecture-for-highperformance-server-and-desktop-products/229049243","publisher":"AMD / ISSCC; uploaded by AMD","published":"2020","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"conference","status":"publicly-readable","verificationNote":"Samuel Naffziger, ISSCC 2020. Original slide 2 and its caption identify CCD and separate client/server I/O dies; no copied diagrams."},{"id":"commons-photo-65929175","title":"NVIDIA GeForce 256 / NV10 — optical die specimen","url":"https://commons.wikimedia.org/wiki/File:NVIDIA@220nm@Fixed-pipline@NV10@GeForce_256@T5A3202220008_S1_Taiwan_A_Stack-DSC04167-DSC04189_-_ZS-DMap-1_(30217645675).jpg","publisher":"Wikimedia Commons / Fritzchens Fritz","published":null,"accessed":"2026-09-06","evidenceClass":"third-party-report","language":"en","type":"photography","status":"publicly-readable","license":"CC0","verificationNote":"Creator caption establishes photographed identity. Existing CC0 rights and original-image records must be retained; no pixels changed by this packet."},{"id":"intel-8086-manual-1979","title":"The 8086 Family Users Manual, October 1979","url":"https://www.inf.pucrs.br/~calazans/undergrad/orgcomp_EC/mat_microproc/intel-8086_family_Users_Manual.pdf","publisher":"Intel; historical scan hosted by PUCRS","published":"1979-10","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"indexed-excerpt-verified","verificationNote":"Publisher and chapter 4 CPU Architecture text verified through indexed primary scan. PDF opens as 208-page image scan; full OCR not available. Group with 1985 manual for conservative derivation budget."},{"id":"intel-8086-manual-1985","title":"iAPX 86/88/186/188 User’s Manual, 210912-001","url":"https://www.bitsavers.org/components/intel/8086/210912-001_iAPX_86_88_186_188_Users_Manual_1985.pdf","publisher":"Intel; historical scan hosted by Bitsavers","published":"1985","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"indexed-excerpt-verified","verificationNote":"8086/8088 CPU, Figures 1-11 and 1-12 indexed text verified; full PDF viewer returned an internal error. Treated as same manual family as 1979 for word-budget audit."},{"id":"intel-8086-ap97a","title":"Memory Component Handbook 1983 — AP-97A","url":"https://www.bitsavers.org/components/intel/_dataBooks/1983_Memory_Component_Handbook.pdf","publisher":"Intel; historical scan hosted by Bitsavers","published":"1983","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"indexed-excerpt-verified","verificationNote":"AP-97A, printed page 3-130, indexed discussion of execution/fetch overlap and wait states verified. Full PDF viewer returned an internal error."},{"id":"intel-8086-ibm-history","title":"The Intel 8086 and the IBM PC","url":"https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-8086-and-the-ibm-pc.html","publisher":"Intel","published":null,"accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":""},{"id":"intel-x86-primer","title":"What is x86 Architecture? A Primer to the Foundation of Modern Computing","url":"https://www.intel.com/content/www/us/en/newsroom/tech101/client-computing/x86-architecture-foundation-of-modern-computing.html","publisher":"Intel","published":null,"accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":""},{"id":"amd-zen2-isscc-core","title":"Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core","url":"https://www.slideshare.net/slideshow/zen-2-the-amd-7nm-energyefficient-highperformance-x8664-microprocessor-core/229049506","publisher":"AMD / ISSCC; uploaded by AMD","published":"2020","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"conference","status":"publicly-readable","verificationNote":"Used original numbered-slide text, not SlideShare AI-enhanced description. Slides 5–10 and 30."},{"id":"amd-zen-architecture-history","title":"AMD Zen Core Architecture","url":"https://www.amd.com/en/technologies/zen-core.html","publisher":"AMD","published":null,"accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Only the explicitly labelled Zen 2 historical subsection is used; current-generation marketing is excluded."},{"id":"gigadevice-gd32f103cbt6","title":"GD32F103CBT6 Product Selector","url":"https://www.gigadevice.com/product/mcu/mcus-product-selector/gd32f103cbt6","publisher":"GigaDevice","published":null,"accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Current SKU specification, not retrospective proof of every 2016 die revision."},{"id":"gigadevice-gd32f103-datasheet-2-12","title":"GD32F103xx Datasheet, Revision 2.12","url":"https://www.gd32mcu.com/data/documents/datasheet/GD32F103xx_Datasheet_Rev2.12.pdf","publisher":"GigaDevice","published":null,"accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Revision deliberately pinned. Device table and sections 3.8–3.10 establish product options, DMA, and pin multiplexing. A newer revision is listed by vendor; no claim that Rev 2.12 is latest."},{"id":"arm-cortex-m3-trm","title":"Cortex-M3 Technical Reference Manual, ARM DDI 0337H","url":"https://documentation-service.arm.com/static/5e8e107f88295d1e18d34714","publisher":"Arm","published":"2010","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Sections 1.5, 3.2, 3.9 and chapter 6; core architectural behavior, not GD32-specific optional implementation guarantees."},{"id":"google-tpu-v1-isca2017","title":"In-Datacenter Performance Analysis of a Tensor Processing Unit","url":"https://arxiv.org/pdf/1704.04760","publisher":"Norman P. Jouppi et al. / Google; ISCA 2017","published":"2017","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"publication","status":"publicly-readable","verificationNote":"Sections 2, 4, 7 and 8; arXiv author paper, 17 pages. Hardware and measurements are first-generation inference TPU scope."},{"id":"google-tpu-v1-explainer","title":"An in-depth look at Google’s first Tensor Processing Unit (TPU)","url":"https://cloud.google.com/blog/products/ai-machine-learning/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu","publisher":"Google Cloud","published":"2017-05-12","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Systolic array and deterministic execution subsections. No modern-TPU specifications imported."},{"id":"google-tpu-history","title":"TPU transformation: A look back at 10 years of our AI-specialized chips","url":"https://cloud.google.com/transform/ai-specialized-chips-tpu-history-gen-ai","publisher":"Google Cloud","published":"2024-07-31","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Main authored text, not Gemini summary. First deployment and v1/v2 scope only."},{"id":"google-tpu-v2-announcement","title":"Build and train machine learning models on our new Google Cloud TPUs","url":"https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/google-cloud-offer-tpus-machine-learning/","publisher":"Google","published":"2017-05-17","accessed":"2026-09-06","evidenceClass":"official-disclosure","language":"en","type":"documentation","status":"publicly-readable","verificationNote":"Establishes second generation and training/inference relationship. No v2 metric assigned to v1."},{"id":"intel-14nm-disclosure-2014","title":"Intel 14 nm Technology Announcement — Mark Bohr, 11 August 2014","url":"https://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf","publisher":"Intel","published":"2014-08-11","accessed":"2026-09-14T17:10:00Z","evidenceClass":"official-disclosure","type":"vendor-presentation","status":"Presentation text checked at PDF pages 14, 15, 23 and 37 (one-based); source linked, slides and photographs not republished."},{"id":"acorn-assembler-release-2","title":"Acorn Assembler Release 2 — Appendix D, ARM datasheet","url":"https://www.4corn.co.uk/archive/docs/Acorn%20Assembler%20Release%202-opt.pdf","publisher":"Acorn Computers; original manual scan hosted by 4corn","published":null,"accessed":"2026-09-07","evidenceClass":"official-disclosure","type":"historical-vendor-manual","status":"Indexed scan text checked at printed p. 191: explicitly ARM2, with reference to VL86C010. Full PDF exceeded browser size limit; publication year not verified."},{"id":"furber-arm-history-1995","title":"Computing without Clocks: Micropipelining the ARM Processor","url":"https://www.researchgate.net/publication/242362827_Computing_without_Clocks_Micropipelining_the_ARM_Processor","publisher":"Steve Furber; Springer-Verlag London (1995); author copy hosted by ResearchGate","published":"1995","accessed":"2026-09-07","evidenceClass":"third-party-report","type":"primary-author-retrospective","status":"Author-uploaded text checked in section 5; uploader attribution to Steve Furber visible. Publisher identity and 1995 date confirmed at https://link.springer.com/chapter/10.1007/978-1-4471-3575-3_5 . Primary participant account, not a contemporaneous release notice. No reuse grant asserted."},{"id":"commons-alpha-ev5-die","title":"File:Alpha EV5 die.JPG","url":"https://commons.wikimedia.org/wiki/File:Alpha_EV5_die.JPG","publisher":"Wikimedia Commons","published":"2013-06-28","accessed":"2026-09-07","evidenceClass":"third-party-report","language":"en","type":"file-record","status":"live-verified","license":"CC BY 3.0","licenseUrl":"https://creativecommons.org/licenses/by/3.0/"},{"id":"wikichip-alpha-21164","title":"File:alpha 21164 die shot.png","url":"https://en.wikichip.org/wiki/File:alpha_21164_die_shot.png","publisher":"WikiChip","published":null,"accessed":"2026-09-07","evidenceClass":"third-party-report","language":"en","type":"file-record","status":"live-verified"},{"id":"chipswiki-451-r932","title":"Alchemy Au1200-500MGD — ChipsWiki, revision 932","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgd&oldid=932","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1200-500mgd"],"contentSha256":"a7bd41a6c339bc3a78ea51832d088e72e2a17d345e1b19114a14a05c588bdca7"},{"id":"chipswiki-458-r939","title":"Alchemy Au1200-333MGC — ChipsWiki, revision 939","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgc&oldid=939","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1200-333mgc"],"contentSha256":"9b3b8c763e0dae7cac3b06f4cabc0c75777a480154e3a06f1c7d4c279ef58827"},{"id":"chipswiki-468-r949","title":"Alchemy Au1100-500MBD — ChipsWiki, revision 949","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbd&oldid=949","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-500mbd"],"contentSha256":"235d91bc23d8a2173d7bf26a5ba2abe9e361a522f342d7bd28ec1b2c900b0ef6"},{"id":"chipswiki-469-r950","title":"Alchemy Au1100-500MBC — ChipsWiki, revision 950","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-500mbc&oldid=950","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-500mbc"],"contentSha256":"c10d1b048784af665a365d127f4de4f267e2c2381235f57c0cb45752eccd3918"},{"id":"chipswiki-471-r952","title":"Alchemy Au1100-400MBC — ChipsWiki, revision 952","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbc&oldid=952","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-400mbc"],"contentSha256":"8164487c96f08324fc2f75f608c4150f76eaecccec89980dca60a24d4f00385f"},{"id":"chipswiki-473-r954","title":"Alchemy Au1100-333MBF — ChipsWiki, revision 954","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbf&oldid=954","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-333mbf"],"contentSha256":"4128d74b33745ae8b38a4b013764b08b5640c68d9d9f8af4d0a3378600083745"},{"id":"chipswiki-485-r969","title":"Alchemy Au1000-500MCC — ChipsWiki, revision 969","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-500mcc&oldid=969","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1000-500mcc"],"contentSha256":"a01b4110ddfc9d7650326d0a7363e60e5595f9d69fb8dc0a6e78f549839e44d8"},{"id":"chipswiki-486-r970","title":"Alchemy Au1000-400MCC — ChipsWiki, revision 970","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-400mcc&oldid=970","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1000-400mcc"],"contentSha256":"ab44ae25525b115a73a5ab1b47d173d0932b5ec8f8481a22c69c69f30dae3f05"},{"id":"chipswiki-573-r1233","title":"ARM3 — ChipsWiki, revision 1233","url":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm3&oldid=1233","publisher":"ChipsWiki / WikiChip contributors","published":"2021-11-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Acorn/microarchitectures/arm3"],"contentSha256":"0a5cf5529fa87bec39721ee49856f6f06186d6a75cc9951194f01a47861b8efe"},{"id":"chipswiki-440-r921","title":"Alchemy Au1250-700MGD — ChipsWiki, revision 921","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-700mgd&oldid=921","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1250-700mgd"],"contentSha256":"80b680479fc7060c4b08123c5d3bdab7ca2075cbdb0270ea371e32e565f8b552"},{"id":"chipswiki-441-r922","title":"Alchemy Au1250-600MGD — ChipsWiki, revision 922","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-600mgd&oldid=922","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1250-600mgd"],"contentSha256":"2caabbd9f2786bd3b4d9552aa565c5e0b435a6e9d47c50a5b395ef44cd9cd4aa"},{"id":"chipswiki-443-r924","title":"Alchemy Au1250-500MGD — ChipsWiki, revision 924","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgd&oldid=924","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1250-500mgd"],"contentSha256":"de7beafb5a60fc0fb8b6aae332803362908d231e54ef93c9e29a7b2c8a620e09"},{"id":"chipswiki-447-r928","title":"Alchemy Au1210-400MGD — ChipsWiki, revision 928","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgd&oldid=928","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1210-400mgd"],"contentSha256":"8b21e35636de6346c9fc7e3f9fbaa52b1b1b17d9314d0fe995574d34e315cf9b"},{"id":"chipswiki-464-r945","title":"Alchemy Au1550-333MBI — ChipsWiki, revision 945","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbi&oldid=945","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1550-333mbi"],"contentSha256":"fe0d6bf367ec542a55f6a8c8c4d4e8eb359295446998ebf67470e6f15383f82d"},{"id":"chipswiki-465-r946","title":"Alchemy Au1550-333MBF — ChipsWiki, revision 946","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbf&oldid=946","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1550-333mbf"],"contentSha256":"f711c00c81c20089275a20253be2fcea44e168636761ae6758969bb12493a2d4"},{"id":"chipswiki-467-r948","title":"Alchemy Au1550-333MBC — ChipsWiki, revision 948","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbc&oldid=948","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1550-333mbc"],"contentSha256":"84a37b46cadb874c56cad95ea7e9b5dfaec8caa6002cce5a16169fd042632381"},{"id":"chipswiki-480-r964","title":"Alchemy Au1500-400MBC — ChipsWiki, revision 964","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbc&oldid=964","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-400mbc"],"contentSha256":"82cfae67275ba25426b4f4e964161ea3048b6d796d945d9a8d8b69bad2a5e160"},{"id":"chipswiki-481-r965","title":"Alchemy Au1500-333MBI — ChipsWiki, revision 965","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbi&oldid=965","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-333mbi"],"contentSha256":"98a08905b0e1afcc8095a74f53a92d88d37b1ae2a6bf883346aaa4daf636b411"},{"id":"chipswiki-482-r966","title":"Alchemy Au1500-333MBF — ChipsWiki, revision 966","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbf&oldid=966","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-333mbf"],"contentSha256":"252e2026da504700c2583dadf9c5111a028d8d502ff48906a88a422d3cd27766"},{"id":"chipswiki-483-r967","title":"Alchemy Au1500-333MBD — ChipsWiki, revision 967","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbd&oldid=967","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-333mbd"],"contentSha256":"7934d2a6ee97ad529c54916d5e566c40adaefbbda08d55d821e2ddf6ecbab8d4"},{"id":"chipswiki-8660-r26859","title":"80186-6/BUC — ChipsWiki, revision 26859","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-buc&oldid=26859","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/80186-6-buc"],"contentSha256":"6064463cdcaf2d9dc3fc0fb22ac52b2fbe8a59b2551a7930fc97f36db33d5cd7"},{"id":"chipswiki-8662-r26861","title":"Am2045B — ChipsWiki, revision 26861","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045b&oldid=26861","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2045b"],"contentSha256":"f0c787d27b5c76e8e83632396e8d75c6759f7ceda75416ccca649de6307fef8d"},{"id":"chipswiki-8665-r26864","title":"Am2029 — ChipsWiki, revision 26864","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2029&oldid=26864","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2029"],"contentSha256":"57ee5c2ff2fb2d67d582f30af4484b23f42e4a4b3b86eaeec26349a1d3be128f"},{"id":"chipswiki-8667-r26866","title":"Am2016 — ChipsWiki, revision 26866","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2016&oldid=26866","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2016"],"contentSha256":"24e8c05192256b0d63898b8de00669245d0cf74be7cfb52c70cd8df693c0ea8c"},{"id":"chipswiki-8635-r26834","title":"MG80186-6 — ChipsWiki, revision 26834","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-6&oldid=26834","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/mg80186-6"],"contentSha256":"7f3aa064c5a4525882015d47fdcf51b2c9a0367853333decf786afd3cb3dca7a"},{"id":"chipswiki-8638-r26837","title":"J80186-3 — ChipsWiki, revision 26837","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-3&oldid=26837","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/j80186-3"],"contentSha256":"a23c8c976af367200f921f43385bc4a9faacbedb438f403cf4e8022d45009331"},{"id":"chipswiki-8647-r26846","title":"IC80186-6 — ChipsWiki, revision 26846","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-6&oldid=26846","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/ic80186-6"],"contentSha256":"0503fce89cb6d852dd87ee294f53a96602c912fed220b50a9cc288b815ad7b6b"},{"id":"chipswiki-8649-r26848","title":"IA80186 — ChipsWiki, revision 26848","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fia80186&oldid=26848","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/ia80186"],"contentSha256":"4cb7c545164abd6b5a591de08ba1c9bcaf403f53570b749d1a09ac5e31b9d8cf"},{"id":"chipswiki-8650-r26849","title":"CG80186-6 — ChipsWiki, revision 26849","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-6&oldid=26849","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/cg80186-6"],"contentSha256":"b71a502bec3f813909ab750aee20f48465441cb71cc8f12bd02435a38ddadca8"},{"id":"chipswiki-8654-r26853","title":"C80186-1 — ChipsWiki, revision 26853","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fc80186-1&oldid=26853","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/c80186-1"],"contentSha256":"2cbc42763fd91e597f10f1eebf7fee5437c502ae19b0e7b7aedac120985d059d"},{"id":"chipswiki-14688-r44749","title":"Am186CC-40KI\\W — ChipsWiki, revision 44749","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40ki%5Cw&oldid=44749","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cc-40ki%5Cw"],"contentSha256":"bbb0cd7a604070f52b49abcba9415b895d31e0d7377498304a7dab54aa85ff11"},{"id":"chipswiki-14691-r44752","title":"Am186CC-25KC\\W — ChipsWiki, revision 44752","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25kc%5Cw&oldid=44752","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cc-25kc%5Cw"],"contentSha256":"47e797da0302c8c95c665d78e993ee7747480cd3368ea2b32bc131e158912f84"},{"id":"chipswiki-14642-r44703","title":"Am186ER–33VC\\W — ChipsWiki, revision 44703","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vc%5Cw&oldid=44703","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9333vc%5Cw"],"contentSha256":"abc07bf5daa37582baa37eb853bec1dc5673eeabc0126853e7866ab052cd6d43"},{"id":"chipswiki-14645-r44706","title":"Am186ER–25VI\\W — ChipsWiki, revision 44706","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vi%5Cw&oldid=44706","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9325vi%5Cw"],"contentSha256":"fabe17d49fb2d1708527f1dbc2c63a4e69d20084c458559bad77dee32a97893b"},{"id":"chipswiki-14646-r44707","title":"Am186ER–25VC\\W — ChipsWiki, revision 44707","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325vc%5Cw&oldid=44707","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9325vc%5Cw"],"contentSha256":"b1b22b8ff85ec820c56bd33a52522f4cdd350adc505b088dc05baa8d81ed4b40"},{"id":"chipswiki-14648-r44709","title":"Am186ER–25KC\\W — ChipsWiki, revision 44709","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325kc%5Cw&oldid=44709","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9325kc%5Cw"],"contentSha256":"0c2e43e76406e3d778c178527abf50ff2e4c23a04e9e63ee5fa3d1191094783c"},{"id":"chipswiki-14650-r44711","title":"Am186EM–40KC\\W — ChipsWiki, revision 44711","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340kc%5Cw&oldid=44711","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9340kc%5Cw"],"contentSha256":"4091dbdd7f50fd4322981358c9aa82a2ce88f688ea165631e3c425d442fa2fb8"},{"id":"chipswiki-14653-r44714","title":"Am186EM–25VC\\W — ChipsWiki, revision 44714","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325vc%5Cw&oldid=44714","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9325vc%5Cw"],"contentSha256":"8506632bc79ca9a7d07ba9f94c3851f5a82339c02a26f846f5bf411a0c5151c9"},{"id":"chipswiki-14654-r44715","title":"Am186EM–25KI\\W — ChipsWiki, revision 44715","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325ki%5Cw&oldid=44715","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9325ki%5Cw"],"contentSha256":"ffef9699867757092a571c4cc44d43307751d96582ed8732dd74d54014356b15"},{"id":"chipswiki-14655-r44716","title":"Am186EM–25KC\\W — ChipsWiki, revision 44716","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9325kc%5Cw&oldid=44716","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9325kc%5Cw"],"contentSha256":"3527531099d354b243299d10ed8edbbc4a7797b1632d6d5ff143382ca8a80ae5"},{"id":"chipswiki-14663-r44724","title":"Am186ED–40VC\\W — ChipsWiki, revision 44724","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340vc%5Cw&oldid=44724","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9340vc%5Cw"],"contentSha256":"6ed868d7d7d8e156f5cae28fe04010b5ef86c6d388936be08400e269d52a3942"},{"id":"chipswiki-14664-r44725","title":"Am186ED–40KC\\W — ChipsWiki, revision 44725","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9340kc%5Cw&oldid=44725","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9340kc%5Cw"],"contentSha256":"513b3c4e0e7dd2cfa4469ec226872ead0f1ee600d12e5ac148f6a987b713f18c"},{"id":"chipswiki-14666-r44727","title":"Am186ED–33KC\\W — ChipsWiki, revision 44727","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333kc%5Cw&oldid=44727","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9333kc%5Cw"],"contentSha256":"e01ab4ab157c1aba5bd937933a99c50570bd9388ef7f8e978de2a92265fd985a"},{"id":"chipswiki-14668-r44729","title":"Am186ED–25KI\\W — ChipsWiki, revision 44729","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325ki%5Cw&oldid=44729","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9325ki%5Cw"],"contentSha256":"cf79da8a77be2ac35fc6ca646fbb9ab250b6e9ae14d27b84ff5cbe89c42b5388"},{"id":"chipswiki-14670-r44731","title":"Am186ED–20VC\\W — ChipsWiki, revision 44731","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320vc%5Cw&oldid=44731","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9320vc%5Cw"],"contentSha256":"f2a8262cc4de4baf323aafe780bb0adb69e15288d052e3d95f374d9f2a4df283"},{"id":"chipswiki-14671-r44732","title":"Am186ED–20KI\\W — ChipsWiki, revision 44732","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320ki%5Cw&oldid=44732","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9320ki%5Cw"],"contentSha256":"6f4f07dfa08eadc6833e2730e30257a542c59835de2f62a5c2c4ec1b9f561843"},{"id":"chipswiki-14673-r44734","title":"Am186EDLV–25VC\\W — ChipsWiki, revision 44734","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325vc%5Cw&oldid=44734","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186edlv%E2%80%9325vc%5Cw"],"contentSha256":"83b59611fc5bcd532e506a681a8fdc47bc3d94f43866070d4ee8ad97e5224a54"},{"id":"chipswiki-14676-r44737","title":"Am186EDLV–20KC\\W — ChipsWiki, revision 44737","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320kc%5Cw&oldid=44737","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186edlv%E2%80%9320kc%5Cw"],"contentSha256":"ce7c75dfb516083b7271227f55178591e864bf7243b3fe1dda71f2380772131d"},{"id":"chipswiki-14678-r44739","title":"Am186CU-40KI\\W — ChipsWiki, revision 44739","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40ki%5Cw&oldid=44739","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cu-40ki%5Cw"],"contentSha256":"a32f16438a2715081600f6d178c666c35f5d64d77b582409133cc18211c48ee9"},{"id":"chipswiki-14682-r44743","title":"Am186CH-50KC\\W — ChipsWiki, revision 44743","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-50kc%5Cw&oldid=44743","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186ch-50kc%5Cw"],"contentSha256":"e4cbc42460007e61dc641264cf6b843021f1977e1cd5982b1c9548039cde462e"},{"id":"chipswiki-14683-r44744","title":"Am186CH-40KI\\W — ChipsWiki, revision 44744","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40ki%5Cw&oldid=44744","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186ch-40ki%5Cw"],"contentSha256":"b0b834110edbfab34d195a91ccebe7e960eaea484f59173e1be8e046617c0978"},{"id":"chipswiki-14684-r44745","title":"Am186CH-40KC\\W — ChipsWiki, revision 44745","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-40kc%5Cw&oldid=44745","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186ch-40kc%5Cw"],"contentSha256":"35b255083a539170cb5de1189e083dc612e15580c810b134256b01d81661485b"},{"id":"chipswiki-14686-r44747","title":"Am186CH-25KC\\W — ChipsWiki, revision 44747","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25kc%5Cw&oldid=44747","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186ch-25kc%5Cw"],"contentSha256":"5ca683d2324c08f8a0155215534c321e248e7e74db0a9cf742599ea360e00fac"},{"id":"chipswiki-8588-r26786","title":"N80L286-16 — ChipsWiki, revision 26786","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-16&oldid=26786","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80l286-16"],"contentSha256":"adb3c2e878c35f3c5eb070f1eb358bef66b5cbc30cfac9348843f8450ae1f26a"},{"id":"chipswiki-8589-r26787","title":"N80L286-12 — ChipsWiki, revision 26787","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-12&oldid=26787","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80l286-12"],"contentSha256":"07b3d121755ad8ed6016d361481b19dc8a8d9f9e62aa1d271f277f614df360a9"},{"id":"chipswiki-8590-r26788","title":"N80L286-10 — ChipsWiki, revision 26788","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-10&oldid=26788","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80l286-10"],"contentSha256":"36b8b68cb9bc3b6605e59c96260750e4e894c2408db889488e29e609766b0d59"},{"id":"chipswiki-8592-r26790","title":"N80C286-20 — ChipsWiki, revision 26790","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-20&oldid=26790","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80c286-20"],"contentSha256":"3b0257d4caa7e752a0924aa10e0a23b6a2456ee2b2a86381c4277bafe3ca6a88"},{"id":"chipswiki-8593-r26791","title":"N80C286-16 — ChipsWiki, revision 26791","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-16&oldid=26791","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80c286-16"],"contentSha256":"86bb2c599f384f2b3998e0ce5ff39a4dfc9c1a24f3b976272f7a9c373761c131"},{"id":"chipswiki-8597-r26795","title":"N80286-16 — ChipsWiki, revision 26795","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80286-16&oldid=26795","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80286-16"],"contentSha256":"d500559eb110166ee93425437133619fe2ba9029c9eb8e0ac5521e005079dc30"},{"id":"chipswiki-8600-r26798","title":"CG80286-8 — ChipsWiki, revision 26798","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-8&oldid=26798","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/cg80286-8"],"contentSha256":"3408970a9ecc863d6d4925607f5e72b8b70636dbd111a7661ae7ef61f4ff6872"},{"id":"chipswiki-8601-r26799","title":"CG80286-12 — ChipsWiki, revision 26799","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-12&oldid=26799","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/cg80286-12"],"contentSha256":"157ab11482bf592095015e3416e7dc8002e045b07c558059af45fa6284655cd5"},{"id":"chipswiki-8605-r26803","title":"C80286-12 — ChipsWiki, revision 26803","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-12&oldid=26803","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/c80286-12"],"contentSha256":"b2149ffaba980e59dc4ac58bd6c60b7e070db0202c74d085619ac3a84f1c2d57"},{"id":"chipswiki-8609-r26807","title":"A80286-16 — ChipsWiki, revision 26807","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-16&oldid=26807","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/a80286-16"],"contentSha256":"b50b3794cbb04aae6cd6e2013ea6890a702bbe149dd18ad50a9b3203b0c0061a"},{"id":"chipswiki-8612-r26810","title":"80286-8/BZC — ChipsWiki, revision 26810","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-bzc&oldid=26810","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/80286-8-bzc"],"contentSha256":"2bd0a1eb3a6af6f2104e9a9d7b34a5192698cc6e11fa4101fdb850bb55c9745d"},{"id":"chipswiki-14620-r44681","title":"Am186ES–33VC\\W — ChipsWiki, revision 44681","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333vc%5Cw&oldid=44681","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9333vc%5Cw"],"contentSha256":"608f14e6a55442232025f5e890928ab2128ef51ac7411b4b281936c251e21791"},{"id":"chipswiki-14625-r44686","title":"Am186ES–20VC\\W — ChipsWiki, revision 44686","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320vc%5Cw&oldid=44686","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9320vc%5Cw"],"contentSha256":"e5fc4700a68dd552d9a5c46001814845e4d34bba4140f81698ac7eae41d5d2fa"},{"id":"chipswiki-14626-r44687","title":"Am186ES–20KI\\W — ChipsWiki, revision 44687","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320ki%5Cw&oldid=44687","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9320ki%5Cw"],"contentSha256":"b96de30e3123c58cfa231cfaab4f73cef7a866ce9ce6ad0dee2847c408a8a2c0"},{"id":"chipswiki-14629-r44690","title":"Am186ESLV–25KC\\W — ChipsWiki, revision 44690","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325kc%5Cw&oldid=44690","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186eslv%E2%80%9325kc%5Cw"],"contentSha256":"13fe0357fc6af43c12f1b469ed70ee97ad3de404eb347fb5c32304cafdce7906"},{"id":"chipswiki-14630-r44691","title":"Am186ESLV–20VC\\W — ChipsWiki, revision 44691","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320vc%5Cw&oldid=44691","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186eslv%E2%80%9320vc%5Cw"],"contentSha256":"9cdcba97f0c1625b1b91b5b74cad6e51ae4cc48a5033c72ecbf9ed85716fb1f4"},{"id":"chipswiki-14631-r44692","title":"Am186ESLV–20KC\\W — ChipsWiki, revision 44692","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9320kc%5Cw&oldid=44692","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186eslv%E2%80%9320kc%5Cw"],"contentSha256":"dd2c4748df49b45c854189245f262c4631b826be98da919dd205c7dd52a7e059"},{"id":"chipswiki-14632-r44693","title":"Am186ER–50VI\\W — ChipsWiki, revision 44693","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vi%5Cw&oldid=44693","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9350vi%5Cw"],"contentSha256":"e93b4ef4eb4bcee480b12d945da92cfbb640ad22c6d02bbb5602d601eacaabd8"},{"id":"chipswiki-14635-r44696","title":"Am186ER–50KI\\W — ChipsWiki, revision 44696","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350ki%5Cw&oldid=44696","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9350ki%5Cw"],"contentSha256":"7c7b44ec9e0df0c503c1e9d14803ce2a91676bffc3bcadaf792c73e710ca3adb"},{"id":"chipswiki-14637-r44698","title":"Am186ER–40VI\\W — ChipsWiki, revision 44698","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vi%5Cw&oldid=44698","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9340vi%5Cw"],"contentSha256":"71421a59d5fa2e01c9051410783c1fdb99e66787373870ef74c65c7637969c91"},{"id":"chipswiki-946-r2646","title":"Am486DX2-66V8B — ChipsWiki, revision 2646","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8b&oldid=2646","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-66v8b"],"contentSha256":"b0842f7cc2c264547600a395aced474ebb465ce0d67808c3cb576143ebca623c"},{"id":"chipswiki-1279-r4217","title":"Am486DX2-80 — ChipsWiki, revision 4217","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80&oldid=4217","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-80"],"contentSha256":"1bf1d969b153640c1711ec2ec38bc9a1780507f1d0647d82a59071cee22efea2"},{"id":"chipswiki-8542-r26738","title":"Am486DXLV-33 — ChipsWiki, revision 26738","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxlv-33&oldid=26738","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dxlv-33"],"contentSha256":"8d6cab575126b5bdb9aaa8bf595f042a93464c4e48373880eed3aab0c89a6d13"},{"id":"chipswiki-8544-r26740","title":"Am486DXL2-66 — ChipsWiki, revision 26740","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-66&oldid=26740","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dxl2-66"],"contentSha256":"4f210b2e0245291c48b0199d56be971f857e77f93cf83f065feac739680fcd8f"},{"id":"chipswiki-8546-r26742","title":"Am486DX4-90NV8T — ChipsWiki, revision 26742","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90nv8t&oldid=26742","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-90nv8t"],"contentSha256":"d1149e5c66ebf834fbc830a0eaa1156bc8561692adfa213dfd621adf73a6001d"},{"id":"chipswiki-8548-r26744","title":"Am486DX4-75SV8B — ChipsWiki, revision 26744","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75sv8b&oldid=26744","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-75sv8b"],"contentSha256":"d070859294df27aaa79b4786f14a148e4f8cb1c41676e7df434e0ea441b334a8"},{"id":"chipswiki-8549-r26745","title":"Am486DX4-75 — ChipsWiki, revision 26745","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-75&oldid=26745","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-75"],"contentSha256":"c3b87d593555080de3e97afb35d6896ea7c9dcbac457b6ff4acaca4ddd62092d"},{"id":"chipswiki-8551-r26747","title":"Am486DX4-120SV8B — ChipsWiki, revision 26747","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120sv8b&oldid=26747","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-120sv8b"],"contentSha256":"8c03dda1d665bc44c8894d3ac00b8a6b400b8df8937b4a840684449d0028118e"},{"id":"chipswiki-8552-r26748","title":"Am486DX4-120NV8T — ChipsWiki, revision 26748","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120nv8t&oldid=26748","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-120nv8t"],"contentSha256":"d4ebb927f4aa568a0c21b0bd5e576606698047096a83a41e1604ef4c7801fc7c"},{"id":"chipswiki-8559-r26755","title":"Am486DX4-100 — ChipsWiki, revision 26755","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100&oldid=26755","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-100"],"contentSha256":"c12404b8749887594fe3b943880401710ec595cefd0088f5b08c56561b87a01b"},{"id":"chipswiki-8560-r26756","title":"Am486DX2-80V8T — ChipsWiki, revision 26756","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80v8t&oldid=26756","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-80v8t"],"contentSha256":"31bd65eabc74f0a44a17cdd6dcca0306d2442580031d0994c2822d5126ee238a"},{"id":"chipswiki-8561-r26757","title":"Am486DX2-80SV8B — ChipsWiki, revision 26757","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80sv8b&oldid=26757","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-80sv8b"],"contentSha256":"be5e0c851dce4b014544297043473db6a747e763ad6e1ce43dd3a4989da03328"},{"id":"chipswiki-8564-r26762","title":"Am486DX2-66V16B — ChipsWiki, revision 26762","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v16b&oldid=26762","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-66v16b"],"contentSha256":"ad1854346d5b8a11194c1061ed29c1a61631dd065754da5a527b851367f8b9cd"},{"id":"chipswiki-8568-r26766","title":"Am486DX2-50 — ChipsWiki, revision 26766","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-50&oldid=26766","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-50"],"contentSha256":"814ef7eef33b946517822fd9e1dc81a9ff0c082c47c1a1e9d79e951d997fab5c"},{"id":"chipswiki-8570-r26768","title":"Am486DX2-100V8B — ChipsWiki, revision 26768","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8b&oldid=26768","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-100v8b"],"contentSha256":"a533c1f2a7c3ed9a57dae4255c083efb570b7082329da474c082d90b6e9f854a"},{"id":"chipswiki-8571-r26769","title":"Am486DX2-100V16B — ChipsWiki, revision 26769","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v16b&oldid=26769","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-100v16b"],"contentSha256":"8b7dd5132de38cb79add778afca9594e42b396a5a7dc8b59f9457d56bd6eac56"},{"id":"chipswiki-8573-r26771","title":"Am486DX-40 — ChipsWiki, revision 26771","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-40&oldid=26771","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx-40"],"contentSha256":"0b6087c5fc1c93ea2edf5406f7af9be09edc943d86b1fe247310bb3675bbd45d"},{"id":"chipswiki-8574-r26772","title":"Am486DX-33 — ChipsWiki, revision 26772","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-33&oldid=26772","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx-33"],"contentSha256":"3053fd6d350d12be467d68a4242d19e7fe743a7f73fb6c4931d6ef774c35d240"},{"id":"chipswiki-791-r1971","title":"AMD-X5-150ADW — ChipsWiki, revision 1971","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adw&oldid=1971","publisher":"ChipsWiki / WikiChip contributors","published":"2021-04-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-150adw"],"contentSha256":"a7749e2f631b62a69dfee4419398b834d638827defebb77505d37e769dc61462"},{"id":"chipswiki-801-r2027","title":"AMD-X5-150ADZ — ChipsWiki, revision 2027","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150adz&oldid=2027","publisher":"ChipsWiki / WikiChip contributors","published":"2021-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-150adz"],"contentSha256":"a98984ec0d8140ed491df44c72486a981aa161160de0dd0213a3e090d2e85df2"},{"id":"chipswiki-8500-r26693","title":"MD8086-2B — ChipsWiki, revision 26693","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2b&oldid=26693","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/md8086-2b"],"contentSha256":"f8dc722913621ede2b606a6778f0b21b667832b541f3f050069dbc7034ea00aa"},{"id":"chipswiki-8504-r26697","title":"J8086-2B — ChipsWiki, revision 26697","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2b&oldid=26697","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/j8086-2b"],"contentSha256":"e9172ac2aa8b015da468463493f62260263b1c133228536eb43ec18bbded6d1f"},{"id":"chipswiki-8508-r26701","title":"J8086 — ChipsWiki, revision 26701","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086&oldid=26701","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/j8086"],"contentSha256":"0c1a522b8d5093a971795cc08b9bfb093fb14d9312794df47a51413df23a1892"},{"id":"chipswiki-8509-r26702","title":"ID8086B — ChipsWiki, revision 26702","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086b&oldid=26702","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/id8086b"],"contentSha256":"5c4135fe6fe5d39d8b569b7780ad985957896889302ee6a2e7ac547d842cdf2f"},{"id":"chipswiki-8511-r26704","title":"ID8086-2 — ChipsWiki, revision 26704","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2&oldid=26704","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/id8086-2"],"contentSha256":"2b8728f43054e67f8460c7560fd5a0e0bfe3f7561d83b452ed5a48d72c96bf1d"},{"id":"chipswiki-8514-r26707","title":"D8086-2B — ChipsWiki, revision 26707","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2b&oldid=26707","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/d8086-2b"],"contentSha256":"f7a7b82ea94acd6cb8ee41f713a3b1b6291e5e195fd3047d2beccd3dd5e2708c"},{"id":"chipswiki-8516-r26709","title":"D8086-1B — ChipsWiki, revision 26709","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1b&oldid=26709","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/d8086-1b"],"contentSha256":"fbd62b2f54f23ba73a2ea0cfeaa7a652b709bb96a8ae6b0d9de0a86ad18ac415"},{"id":"chipswiki-8520-r26713","title":"8086-2/BQA — ChipsWiki, revision 26713","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-2-bqa&oldid=26713","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/8086-2-bqa"],"contentSha256":"a64910acfd1080ceb4cbb0276b4263a76ea3766e83ae9fb4a4506e6de1f8629f"},{"id":"chipswiki-8521-r26714","title":"AMD-X5-160 — ChipsWiki, revision 26714","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-160&oldid=26714","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-160"],"contentSha256":"9f70b35926f1fafde0bd46b010817c71a2c562f31ff62c5e96c30708fd25285b"},{"id":"chipswiki-8522-r26716","title":"AMD-X5-150ADY — ChipsWiki, revision 26716","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-150ady&oldid=26716","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-150ady"],"contentSha256":"8ea242c02a1ba7e1e6e035c1c48b07d81c672231d17e42ab619d76f738ee1853"},{"id":"chipswiki-8523-r26718","title":"AMD-X5-133SFZ — ChipsWiki, revision 26718","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfz&oldid=26718","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-133sfz"],"contentSha256":"4950be5bba5e8ce5b0e2b56e1f1c5bc2c8840d2094b125ec861f896f20483937"},{"id":"chipswiki-8526-r26721","title":"AMD-X5-133SDZ — ChipsWiki, revision 26721","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdz&oldid=26721","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-133sdz"],"contentSha256":"f455740bd19c605b480deca9948dc7e402fa3b93064efe32f5b796b4a2d64e1f"},{"id":"chipswiki-8535-r26731","title":"Am486SXLV-33 — ChipsWiki, revision 26731","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sxlv-33&oldid=26731","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486sxlv-33"],"contentSha256":"e69183586a45db477401978a0b898ae594d3d023a1eae629a0cb1db3fe66e1bf"},{"id":"chipswiki-8537-r26733","title":"Am486SX2-50 — ChipsWiki, revision 26733","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-50&oldid=26733","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486sx2-50"],"contentSha256":"713ef1b62e52bbdf49b1aa0100e9551349248c9da82787a2d7cc5abc6c886289"},{"id":"chipswiki-8539-r26735","title":"Am486SX-33 — ChipsWiki, revision 26735","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-33&oldid=26735","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486sx-33"],"contentSha256":"5ba46c214d1318f180dfb46311d1309ff8c7e3b674d228a941a2d67892b16c07"},{"id":"chipswiki-8540-r26736","title":"Am486SE-33 — ChipsWiki, revision 26736","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-33&oldid=26736","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486se-33"],"contentSha256":"baa0bc2ce0e60930bd5e1c508b6b82c0a6aa5eb7de2b96f34c5caca71857404f"},{"id":"chipswiki-31477-r92441","title":"Template:Packages/amd/socket am4 — revision 92441","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsocket_am4"],"contentSha256":"bb3fd846c7d67fda0ede67b082fec9ef39213f59bdd43493b5cafad816366aa4"},{"id":"chipswiki-8463-r26656","title":"AM9080APCB — ChipsWiki, revision 26656","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apcb&oldid=26656","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080apcb"],"contentSha256":"744603c2e80d3cf94bf06f6c60292a41a48522fbf2b0925d6a92139a6ce36904"},{"id":"chipswiki-8469-r26662","title":"AM9080ADC — ChipsWiki, revision 26662","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adc&oldid=26662","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080adc"],"contentSha256":"8cfbfeef8a2710ed2e82e0b5430ca7c845057657f9b17a7dafa897e408925851"},{"id":"chipswiki-8482-r26675","title":"AM9080A-2DC — ChipsWiki, revision 26675","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dc&oldid=26675","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080a-2dc"],"contentSha256":"4c59b82168181cc93504ddde6fe0b3fda747876aeb871fdbfc1381402ee90773"},{"id":"chipswiki-8483-r26676","title":"AM9080A-2CC — ChipsWiki, revision 26676","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2cc&oldid=26676","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080a-2cc"],"contentSha256":"9259a78dcd62b0d9720f0dcff2ee33a8f716f96ceb9cdb8319f19b53f0078a84"},{"id":"chipswiki-8494-r26687","title":"P8086-1B — ChipsWiki, revision 26687","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1b&oldid=26687","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/p8086-1b"],"contentSha256":"309987b7b64ff373f4e23838c674dedf97b77c429f4ec189e84a5e1a16daa2d6"},{"id":"chipswiki-8495-r26688","title":"P8086-1 — ChipsWiki, revision 26688","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-1&oldid=26688","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/p8086-1"],"contentSha256":"9f2cc4e4bc1d55567fc1848a1ec29f8c554554279ad6df85b0ecdf4bf3096cd5"},{"id":"chipswiki-1384-r4658","title":"Athlon Silver 3050U — ChipsWiki, revision 4658","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20silver%2F3050u&oldid=4658","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_silver/3050u"],"contentSha256":"9d920cef1cf6816b202af05a49a08354e1ff22a9ba59d8ed2197c47abef8325a"},{"id":"chipswiki-8445-r26638","title":"Athlon MP 2800+ — ChipsWiki, revision 26638","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2800dut4c&oldid=26638","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/amsn2800dut4c"],"contentSha256":"13837f4de9d033690480313b50318db187363d15dcb0acf1c88c7f774ea180d0"},{"id":"chipswiki-31459-r92404","title":"Template:Packages/amd/pga-453 — revision 92404","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fpga-453"],"contentSha256":"a86a07f3c6fee4e53da95493f04f69b4e10258066968b6d55bb466dbfa40dd31"},{"id":"chipswiki-8447-r26640","title":"Athlon MP 2600+ — ChipsWiki, revision 26640","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dkt3c&oldid=26640","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/amsn2600dkt3c"],"contentSha256":"9073f6b5a94d8cad36cca63e12e2330de8f136c4f830a37429d08a3ae68f7696"},{"id":"chipswiki-8448-r26641","title":"Athlon MP 2400+ — ChipsWiki, revision 26641","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dut3c&oldid=26641","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/amsn2400dut3c"],"contentSha256":"1c5e8b85606c00785b0ab387850c3611201a7395a7f8789e73d89f8dc472e000"},{"id":"chipswiki-8450-r26643","title":"Athlon MP 2200+ — ChipsWiki, revision 26643","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2200dkt3c&oldid=26643","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/amsn2200dkt3c"],"contentSha256":"3dd790ca72f80414b6f7d769114db16e44969cd929fe43c7c88df169f0db00de"},{"id":"chipswiki-8455-r26648","title":"Athlon MP 1900+ — ChipsWiki, revision 26648","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1900dms3c&oldid=26648","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/amp1900dms3c"],"contentSha256":"b33389ea065ff3da1fb8ad594327817e63ddcfd4c807c090246bb958369e174b"},{"id":"chipswiki-8458-r26651","title":"Athlon MP 1500+ — ChipsWiki, revision 26651","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1500dms3c&oldid=26651","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/amp1500dms3c"],"contentSha256":"73431c8e0268553eb575bf6eafecdcb926efd48de6572a87ae07d0b49c0f63ee"},{"id":"chipswiki-8459-r26652","title":"Athlon MP 1200 — ChipsWiki, revision 26652","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200dhs3c&oldid=26652","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/ahx1200dhs3c"],"contentSha256":"7cee0e648e092938f6a344ed42914f37502bc0175a34d6505dbd8b9a0b55fbdc"},{"id":"chipswiki-8460-r26653","title":"Athlon MP 1200 — ChipsWiki, revision 26653","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ans3b&oldid=26653","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/ahx1200ans3b"],"contentSha256":"fe2df1b0191e88dcaff4737dabe5973e2c2dc908d4ae5151d0427ba02e4b439c"},{"id":"chipswiki-8461-r26654","title":"Athlon MP 1200 — ChipsWiki, revision 26654","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1200ams3c&oldid=26654","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon_mp/ahx1200ams3c"],"contentSha256":"420437ff45dd407e42050148b403c44d11dd11849f66c96fc82d7dac1ac41ddd"},{"id":"chipswiki-31122-r91589","title":"Template:Packages/amd/FT1 — revision 91589","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2FFT1"],"contentSha256":"9cf9c075c04557463591437db38421b5563b3921f20050dc49f4a81372740174"},{"id":"chipswiki-420-r892","title":"Embedded G-Series T44R — ChipsWiki, revision 892","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft44r&oldid=892","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t44r"],"contentSha256":"f2dcdf9e30108c644ed506531bb706c42b7cf865a89320d4cfc7aa3fb07c89bc"},{"id":"chipswiki-423-r895","title":"Embedded G-Series T40E — ChipsWiki, revision 895","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40e&oldid=895","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t40e"],"contentSha256":"f4186cd6930295233fa7d1171e42fb81e59c4b93c2d3536fd9d5ce8fcea6f8bd"},{"id":"chipswiki-425-r897","title":"Embedded G-Series T24L — ChipsWiki, revision 897","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft24l&oldid=897","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t24l"],"contentSha256":"37ba7fe5aced6ae18d1b6a5a0beab1614b5cc9f4562ddbe26920384b94c4f837"},{"id":"chipswiki-426-r898","title":"Embedded G-Series T16R — ChipsWiki, revision 898","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft16r&oldid=898","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t16r"],"contentSha256":"76c467ab0d3fb15d340ca8bcea7827fdb446b616a29dab6b1094e90ca9afcdee"},{"id":"chipswiki-8410-r26118","title":"Duron 1100 (Camaro) — ChipsWiki, revision 26118","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1100ahq1b&oldid=26118","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm1100ahq1b"],"contentSha256":"2c7ebbfd08d8f8bf67ed52c13ffe4c339b8ff6aa859e3f503d9a2a4147f6291d"},{"id":"chipswiki-8414-r26122","title":"Duron 850 (Camaro) — ChipsWiki, revision 26122","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1bm&oldid=26122","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0850avs1bm"],"contentSha256":"7056d15bf583bead7b7e2b6cd1c28fa72b166314c54568fd559b58c10b406671"},{"id":"chipswiki-8415-r26123","title":"Duron 850 (Camaro) — ChipsWiki, revision 26123","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850avs1b&oldid=26123","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0850avs1b"],"contentSha256":"76ca3a460994175d1ba7bd4fb37981562878cbf3a888f72007ed3a1c095bb2ae"},{"id":"chipswiki-8419-r26127","title":"Duron 800 (Camaro) — ChipsWiki, revision 26127","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhg0800avs1b&oldid=26127","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhg0800avs1b"],"contentSha256":"83ca30b96bd9d4089d9740f86ab1395ec20e583181b6da3d4e7cce6e038fa294"},{"id":"chipswiki-8424-r26132","title":"Duron 1400 (Applebred) — ChipsWiki, revision 26132","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1400dlv1c&oldid=26132","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhd1400dlv1c"],"contentSha256":"7e3f154be0259c27d0723a320b59e747091199e38d80bf41e8dc2afeaae6a234"},{"id":"chipswiki-8428-r26136","title":"Duron 1000 (Morgan) — ChipsWiki, revision 26136","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1000amt1b&oldid=26136","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhd1000amt1b"],"contentSha256":"c2b8e9da580f519453ea4f16763ebf11ccf929dc15e177e0e46aacf1032d731d"},{"id":"chipswiki-8429-r26137","title":"Duron 950 (Spitfire) — ChipsWiki, revision 26137","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd950aut1b&oldid=26137","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d950aut1b"],"contentSha256":"37bd5bd4f20e5f5e0c2156456dc0ba99052db00bf8d093e4a21a266db3dba751"},{"id":"chipswiki-8430-r26138","title":"Duron 900 (Spitfire) — ChipsWiki, revision 26138","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd900aut1b&oldid=26138","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d900aut1b"],"contentSha256":"214b9316262799be8519703c9af18c4ff79eadb8a3a74df86c69aceb7081213f"},{"id":"chipswiki-8431-r26139","title":"Duron 850 (Spitfire) — ChipsWiki, revision 26139","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd850aut1b&oldid=26139","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d850aut1b"],"contentSha256":"6b79864794ecfe4cc4aeb7ee80008a0f3aacf25608349913598062ee078f7790"},{"id":"chipswiki-8435-r26143","title":"Duron 750 (Spitfire) — ChipsWiki, revision 26143","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750ast1b&oldid=26143","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d750ast1b"],"contentSha256":"033735cb93ae1eb197d5f1281de5cfd3e6ac6183ae1f5edd1b3e7247a63f8330"},{"id":"chipswiki-8438-r26146","title":"Duron 700 (Spitfire) — ChipsWiki, revision 26146","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700ast1b&oldid=26146","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d700ast1b"],"contentSha256":"463a4171e15af16b6891c35a5f1accfc217b0c1ae41d9312ee76c1fc41d81895"},{"id":"chipswiki-8442-r26150","title":"Duron 600 (Spitfire) — ChipsWiki, revision 26150","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600ast1b&oldid=26150","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d600ast1b"],"contentSha256":"31420a168a0ae1e7b92b1a219f691f512ba1e4128c9f609ee2faac97cc68b998"},{"id":"chipswiki-8443-r26151","title":"Duron 550 (Spitfire) — ChipsWiki, revision 26151","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd550aut1b&oldid=26151","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d550aut1b"],"contentSha256":"1658cbdcd98a85f895f7365f2b92e6b57ebd7306f198df40ee7ad2682a4e4193"},{"id":"chipswiki-417-r889","title":"Embedded G-Series T48N — ChipsWiki, revision 889","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48n&oldid=889","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t48n"],"contentSha256":"3856c0fe0db741a28a08ae8884fddb13a2aeed102b07a1e48bb9b2953876d32c"},{"id":"chipswiki-418-r890","title":"Embedded G-Series T48L — ChipsWiki, revision 890","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48l&oldid=890","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t48l"],"contentSha256":"8d9681a6e27abb0a7ee4adc28c123db9f1df50a1680bc1fbb5c82d164675be3c"},{"id":"chipswiki-31468-r92417","title":"Template:Packages/amd/socket sp3 — revision 92417","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsocket_sp3"],"contentSha256":"aa7769590c72cab44b532bbe05da8b6123f5b0eebea5f7384076e7fe7d710e06"},{"id":"chipswiki-730-r1751","title":"EPYC 7343 — ChipsWiki, revision 1751","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7343&oldid=1751","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7343"],"contentSha256":"85fda6eb24bc3e77a45f16e6f28f2eb95e7270ce04a530de31831ccf5b7ed038"},{"id":"chipswiki-731-r1752","title":"EPYC 7413 — ChipsWiki, revision 1752","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7413&oldid=1752","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7413"],"contentSha256":"990f6c6961ddd99fe1010866d2cc134577e04e89969fc1bf8d295541b7fff2be"},{"id":"chipswiki-732-r1753","title":"EPYC 7443 — ChipsWiki, revision 1753","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443&oldid=1753","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7443"],"contentSha256":"d32e06c6fa226ad27394f4f442f2f1112c12b41afa4148dea60ba7a6c7b6c825"},{"id":"chipswiki-733-r1754","title":"EPYC 7453 — ChipsWiki, revision 1754","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7453&oldid=1754","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7453"],"contentSha256":"3abcc8a1c6f2c64045330feec19c839f833f56170e79cd0e6724c77f9fc88c4a"},{"id":"chipswiki-734-r1755","title":"EPYC 7513 — ChipsWiki, revision 1755","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7513&oldid=1755","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7513"],"contentSha256":"c06f4a477bae4f6b063e4337739461fbc64e9655bbadd82ca97bb74b2022f23c"},{"id":"chipswiki-746-r1787","title":"EPYC 72F3 — ChipsWiki, revision 1787","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F72f3&oldid=1787","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/72f3"],"contentSha256":"1f6425d906ee91f20c7cf84277076d3df1a4e635508f4e8460910971720de796"},{"id":"chipswiki-747-r1788","title":"EPYC 73F3 — ChipsWiki, revision 1788","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F73f3&oldid=1788","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/73f3"],"contentSha256":"9e1758bb28a68d2fe69a1564f2658a5a8bf03418273a44f0d3e86319d20e0869"},{"id":"chipswiki-748-r1789","title":"EPYC 74F3 — ChipsWiki, revision 1789","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F74f3&oldid=1789","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/74f3"],"contentSha256":"84626ee177165d1612590daccd75caef613a5fb4a52e5d2fb49b4d1e7c25e54c"},{"id":"chipswiki-752-r1794","title":"EPYC 7443P — ChipsWiki, revision 1794","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7443p&oldid=1794","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7443p"],"contentSha256":"c9649ef185116f83b81e36c06dc2098fdd07a0e4e3c96305822bc81ad6b04bed"},{"id":"chipswiki-842-r2215","title":"EPYC 7282 — ChipsWiki, revision 2215","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7282&oldid=2215","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7282"],"contentSha256":"16883f8d56a8ce529f41072b766178108fa41fc7d50f5e65791d27530d6e3429"},{"id":"chipswiki-858-r2238","title":"EPYC 7352 — ChipsWiki, revision 2238","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7352&oldid=2238","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7352"],"contentSha256":"d190903b855eb6169c07a1b5e735be08880b2df6f403b0fcc77c0b5c406f9fe9"},{"id":"chipswiki-859-r2239","title":"EPYC 7402 — ChipsWiki, revision 2239","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402&oldid=2239","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7402"],"contentSha256":"e3936d379e6aba6889494ca949782028e4abb1708efd9b37d50a5875cc0b31c3"},{"id":"chipswiki-860-r2240","title":"EPYC 7402P — ChipsWiki, revision 2240","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7402p&oldid=2240","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7402p"],"contentSha256":"ea3e0c0e2000eaa3c66cb3d82be2daafd3fe8d07239de48ec8ed34a6d4bd27a5"},{"id":"chipswiki-863-r2246","title":"EPYC 7502P — ChipsWiki, revision 2246","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502p&oldid=2246","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7502p"],"contentSha256":"7d664cc380c294273abed0140f281183d61a93c7dedee4b889fd91e846494f55"},{"id":"chipswiki-864-r2248","title":"EPYC 7542 — ChipsWiki, revision 2248","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7542&oldid=2248","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7542"],"contentSha256":"e2721fe199986e749b1be0030e2f5cf4e70123e2b3f3f44537e1a92f126604ff"},{"id":"chipswiki-3824-r12077","title":"EPYC 7281 — ChipsWiki, revision 12077","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7281&oldid=12077","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7281"],"contentSha256":"94d9fe6c4bcff96b40061ee6cab25859cdbd697feef433084de7fd7f439fea83"},{"id":"chipswiki-3929-r12499","title":"EPYC 7601 — ChipsWiki, revision 12499","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7601&oldid=12499","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7601"],"contentSha256":"bdef0b6e2e40fc011d490b31c051eeb1eee25db5b2c053c352acb43880c42cad"},{"id":"chipswiki-4493-r14595","title":"EPYC 7261 — ChipsWiki, revision 14595","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7261&oldid=14595","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7261"],"contentSha256":"d8ec1ff7cb38f42d89133e65b88f22ab04d99f27646ce813a4231ccee8b8926e"},{"id":"chipswiki-5072-r16544","title":"EPYC 7351P — ChipsWiki, revision 16544","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351p&oldid=16544","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7351p"],"contentSha256":"e9d35974528355cd4bf0da4a948b3a8e0184617bafa69ba867a6f12207a125a3"},{"id":"chipswiki-5073-r16545","title":"EPYC 7401 — ChipsWiki, revision 16545","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401&oldid=16545","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7401"],"contentSha256":"daf1f4084a848f8e126096b4042748b4254c4b46f81c9f4315da8a831bcc968a"},{"id":"chipswiki-403-r873","title":"EPYC Embedded 3451 — ChipsWiki, revision 873","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3451&oldid=873","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3451"],"contentSha256":"da99f46615bbc2b13b05373b1fb1c32812f0f4253de3b2611d31f44d6c79b943"},{"id":"chipswiki-31097-r91556","title":"Template:Packages/amd/package sp4 — revision 91556","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fpackage_sp4"],"contentSha256":"08de060f40ba925f1f768975406f2684ec6cb2cd6f7e56d153460f19791d76ef"},{"id":"chipswiki-31098-r91557","title":"Template:Packages/amd/package sp4r2 — revision 91557","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fpackage_sp4r2"],"contentSha256":"d173a1f3ea80d3c9a39bec7ff2930b207e4c76d8412350aec84845d5ab185d39"},{"id":"chipswiki-408-r878","title":"EPYC Embedded 3251 — ChipsWiki, revision 878","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3251&oldid=878","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3251"],"contentSha256":"69dde7b3c12213b7403dc4eb8f126eb2252efe69602d342ad42ad403956b3de6"},{"id":"chipswiki-410-r880","title":"EPYC Embedded 3151 — ChipsWiki, revision 880","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3151&oldid=880","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3151"],"contentSha256":"903d89f108074fc5b7db767f7e9d6b56292aff34c6a145eb93bdda7638eb3519"},{"id":"chipswiki-411-r881","title":"EPYC Embedded 3101 — ChipsWiki, revision 881","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3101&oldid=881","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3101"],"contentSha256":"43db2681e61f274b27aaca5fb85485ec4c9d3aa160c1d464e8a0616f9ca25939"},{"id":"chipswiki-868-r2252","title":"EPYC 7702P — ChipsWiki, revision 2252","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702p&oldid=2252","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7702p"],"contentSha256":"2c0d6ecceff8c5931ebe33befada178734f06d781dba77c763d099b240e75f39"},{"id":"chipswiki-869-r2253","title":"EPYC 7742 — ChipsWiki, revision 2253","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7742&oldid=2253","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7742"],"contentSha256":"24a491e276713f0a224e7453e9c35bff6ad7905a93e541fee28a1fa30049d014"},{"id":"chipswiki-31126-r91598","title":"Template:Packages/amd/super socket 7 — revision 91598","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsuper_socket_7"],"contentSha256":"564eb6bed66ec716de2836b472663d3540723b1587ee24b2e0a152705eca610b"},{"id":"chipswiki-994-r2840","title":"K6-2+/475ACZ — ChipsWiki, revision 2840","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-475acz&oldid=2840","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2+-475acz"],"contentSha256":"d43813176c8296b39e0226b92c7f988fc4e9813a9f725d5dd673f28557b47f40"},{"id":"chipswiki-995-r2841","title":"K6-2+/500ACZ — ChipsWiki, revision 2841","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-500acz&oldid=2841","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2+-500acz"],"contentSha256":"a45538674dc43df0c76763a7662878eae489d288ea032c817713f5614b745de2"},{"id":"chipswiki-1195-r3737","title":"EPYC 7F52 — ChipsWiki, revision 3737","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f52&oldid=3737","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7f52"],"contentSha256":"3e6efab4bfd95a17b155082c53c6988eabd1bb82e94371f4ff55c8c367e295b6"},{"id":"chipswiki-1196-r3738","title":"EPYC 7F72 — ChipsWiki, revision 3738","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f72&oldid=3738","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7f72"],"contentSha256":"8f0202d720390fbdcd4059877d880a1fb1c24c02c344557ea88458f7bb59c5a2"},{"id":"chipswiki-8390-r26086","title":"AMD-SSA/5-90ABQ — ChipsWiki, revision 26086","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-90abq&oldid=26086","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-ssa-5-90abq"],"contentSha256":"5110190278094d0fcbe61b28c0476ec156223bf40946ca4cc6fd0e6909f93ed7"},{"id":"chipswiki-8395-r26091","title":"AMD-K5-PR166ABX — ChipsWiki, revision 26091","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abx&oldid=26091","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-k5-pr166abx"],"contentSha256":"6d8d50812114133936e69668a01045b771ed8d8fc02735529e703e7b5842feb7"},{"id":"chipswiki-8398-r26094","title":"AMD-K5-PR150ABR — ChipsWiki, revision 26094","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr150abr&oldid=26094","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-k5-pr150abr"],"contentSha256":"bac18d587a4ba67a6e2b5948fb1b09369ba2a791de279b371fb761b625bc5eab"},{"id":"chipswiki-8400-r26096","title":"AMD-K5-PR133ABQ — ChipsWiki, revision 26096","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abq&oldid=26096","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-k5-pr133abq"],"contentSha256":"98d8a607ac84a6540d87d2393f3896b5a80210fc283174292f2746ab60078083"},{"id":"chipswiki-8401-r26097","title":"AMD-K5-PR120ABR — ChipsWiki, revision 26097","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abr&oldid=26097","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-k5-pr120abr"],"contentSha256":"f1cf685629b9f9aa1670bc3d7358cdb8041d866947dacb83755b7162ed1549f5"},{"id":"chipswiki-8403-r26099","title":"AMD-K5-PR100ABR — ChipsWiki, revision 26099","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abr&oldid=26099","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-k5-pr100abr"],"contentSha256":"0b5bf5760b3ade9f6b97d4f59e16b6510463f8ad1ab9cafb2a48090d4c990325"},{"id":"chipswiki-8404-r26100","title":"AMD-K5-PR100ABQ — ChipsWiki, revision 26100","url":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr100abq&oldid=26100","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k5/amd-k5-pr100abq"],"contentSha256":"f5ecc45a3f7c0f5ccd9035b678be447b312a59c297f1668aa0ce1be57d63ed64"},{"id":"chipswiki-31127-r91599","title":"Template:Packages/amd/OBGA-349 — revision 91599","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2FOBGA-349"],"contentSha256":"109f330b924e1969cc2d8e580bc51ed3a4db79c39e1e9382893f2d98b474884b"},{"id":"chipswiki-1002-r2853","title":"K6-2E+/400ATZ — ChipsWiki, revision 2853","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400atz&oldid=2853","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2e+-400atz"],"contentSha256":"c9d43dd7ba4d5db8f595fc472d4f2d6d0444f3d73b3f431d34fae82708154f74"},{"id":"chipswiki-1005-r2856","title":"K6-2E+/450ACR — ChipsWiki, revision 2856","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450acr&oldid=2856","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2e+-450acr"],"contentSha256":"b6292d8dde89d6cf7dc2894831555ad4d325cc45e71a4b754ecf7946cfd81778"},{"id":"chipswiki-1007-r2858","title":"K6-2E+/450ICR — ChipsWiki, revision 2858","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450icr&oldid=2858","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2e+-450icr"],"contentSha256":"a268c886dcff7ce1e41644c821f67a10e9ecff838562019d85f4f21de46e8ab1"},{"id":"chipswiki-1008-r2859","title":"K6-2E+/500ACR — ChipsWiki, revision 2859","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-500acr&oldid=2859","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2e+-500acr"],"contentSha256":"706c565f66551e2c24cd5dd6627cb0cbc75af6a97b6bdf6d2a020dce98e59e3b"},{"id":"chipswiki-8354-r26049","title":"K6-2/400AFQ — ChipsWiki, revision 26049","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq&oldid=26049","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-400afq"],"contentSha256":"9c050cd88224ae76e2c7611a647ffa0343ea41b73dce1bc44b12784368751f7a"},{"id":"chipswiki-8355-r26050","title":"K6-2/400AFK-66 — ChipsWiki, revision 26050","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk-66&oldid=26050","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-400afk-66"],"contentSha256":"429eab487fee96beba0cf520437b1a34623ba08411c1a816950dc778de29b7b4"},{"id":"chipswiki-8358-r26053","title":"K6-2/400ACK — ChipsWiki, revision 26053","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack&oldid=26053","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-400ack"],"contentSha256":"290748e0ecace44f95a380f2cc0c0614e1da9137d50a334dd4279a977ccd569b"},{"id":"chipswiki-8364-r26059","title":"K6-2/350AFR — ChipsWiki, revision 26059","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afr&oldid=26059","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-350afr"],"contentSha256":"738b21e576b94da06343ab7233d7a6040987ff9630028c065194c2cb596ef8a8"},{"id":"chipswiki-8365-r26060","title":"K6-2/350AFQ — ChipsWiki, revision 26060","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afq&oldid=26060","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-350afq"],"contentSha256":"1029f0ee7ebcb6cf850f5ac47786a43261b011189ba56225dd2db8fbb7294e51"},{"id":"chipswiki-8366-r26061","title":"K6-2/350AFK — ChipsWiki, revision 26061","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-350afk&oldid=26061","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-350afk"],"contentSha256":"fdc32f06c50455e389999ccf2a088708bb87dc5156b2ce5734fc6c00d135ff8b"},{"id":"chipswiki-8368-r26063","title":"AMD-K6-2/333BNZ-66 — ChipsWiki, revision 26063","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz-66&oldid=26063","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-333bnz-66"],"contentSha256":"f4b41f37fce8fbbb10853487d3efd6b03120e70a10f8acf4e2a44876f8a88abf"},{"id":"chipswiki-8369-r26064","title":"AMD-K6-2/333BNZ — ChipsWiki, revision 26064","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333bnz&oldid=26064","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-333bnz"],"contentSha256":"5e3944ff38e20e163f44d74157a0b913f050c21f3e4c3178f282bda70098722c"},{"id":"chipswiki-8370-r26065","title":"AMD-K6-2/333ANZ-66 — ChipsWiki, revision 26065","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz-66&oldid=26065","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-333anz-66"],"contentSha256":"4a55aac67208ac08a5aa34a97095c0389bf844901a4e04769ec4cb71cefb1751"},{"id":"chipswiki-8375-r26070","title":"K6-2/333AFR — ChipsWiki, revision 26070","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr&oldid=26070","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-333afr"],"contentSha256":"c9d6491fa301a9e3a2218cad05bc77d2869c3691f83f92a0cc452436eb6d4d08"},{"id":"chipswiki-8378-r26073","title":"AMD-K6-2/300ANZ-66 — ChipsWiki, revision 26073","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz-66&oldid=26073","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-300anz-66"],"contentSha256":"331f1ed491f562ae5546991559bd6bc4d163a6d7dbb639eb834d6f853085791a"},{"id":"chipswiki-8379-r26074","title":"AMD-K6-2/300ANZ — ChipsWiki, revision 26074","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300anz&oldid=26074","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-300anz"],"contentSha256":"a7f4d69a31dd2c7f2add68063c6ea35612b84d769d7bd6d107560716c5991d98"},{"id":"chipswiki-8383-r26078","title":"AMD-K6-2/266BNZ — ChipsWiki, revision 26078","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266bnz&oldid=26078","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-266bnz"],"contentSha256":"903c25a51b68b8c89c1d5b5d85a9011e016ca3d48a331c9848bbf5b4048872d0"},{"id":"chipswiki-8385-r26080","title":"AMD-K6-2/266AMZ — ChipsWiki, revision 26080","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266amz&oldid=26080","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-266amz"],"contentSha256":"e905be975d383120429fdbede56fe0c6cd077505140e184567f5716af3652b89"},{"id":"chipswiki-8387-r26082","title":"K6-2/250AFR — ChipsWiki, revision 26082","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-250afr&oldid=26082","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-250afr"],"contentSha256":"effd8005013ba425f3aaad26d82fd65fd27baf5591beb5fa3fd788bce72f8d73"},{"id":"chipswiki-8389-r26084","title":"K6-2/233AFR — ChipsWiki, revision 26084","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233afr&oldid=26084","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-233afr"],"contentSha256":"9d4c4937173314d596a688866f8a7f305efa270e8ce7b8c8bf25fe11dd5bad46"},{"id":"chipswiki-1009-r2860","title":"AMD-K6-IIIE+/400ICR — ChipsWiki, revision 2860","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400icr&oldid=2860","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii+/amd-k6-iiie+-400icr"],"contentSha256":"abaeea91500cb13aaa09f7c7d51a4c63c017b1b96e536fef2ab1fe82137b7bcc"},{"id":"chipswiki-8309-r25999","title":"AMD-K6-III/350AFK — ChipsWiki, revision 25999","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-350afk&oldid=25999","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii-p/amd-k6-iii-350afk"],"contentSha256":"3d62cc1f97861ad33904479d658547594959e49eeedea37bb9f6a8dd9737687f"},{"id":"chipswiki-8310-r26000","title":"AMD-K6-III/333AFK — ChipsWiki, revision 26000","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-333afk&oldid=26000","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii-p/amd-k6-iii-333afk"],"contentSha256":"10ab1e36dc2a4b45509edb182cf8b63c7ffb340d6ce83a5abad315b0012be3ab"},{"id":"chipswiki-8311-r26001","title":"AMD-K6-IIIE+/550ACR — ChipsWiki, revision 26001","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-550acr&oldid=26001","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii+/amd-k6-iiie+-550acr"],"contentSha256":"07ffc08fbed2afbcc7c477351eb16f55ccf022fd7a3055b33fde5ebcdaa793ea"},{"id":"chipswiki-8314-r26004","title":"AMD-K6-IIIE+/450APZ — ChipsWiki, revision 26004","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450apz&oldid=26004","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii+/amd-k6-iiie+-450apz"],"contentSha256":"dd6def8d2275d77a586ee812d3a0c8b3bf4a6ddf0ac3e5d5060d4e4b13476522"},{"id":"chipswiki-8322-r26017","title":"K6-2E/333AFR-66 — ChipsWiki, revision 26017","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr-66&oldid=26017","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2e-333afr-66"],"contentSha256":"2e3ab8340bb139ed1cffbcd84c8914b9bc2d98b93ace5371c919d4ead9e7cf77"},{"id":"chipswiki-8324-r26019","title":"K6-2E/300AMZ-66 — ChipsWiki, revision 26019","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz-66&oldid=26019","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2e-300amz-66"],"contentSha256":"d92b39318affc3a66b20e1ed273f54bac1b8365ed7d307cb7526ae845fa54399"},{"id":"chipswiki-8325-r26020","title":"K6-2E/300AMZ — ChipsWiki, revision 26020","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300amz&oldid=26020","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2e-300amz"],"contentSha256":"0b71dfd75775b49cf7959e2c71c4476516a8d6f471548e0bdb28a9de6654dd8a"},{"id":"chipswiki-8327-r26022","title":"K6-2E/300AFR — ChipsWiki, revision 26022","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr&oldid=26022","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2e-300afr"],"contentSha256":"08d309bc2191e6b48b1afea95d520ff558877ff214b95240ce95311000891bff"},{"id":"chipswiki-8328-r26023","title":"K6-2E/266AMZ — ChipsWiki, revision 26023","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266amz&oldid=26023","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2e-266amz"],"contentSha256":"e771ba1e273625ce897498d74f41ade5558baaa875ccba251484067e975a73df"},{"id":"chipswiki-8330-r26025","title":"K6-2E/233AMZ — ChipsWiki, revision 26025","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233amz&oldid=26025","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2e-233amz"],"contentSha256":"95936ffb672581d3e1c621935d37b98110a3f92ed3ac87da51fc155c17696188"},{"id":"chipswiki-8333-r26028","title":"K6-2/550AFX — ChipsWiki, revision 26028","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550afx&oldid=26028","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-550afx"],"contentSha256":"710d129670dbaefd8257d858c11c16934c1d0d46a01dd7a8ab47ff2c3f16e5e2"},{"id":"chipswiki-8340-r26035","title":"K6-2/475AFX — ChipsWiki, revision 26035","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475afx&oldid=26035","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-475afx"],"contentSha256":"ff0e362eb44bf3a7c934166805780f0e1ce13a001acb8eef8ceeff0501474eb4"},{"id":"chipswiki-8342-r26037","title":"K6-2/475ACK — ChipsWiki, revision 26037","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475ack&oldid=26037","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-475ack"],"contentSha256":"dd65f6fa9931349b77a0c24ad0afac76fdd19863e2ba9f8cdf6b8f972d0e53a6"},{"id":"chipswiki-8343-r26038","title":"K6-2/450AHX — ChipsWiki, revision 26038","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ahx&oldid=26038","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-450ahx"],"contentSha256":"26d8ceefd1832fe0479632256bfec729607496b348943464874283995ff027a4"},{"id":"chipswiki-8344-r26039","title":"K6-2/450AGX — ChipsWiki, revision 26039","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450agx&oldid=26039","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-450agx"],"contentSha256":"5d46a111a0f9f162d7d3479019fad2407cb37387bb082276843efc177e3a7274"},{"id":"chipswiki-8347-r26042","title":"K6-2/450ACK — ChipsWiki, revision 26042","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450ack&oldid=26042","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-450ack"],"contentSha256":"d798f2c92704b51d40937d0c1fe528cc70197c14822afce72920d083627f9621"},{"id":"chipswiki-8348-r26043","title":"K6-2/433ADK — ChipsWiki, revision 26043","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-433adk&oldid=26043","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-433adk"],"contentSha256":"02da9468824980c0d9e9c9a3a9a780e85d4044e524cfdbc6605549e50b66ea62"},{"id":"chipswiki-8349-r26044","title":"K6-2/400AHX-66 — ChipsWiki, revision 26044","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx-66&oldid=26044","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-400ahx-66"],"contentSha256":"c24621274e470aed0ffcf22ee31c0c1678d7eec66a2677884368e4ba24452beb"},{"id":"chipswiki-8351-r26046","title":"K6-2/400AFR-66 — ChipsWiki, revision 26046","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr-66&oldid=26046","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-400afr-66"],"contentSha256":"82217d9823e2deac49fbc29559f2562fba4049120e5b2d68f6053e7c27456df9"},{"id":"chipswiki-667-r1613","title":"Piledriver — ChipsWiki, revision 1613","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpiledriver&oldid=1613","publisher":"ChipsWiki / WikiChip contributors","published":"2021-07-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/piledriver"],"contentSha256":"cc29a460c490011459d29cdae485ca295a9eee9b2105fe424e3a8c9318964af5"},{"id":"chipswiki-1012-r2863","title":"AMD-K6/300BDZ — ChipsWiki, revision 2863","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300bdz&oldid=2863","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6/300bdz"],"contentSha256":"82a5d24f02384af9fef98d27b9124a43fb2286c8b539fb13ab5668c8076d6ebe"},{"id":"chipswiki-31128-r91600","title":"Template:Packages/amd/CBGA-360 — revision 91600","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2FCBGA-360"],"contentSha256":"73c836a599292c8c5ceaff2b06655c858c4ef357aeab13613fcd5150c2a813b2"},{"id":"chipswiki-1014-r2865","title":"AMD-K6/266BCZ — ChipsWiki, revision 2865","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266bcz&oldid=2865","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6/266bcz"],"contentSha256":"5557f1ef7b098773853aafc0de126000654b2d58d7cdcc83a480ebb4cf3766ff"},{"id":"chipswiki-1080-r3147","title":"Vega — ChipsWiki, revision 3147","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvega&oldid=3147","publisher":"ChipsWiki / WikiChip contributors","published":"2020-06-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/vega"],"contentSha256":"df300c264078742ebda338d161255159e4ae3a7e99d92876a10db15f754f759a"},{"id":"chipswiki-2208-r7478","title":"Bulldozer — ChipsWiki, revision 7478","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fbulldozer&oldid=7478","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/bulldozer"],"contentSha256":"547f1162de2c0f75e84d587060bc87bcdb8d4c171a0786886bdd89e20043b4bf"},{"id":"chipswiki-2222-r7535","title":"Navi — ChipsWiki, revision 7535","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fnavi&oldid=7535","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/navi"],"contentSha256":"44a7547a7dfcb167d3c9a59f0b46bee1396ceb64ae60b8d07a4becf2abb22a21"},{"id":"chipswiki-4499-r14625","title":"AMD-K6-III/450ACK — ChipsWiki, revision 14625","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-450ack&oldid=14625","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii-p/amd-k6-iii-450ack"],"contentSha256":"65a1edfbdab804fbb94660d093086cef52e625d6443e021324f1045ee3c79bc4"},{"id":"chipswiki-5201-r17060","title":"Excavator — ChipsWiki, revision 17060","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fexcavator&oldid=17060","publisher":"ChipsWiki / WikiChip contributors","published":"2018-07-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/excavator"],"contentSha256":"37de9e0c97a6f6c8998d04d2567bcc0c12a0b2ed5d3c29b3fffb45727f84cf4d"},{"id":"chipswiki-7326-r23574","title":"Steamroller — ChipsWiki, revision 23574","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsteamroller&oldid=23574","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/steamroller"],"contentSha256":"da3a18ee1f873f7062856b9bcbb76ae9d2bc58bf00d6f3f096164e2f8d8578c2"},{"id":"chipswiki-8291-r25979","title":"AMD-K6/PR2-200ALR — ChipsWiki, revision 25979","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-200alr&oldid=25979","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6-pr2-200alr"],"contentSha256":"460b2b98488f97b27d530bbb7a2c8d392835c62822211e7b8261b0b6f8e8cdb9"},{"id":"chipswiki-8292-r25980","title":"AMD-K6/PR2-166ALR — ChipsWiki, revision 25980","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-pr2-166alr&oldid=25980","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6-pr2-166alr"],"contentSha256":"98965db36be04d9c8a8f7e0b7e0f16dc3c7af8db1247bc352657f00821a95687"},{"id":"chipswiki-8295-r25983","title":"AMD-K6-233AFR — ChipsWiki, revision 25983","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233afr&oldid=25983","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6-233afr"],"contentSha256":"cd51564bd39d36ff9551fb477131f6c944e07269459734a7417e3b9e02fc39a7"},{"id":"chipswiki-8297-r25986","title":"AMD-K6-200AFR — ChipsWiki, revision 25986","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200afr&oldid=25986","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6-200afr"],"contentSha256":"e42cd880716f4121ac8e4cd6687d00d96eaab4d204ba063ccf7d7c2dab171315"},{"id":"chipswiki-8299-r25988","title":"AMD-K6-166ALR — ChipsWiki, revision 25988","url":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alr&oldid=25988","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6/amd-k6-166alr"],"contentSha256":"0d12a80d09b64973556f01638377afb69788d9702da2e058341c183192e20464"},{"id":"chipswiki-8300-r25989","title":"AMD-K6-III/450AHX — ChipsWiki, revision 25989","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450ahx&oldid=25989","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii/amd-k6-iii-450ahx"],"contentSha256":"54b343737568d1366756917e1f7f28e5cd70a2d00cb622af872ea464a2b41c73"},{"id":"chipswiki-8301-r25990","title":"AMD-K6-III/450AFX — ChipsWiki, revision 25990","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-450afx&oldid=25990","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii/amd-k6-iii-450afx"],"contentSha256":"52187551d8e0e318202854ab7dd845d72b6aac09aa2382ae2e5e59f7b75ef522"},{"id":"chipswiki-8304-r25993","title":"AMD-K6-III/333AFR — ChipsWiki, revision 25993","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-333afr&oldid=25993","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-iii/amd-k6-iii-333afr"],"contentSha256":"8802b5c65c5f36e636106dc9037b749d2385f659bb391f57428bb278ffc65dcd"},{"id":"chipswiki-76-r97029","title":"Zen 3 — ChipsWiki, revision 97029","url":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%203&oldid=97029","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/microarchitectures/zen_3"],"contentSha256":"25d923a33bf5040539cbf4d6583b4fc61486dc85e7915ae346cbdbcf581f3802"},{"id":"chipswiki-31113-r91580","title":"Template:Packages/amd/SP1 — revision 91580","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2FSP1"],"contentSha256":"8806409cd3de53d8bc1e99742ce2afe1843367aceb76627111f014c71d433334"},{"id":"chipswiki-957-r2707","title":"Opteron A1170 — ChipsWiki, revision 2707","url":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1170&oldid=2707","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/opteron/a1170"],"contentSha256":"b18a064dd57aacb8d6f3625ecd6928bb09658acfd1d1e1b0f0eb65ca521d1bb8"},{"id":"chipswiki-611-r1433","title":"Ryzen 3 PRO 5350GE — ChipsWiki, revision 1433","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350ge&oldid=1433","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_5350ge"],"contentSha256":"ecc6e9f728b543a66c5f56c702d1da1c7f0edc82b18a62081fe7b8c4df47196c"},{"id":"chipswiki-612-r1434","title":"Ryzen 3 PRO 5350G — ChipsWiki, revision 1434","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205350g&oldid=1434","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_5350g"],"contentSha256":"60f7f75c396c1a1116c5f6c404fce9dbef52ab9a557cadcc75c61d0e641c3a89"},{"id":"chipswiki-634-r1530","title":"Ryzen 3 4300GE — ChipsWiki, revision 1530","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300ge&oldid=1530","publisher":"ChipsWiki / WikiChip contributors","published":"2021-08-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/4300ge"],"contentSha256":"948f118afdcd55852020e0e09e06bfd8e841419c088f80e16cee2b1f44df732d"},{"id":"chipswiki-689-r1683","title":"Ryzen 3 4300U — ChipsWiki, revision 1683","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300u&oldid=1683","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/4300u"],"contentSha256":"74bffe2ccb4f1c133f91eceb341128f0c351491f98c388a50aac0926d82fc3bf"},{"id":"chipswiki-690-r1684","title":"Ryzen 3 PRO 4450U — ChipsWiki, revision 1684","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204450u&oldid=1684","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_4450u"],"contentSha256":"e782dffa2bc0c909ef677bb738a5c9f1ebfbb7ffbb23241cb9131f40707b1dfd"},{"id":"chipswiki-708-r1714","title":"Ryzen 3 5300GE — ChipsWiki, revision 1714","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300ge&oldid=1714","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/5300ge"],"contentSha256":"3c41dee17671851172aed0f32d88c3ae6eeea4fed4731b16aa42c697b57cc742"},{"id":"chipswiki-710-r1716","title":"Ryzen 3 5400U — ChipsWiki, revision 1716","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5400u&oldid=1716","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/5400u"],"contentSha256":"9a3f4996525bd3bc39e4293b3072781ba8c6e1162908507394caef06704b9012"},{"id":"chipswiki-711-r1717","title":"Ryzen 3 PRO 5450U — ChipsWiki, revision 1717","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%205450u&oldid=1717","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_5450u"],"contentSha256":"24c6823e7d36d1377a3c1401a2149934b57886c653fed3c2184d828f31aad97d"},{"id":"chipswiki-31111-r91577","title":"Template:Packages/amd/socket fp5 — revision 91577","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsocket_fp5"],"contentSha256":"c2f29e9f0176b46048287e29b520e99aedf0680c24c8c0ba08c308912e036b53"},{"id":"chipswiki-1554-r5095","title":"Ryzen 3 PRO 3200G — ChipsWiki, revision 5095","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200g&oldid=5095","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_3200g"],"contentSha256":"64273bcce3f068d99809b6caecc7cbaf5bd35a3e710f15df89c8354031efcdc6"},{"id":"chipswiki-2186-r7377","title":"Ryzen 3 PRO 3300U — ChipsWiki, revision 7377","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203300u&oldid=7377","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_3300u"],"contentSha256":"7f30a974ed93863941baebc61950d096319491b739777ef5c19a88a0d09788e5"},{"id":"chipswiki-4910-r15839","title":"Ryzen 3 PRO 2200G — ChipsWiki, revision 15839","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200g&oldid=15839","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_2200g"],"contentSha256":"a96d01a5cff9d2ca676fa616b6be28c7560e204e06cede8d9bcfd556681ddaf5"},{"id":"chipswiki-7355-r23750","title":"Ryzen 3 PRO 1300 — ChipsWiki, revision 23750","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201300&oldid=23750","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_1300"],"contentSha256":"bf038ea119a442f53b55aab92ed0f04075aa5f612bbaa23af387e8a8012fd389"},{"id":"chipswiki-181-r351","title":"Ryzen 5 4600GE — ChipsWiki, revision 351","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600ge&oldid=351","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/4600ge"],"contentSha256":"1fe67c04c8864beff4ac7e1c21602d25a9febc7617423e76234519d279bb2745"},{"id":"chipswiki-518-r1051","title":"Ryzen 5 PRO 4650GE — ChipsWiki, revision 1051","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650ge&oldid=1051","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_4650ge"],"contentSha256":"c856a7611d1e72d75b0d36a117aa1d5e7971f0ea63822440148f9b4a98509139"},{"id":"chipswiki-684-r1678","title":"Ryzen 5 4600HS — ChipsWiki, revision 1678","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600hs&oldid=1678","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/4600hs"],"contentSha256":"dd8d31db37b57d8b1343e63a5fe3426b95be01211645d80cccbe730281609be0"},{"id":"chipswiki-692-r1687","title":"Ryzen 5 4680U — ChipsWiki, revision 1687","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4680u&oldid=1687","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/4680u"],"contentSha256":"565976741a409e655459fe191f031ea351a886ebb6a8acf880d08339cc07245d"},{"id":"chipswiki-712-r1718","title":"Ryzen 5 5500U — ChipsWiki, revision 1718","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5500u&oldid=1718","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/5500u"],"contentSha256":"f6201b6dfcf93c7b2c872844ab69b1b321031d195f185ba450a2c36ab607a75d"},{"id":"chipswiki-713-r1720","title":"Ryzen 5 5600GE — ChipsWiki, revision 1720","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600ge&oldid=1720","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/5600ge"],"contentSha256":"de797cef534d7b6949c8c21ce342d4822df02d24cbc30735dc973d12d5cf1c70"},{"id":"chipswiki-715-r1722","title":"Ryzen 5 5600HS — ChipsWiki, revision 1722","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600hs&oldid=1722","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/5600hs"],"contentSha256":"ccfe5e5f1b271eb9e0a74a7a507318a6bb6dbc649260ed0629a946539837ae82"},{"id":"chipswiki-716-r1723","title":"Ryzen 5 5600U — ChipsWiki, revision 1723","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600u&oldid=1723","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/5600u"],"contentSha256":"036a2c77bc1ea8569d1d29a78245fb4deabedc8b54ff6d01fbcfd87ab2f4ac3e"},{"id":"chipswiki-782-r1920","title":"Ryzen 5 3600XT — ChipsWiki, revision 1920","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3600xt&oldid=1920","publisher":"ChipsWiki / WikiChip contributors","published":"2021-04-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/3600xt"],"contentSha256":"77a8a343a0e2c71ed1c08ebc02ec6844408624834f0f13ff7340cd91acaa6451"},{"id":"chipswiki-900-r2384","title":"Ryzen 5 2500U — ChipsWiki, revision 2384","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500u&oldid=2384","publisher":"ChipsWiki / WikiChip contributors","published":"2020-11-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/2500u"],"contentSha256":"508c4ceaf3f520a380f7aa1a74ee58e562cbe79ffe1006a12086ea6bdd8b5538"},{"id":"chipswiki-922-r2546","title":"Ryzen 5 3580U — ChipsWiki, revision 2546","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3580u&oldid=2546","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/3580u"],"contentSha256":"f7ffbde82b1d6e417124561ddbefda58576dd32abd8246768d2e5361994b9418"},{"id":"chipswiki-2185-r7374","title":"Ryzen 5 PRO 3500U — ChipsWiki, revision 7374","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203500u&oldid=7374","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_3500u"],"contentSha256":"aa216600b65d01611c766ed40a91ab2e0f6f57c48899fde8dfc8475a11139612"},{"id":"chipswiki-3144-r10449","title":"Ryzen 5 PRO 2400G — ChipsWiki, revision 10449","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400g&oldid=10449","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_2400g"],"contentSha256":"c3261caa8225565f0c0aee36e324de2bd9c05fa5401e2c6ce7c16be5ad2b3f96"},{"id":"chipswiki-4834-r15632","title":"Ryzen 5 2600H — ChipsWiki, revision 15632","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600h&oldid=15632","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/2600h"],"contentSha256":"4ffa84dc40a0f6e8ffe7732d06800476910b344a626383d2ae846ad402c3707c"},{"id":"chipswiki-4895-r15756","title":"Ryzen 5 2500X — ChipsWiki, revision 15756","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2500x&oldid=15756","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/2500x"],"contentSha256":"4ef14826c9495b0ea477e70f23d14c54902c3f6eda27e2a2ead422479fbadc4c"},{"id":"chipswiki-5064-r16448","title":"Ryzen 5 2400GE — ChipsWiki, revision 16448","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2400ge&oldid=16448","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/2400ge"],"contentSha256":"81d0519f298d73b95ce48fd05e447190f9ff37969452fad0449f5f367fb3daba"},{"id":"chipswiki-545-r1123","title":"Ryzen 7 5800H — ChipsWiki, revision 1123","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800h&oldid=1123","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/5800h"],"contentSha256":"2a30c31a5300528c23948ace861f659a0d0fbf443ab8e79506aef13c129ee25c"},{"id":"chipswiki-685-r1679","title":"Ryzen 7 4800H — ChipsWiki, revision 1679","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800h&oldid=1679","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4800h"],"contentSha256":"32d743b9105407a72c4eb4b20330b1e40a024c3073e298718a1f42091890d204"},{"id":"chipswiki-686-r1680","title":"Ryzen 7 4800HS — ChipsWiki, revision 1680","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800hs&oldid=1680","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4800hs"],"contentSha256":"85378cec071e839afd485aede0735bc63f2e8b42036bd860b98d8b31c4ae107f"},{"id":"chipswiki-694-r1689","title":"Ryzen 7 4700U — ChipsWiki, revision 1689","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700u&oldid=1689","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4700u"],"contentSha256":"78bc8063aa689212a792d2bbda2482375244a8d3a191b7765986c997996033f5"},{"id":"chipswiki-695-r1690","title":"Ryzen 7 4800U — ChipsWiki, revision 1690","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4800u&oldid=1690","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4800u"],"contentSha256":"e5825a2cdcac0300728670e28a05786a7885c2b88e22c838a89532446c6d225e"},{"id":"chipswiki-696-r1691","title":"Ryzen 7 4980U — ChipsWiki, revision 1691","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4980u&oldid=1691","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4980u"],"contentSha256":"1f9dc7e17964e2ee6f4b28a000d47f11b4b1cc036edf6c4f21d05261962a6eaa"},{"id":"chipswiki-703-r1704","title":"Ryzen 7 PRO 4750GE — ChipsWiki, revision 1704","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750ge&oldid=1704","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_4750ge"],"contentSha256":"8a02b61f65aa64e3fa7f61cd3140d3fe7ba031050ff909478edd0e2bae1ad86b"},{"id":"chipswiki-719-r1729","title":"Ryzen 7 5800HS — ChipsWiki, revision 1729","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800hs&oldid=1729","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/5800hs"],"contentSha256":"89fddcf90c6ce98ea3b414ef2b71ec35aa72eca28344f1ccf810ad9b5d4755cf"},{"id":"chipswiki-725-r1739","title":"Ryzen 7 5800 — ChipsWiki, revision 1739","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800&oldid=1739","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/5800"],"contentSha256":"8e81a5757b3976f405705fb31d154b3f64168820fef0a8b74984561e43764fa9"},{"id":"chipswiki-1548-r5055","title":"Ryzen 7 PRO 3700 — ChipsWiki, revision 5055","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700&oldid=5055","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_3700"],"contentSha256":"277e8eb2ee8a1c527c78165dbf6d09397c4997322d16c87835974ccb20357574"},{"id":"chipswiki-2183-r7371","title":"Ryzen 7 PRO 3700U — ChipsWiki, revision 7371","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%203700u&oldid=7371","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_3700u"],"contentSha256":"ac9a822e60592f433035118d1dcdce70168ac86ae97aa3afae87bce30f9cede3"},{"id":"chipswiki-2184-r7373","title":"Ryzen 7 3700U — ChipsWiki, revision 7373","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3700u&oldid=7373","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/3700u"],"contentSha256":"d8bde2e0fa67e07548686ee58215aaf931fdac2dbdcfce98ac24c3c09cecb8cb"},{"id":"chipswiki-2534-r8710","title":"Ryzen 7 2700U — ChipsWiki, revision 8710","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700u&oldid=8710","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/2700u"],"contentSha256":"20ee208ba2d71f7ebaf9974dec45d38b542d4a5821a816d06e7b8e8974257f0e"},{"id":"chipswiki-4913-r15850","title":"Ryzen 7 PRO 2700X — ChipsWiki, revision 15850","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700x&oldid=15850","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_2700x"],"contentSha256":"fd7add43e044d25fd100aa0f8ad901fa309ececda9b6f571af79ae494cfab151"},{"id":"chipswiki-7352-r23747","title":"Ryzen 7 PRO 1700 — ChipsWiki, revision 23747","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700&oldid=23747","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_1700"],"contentSha256":"583c4ad65fcfcd2599520bc80079d1d0dcd695eadb3c277d30e619f3577cbac6"},{"id":"chipswiki-384-r829","title":"Ryzen Threadripper PRO 3995WX — ChipsWiki, revision 829","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203995wx&oldid=829","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_threadripper/pro_3995wx"],"contentSha256":"9e43941ed8b4c34e25c88a4f7e76c7d7f3f3065dc355981dd755b9ddebcb8e44"},{"id":"chipswiki-31095-r91554","title":"Template:Packages/amd/socket swrx8 — revision 91554","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsocket_swrx8"],"contentSha256":"c8bfbda34898c73f0741f3143d193d3c6fa5eaf7e038ce64f21496268931a3c8"},{"id":"chipswiki-393-r839","title":"Ryzen Threadripper PRO 5965WX — ChipsWiki, revision 839","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205965wx&oldid=839","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_threadripper/pro_5965wx"],"contentSha256":"245f825611abab3269ff6534359e97440c7ff308b450a0d541ac967ba1fca176"},{"id":"chipswiki-394-r840","title":"Ryzen Threadripper PRO 5955WX — ChipsWiki, revision 840","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205955wx&oldid=840","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_threadripper/pro_5955wx"],"contentSha256":"f466b7782e429ac146045da80716f9ce4a2e17e37b44aa421325f4a6ac58c123"},{"id":"chipswiki-552-r1142","title":"Ryzen 9 5980HX — ChipsWiki, revision 1142","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hx&oldid=1142","publisher":"ChipsWiki / WikiChip contributors","published":"2021-12-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/5980hx"],"contentSha256":"e9a69b95b1124763672cedf5364a480c387e9aa238e3f916cff5f4e55764e4f0"},{"id":"chipswiki-881-r2292","title":"Ryzen Embedded V2546 — ChipsWiki, revision 2292","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2546&oldid=2292","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/v2546"],"contentSha256":"4f6ad0ffbd603ed86aefee6282853bcaea93a8a3b1eb1a3d6c30c99b98bc0f14"},{"id":"chipswiki-882-r2293","title":"Ryzen Embedded V2516 — ChipsWiki, revision 2293","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2516&oldid=2293","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/v2516"],"contentSha256":"e7248c00e760822fd707db86f812732f7060d1d6785bbb9042b3875330c4abef"},{"id":"chipswiki-920-r2542","title":"Ryzen Embedded R1305G — ChipsWiki, revision 2542","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1305g&oldid=2542","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/r1305g"],"contentSha256":"587fded11ade61e0e564ce352e0eed813ba6edc8014d69736ccb89b40a19682d"},{"id":"chipswiki-930-r2555","title":"Ryzen Embedded V1404I — ChipsWiki, revision 2555","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1404i&oldid=2555","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/v1404i"],"contentSha256":"59ca7910520c42276fbcbc47f57e7d99ee1a59e010882e79e8d763502e617f6c"},{"id":"chipswiki-932-r2557","title":"Ryzen Embedded V1780B — ChipsWiki, revision 2557","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1780b&oldid=2557","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/v1780b"],"contentSha256":"d608ab4b5c494ec26d76015e45135805354253a9958be5ab13ef825ba1a7c7f5"},{"id":"chipswiki-1549-r5056","title":"Ryzen 9 PRO 3900 — ChipsWiki, revision 5056","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2Fpro%203900&oldid=5056","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/pro_3900"],"contentSha256":"894c31a638642ab1619f804bb5ffdd76b0f56e8770c3a71ada8e266d562c4ea2"},{"id":"chipswiki-2-r96913","title":"A14 Bionic — ChipsWiki, revision 96913","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa14&oldid=96913","publisher":"ChipsWiki / WikiChip contributors","published":"2022-12-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a14"],"contentSha256":"269a2ec91dc53f42deb616d97412169155371d79e09ed5a743962005e55e355a"},{"id":"chipswiki-186-r374","title":"A13 Bionic — ChipsWiki, revision 374","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa13&oldid=374","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a13"],"contentSha256":"a4361b726dd4b30f7e52e70fa91a691e35490423c16bac90246517d79f3d8736"},{"id":"chipswiki-282-r567","title":"AWS Graviton — ChipsWiki, revision 567","url":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Fal73400&oldid=567","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Annapurna_labs/alpine/al73400"],"contentSha256":"83d2ffdfb1dbde87be38340aedffc73029636a298ca9107239ba46ef9e31c632"},{"id":"chipswiki-618-r1450","title":"A12 Bionic — ChipsWiki, revision 1450","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12&oldid=1450","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a12"],"contentSha256":"546b354ef23f7d31e19e88d7f252ca48bd649829e1c5d90228e0497803787578"},{"id":"chipswiki-810-r2070","title":"A6 — ChipsWiki, revision 2070","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa6&oldid=2070","publisher":"ChipsWiki / WikiChip contributors","published":"2021-02-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a6"],"contentSha256":"0755f39baafabf0833645c5b1b0442c04d0ed5d1972c65ee0c4ceb04d7e8fc80"},{"id":"chipswiki-811-r2071","title":"A7 — ChipsWiki, revision 2071","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa7&oldid=2071","publisher":"ChipsWiki / WikiChip contributors","published":"2021-02-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a7"],"contentSha256":"60b717830b3e5f728b0f2ec9a8c8bef9a8d4c6fbb098679264bad3941380795b"},{"id":"chipswiki-1236-r3943","title":"A12X Bionic — ChipsWiki, revision 3943","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12x&oldid=3943","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a12x"],"contentSha256":"18ac1a2b56ebdfcf393a644613dc84bcabed19775cc0df1712b5f87edef46956"},{"id":"chipswiki-4750-r15326","title":"X-Gene 1 APM883408-X1 — ChipsWiki, revision 15326","url":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x1&oldid=15326","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apm/x-gene/apm883408-x1"],"contentSha256":"4e4cb54d5112d2c26864fa2971171050878c214429ceb2921be4ebbf018b6c5d"},{"id":"chipswiki-4751-r15329","title":"X-Gene 1 APM883208-X1 — ChipsWiki, revision 15329","url":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x1&oldid=15329","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apm/x-gene/apm883208-x1"],"contentSha256":"3540f8a0968b75349dcc0725a45e94188c03e7dab6a3d9c34afe82265a7b05dc"},{"id":"chipswiki-4753-r15334","title":"eMAG 8180 — ChipsWiki, revision 15334","url":"https://chipswiki.org/index.php?title=Ampere%20computing%2Femag%2F8180&oldid=15334","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ampere_computing/emag/8180"],"contentSha256":"93f1974679546810efbb4a0e7a4907d297b4b43315deaebbc213957605be5598"},{"id":"chipswiki-31305-r92007","title":"Template:Packages/ampere computing/fcbga-3211 — revision 92007","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fampere%20computing%2Ffcbga-3211&oldid=92007","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fampere_computing%2Ffcbga-3211"],"contentSha256":"91d7f350ed8d3323d8da3ec71dd655814a12a16f441fdb33e17de1a254a06f78"},{"id":"chipswiki-4758-r15344","title":"X-Gene 2 APM883408-X2 — ChipsWiki, revision 15344","url":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883408-x2&oldid=15344","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apm/x-gene/apm883408-x2"],"contentSha256":"5ba5829cb05f65c7b873957d63489d01d60083296bf5b01a7348b87d2a57e22b"},{"id":"chipswiki-4776-r15405","title":"Skylark — ChipsWiki, revision 15405","url":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fskylark&oldid=15405","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apm/microarchitectures/skylark"],"contentSha256":"c42276140fe387c925dcf61cacd9043b35bf2f89f3a68403a3666ae371843251"},{"id":"chipswiki-45-r96985","title":"Cortex-A510 — ChipsWiki, revision 96985","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a510&oldid=96985","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a510"],"contentSha256":"2df2b3a54358d9e9be7d672678bf3f09521f99efe2c4ece86bc2de7c2c471d3f"},{"id":"chipswiki-216-r442","title":"Logan — ChipsWiki, revision 442","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton-elp&oldid=442","publisher":"ChipsWiki / WikiChip contributors","published":"2022-08-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/chaberton-elp"],"contentSha256":"fc541f9f21a60e80a78e0a64e518a1902892dfca088f971394b31bedb5716be8"},{"id":"chipswiki-304-r618","title":"Chaberton — ChipsWiki, revision 618","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fchaberton&oldid=618","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/chaberton"],"contentSha256":"01594c9216289848176983d0e608dbaf3b5a8b7ae9850cc1396b0ac388c37fe3"},{"id":"chipswiki-307-r622","title":"Cortex-A715 — ChipsWiki, revision 622","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a715&oldid=622","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a715"],"contentSha256":"f647b30a5a4540a6062bb95b1439b2dd760c31c23042e83c2cf8418f8d14793e"},{"id":"chipswiki-493-r985","title":"Cortex-A53 — ChipsWiki, revision 985","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a53&oldid=985","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a53"],"contentSha256":"2e01138ee99c7fd619eba94aa0e489639cb8a8d4c1ca624ba8c5e51d82ab0fe9"},{"id":"chipswiki-559-r1175","title":"Cortex-A34 — ChipsWiki, revision 1175","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a34&oldid=1175","publisher":"ChipsWiki / WikiChip contributors","published":"2021-12-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a34"],"contentSha256":"d89b5ac8e3d92459bc505b8743fd05bce5abcd2c993566fb3a94b16a678506bc"},{"id":"chipswiki-792-r1981","title":"Cortex-A73 — ChipsWiki, revision 1981","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a73&oldid=1981","publisher":"ChipsWiki / WikiChip contributors","published":"2021-04-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a73"],"contentSha256":"a120af7dae670acb1776c5e06ed245488a12c31e7c1e5af7b7bcb2a79c276ed5"},{"id":"chipswiki-934-r2600","title":"ARM9 — ChipsWiki, revision 2600","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm9&oldid=2600","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/arm9"],"contentSha256":"15551401665888ec3404a2fc01fc306e2b241032cedb32ecc72b6f9604bf55e6"},{"id":"chipswiki-1668-r5834","title":"ARM8 — ChipsWiki, revision 5834","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm8&oldid=5834","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/arm8"],"contentSha256":"1fd39dd0517e55989d41c634a423e109d9ab21d5559e25367900cd14a1c9ec92"},{"id":"chipswiki-4146-r13211","title":"Cortex-A15 — ChipsWiki, revision 13211","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a15&oldid=13211","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a15"],"contentSha256":"f239ce8452e36725ed9485347bf6841307a09b0549c72ac968908ef31423d19a"},{"id":"chipswiki-4149-r13226","title":"Cortex-A17 — ChipsWiki, revision 13226","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a17&oldid=13226","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a17"],"contentSha256":"ba3b523905e6b3949ce1e869ef4e3837c3d6be9cfcc3c464653c45426aaf37e9"},{"id":"chipswiki-4154-r13231","title":"ARM7 — ChipsWiki, revision 13231","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm7&oldid=13231","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/arm7"],"contentSha256":"ea22eb6de9bc012592f82c516644574f00220d7c4eb2a53408338b759a5445d1"},{"id":"chipswiki-4167-r13321","title":"ARM10 — ChipsWiki, revision 13321","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm10&oldid=13321","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/arm10"],"contentSha256":"9714a27f3761c8ce942ab4931c0869f2e7883399a00092b94e6ecced9e06ea19"},{"id":"chipswiki-303-r617","title":"Cortex-X1 — ChipsWiki, revision 617","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x1&oldid=617","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-x1"],"contentSha256":"8c166625633076373e62419241f2d94a387cd6605e795ece80401761dcdc50ee"},{"id":"chipswiki-305-r619","title":"Hunter — ChipsWiki, revision 619","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter&oldid=619","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/hunter"],"contentSha256":"e9f88f6230b467cd91164bff9177c0a8137b757066973607f85b7e9746ef04ef"},{"id":"chipswiki-427-r899","title":"Cortex-A78 — ChipsWiki, revision 899","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a78&oldid=899","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a78"],"contentSha256":"d8bb59e61b3365c782adca3e635294cd22bbcf7e0da6de8f1dc00316d773cc26"},{"id":"chipswiki-657-r1592","title":"Neoverse N1 — ChipsWiki, revision 1592","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n1&oldid=1592","publisher":"ChipsWiki / WikiChip contributors","published":"2021-07-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/neoverse_n1"],"contentSha256":"2bd5f2d7f1629135afa1380b8d27b58b38c852b133bdd151a2cc587c75aab412"},{"id":"chipswiki-775-r1908","title":"Neoverse N2 — ChipsWiki, revision 1908","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20n2&oldid=1908","publisher":"ChipsWiki / WikiChip contributors","published":"2021-04-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/neoverse_n2"],"contentSha256":"8f7cbdbf451fd79e313c1484bca944352c96f1132e7c02cf8a5c1d5a45c4755f"},{"id":"chipswiki-926-r2550","title":"Cortex-A76 — ChipsWiki, revision 2550","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a76&oldid=2550","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a76"],"contentSha256":"e50b6c4de923f005e4c03377a244c2b01f509b3b1a80b41a8515783db29c0d6a"},{"id":"chipswiki-1089-r3208","title":"Cortex-A77 — ChipsWiki, revision 3208","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a77&oldid=3208","publisher":"ChipsWiki / WikiChip contributors","published":"2020-06-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a77"],"contentSha256":"d8a2fcc6c2f9f85bd1122ccedfa3e05378d8bd57dd94ccb5cf0f8505b2f2d2a4"},{"id":"chipswiki-1235-r3896","title":"Cortex-A75 — ChipsWiki, revision 3896","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a75&oldid=3896","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a75"],"contentSha256":"b93282fbf655a688a7d61b88cdb40795dea9b75d3405ad3faa26e2c090d6995e"},{"id":"chipswiki-1310-r4387","title":"Machine Learning Processor (MLP) — ChipsWiki, revision 4387","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fmlp&oldid=4387","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/mlp"],"contentSha256":"c76f80a61d1d5a2cc16bcf535a6cfbdb6aaf36c959c0ac30b451a63f9b8006bf"},{"id":"chipswiki-4147-r13218","title":"Cortex-A8 — ChipsWiki, revision 13218","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a8&oldid=13218","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a8"],"contentSha256":"7b47ddcd5abc07aa0defaf35f22c48f7c2978b944d24ffda8ee83a7f0c6627f4"},{"id":"chipswiki-31370-r92158","title":"Template:Packages/bitmain/fcbga-1599 — revision 92158","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fbitmain%2Ffcbga-1599"],"contentSha256":"6c5e1f222409cb10ece4588ac5fbe3e9cec09616c110271568bc60144ceeb2f4"},{"id":"chipswiki-5066-r16475","title":"Sophon BM1686 — ChipsWiki, revision 16475","url":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1686&oldid=16475","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Bitmain/sophon/bm1686"],"contentSha256":"f69338e887504465f37b4e0a2c9a599d258dafa77044452b5d773a13de617d5d"},{"id":"chipswiki-5068-r16483","title":"Sophon BM1680 — ChipsWiki, revision 16483","url":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1680&oldid=16483","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Bitmain/sophon/bm1680"],"contentSha256":"015087e9fd0fcdf79e64dfa8835e362b967bbc829f5409262ca0c8b1b33bed78"},{"id":"chipswiki-3040-r10166","title":"MLU100 — ChipsWiki, revision 10166","url":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu100&oldid=10166","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cambricon/mlu/mlu100"],"contentSha256":"b0ab9b033321312ca392f1f9033895be79aeb28227f258c342671ac37ab41898"},{"id":"chipswiki-8256-r25916","title":"CN3110-550 EXP — ChipsWiki, revision 25916","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-exp&oldid=25916","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-550bg868-exp"],"contentSha256":"5bd75ce8f58d0c2e586c2122f00d5ea56523f79c2b0720e2219ce1f66b5ecf8b"},{"id":"chipswiki-31467-r92415","title":"Template:Packages/cavium/hsbga-868 — revision 92415","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fcavium%2Fhsbga-868"],"contentSha256":"8fa01a79460e61138794162e0383545bbcd974317610a91b51a1e40a075ccc29"},{"id":"chipswiki-8260-r25920","title":"CN3110-500 EXP — ChipsWiki, revision 25920","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-exp&oldid=25920","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-500bg868-exp"],"contentSha256":"fad0f06a77ba02f058bad8bbb4a4eb9595afaa7e02e22f6128b6fe86188d449e"},{"id":"chipswiki-8261-r25921","title":"CN3110-500 CP — ChipsWiki, revision 25921","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-cp&oldid=25921","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-500bg868-cp"],"contentSha256":"beb642b3d22bde75a3e10bbca3353b551df7d840bbdfd988fe35137b294e72ef"},{"id":"chipswiki-8262-r25922","title":"CN3110-400 SCP — ChipsWiki, revision 25922","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-scp&oldid=25922","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-400bg868-scp"],"contentSha256":"a6fa5d30e37a7a962841cfd7fbc9c5910d4dc8a41dba62247c7612b12401dcb5"},{"id":"chipswiki-8265-r25925","title":"CN3110-400 CP — ChipsWiki, revision 25925","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-cp&oldid=25925","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-400bg868-cp"],"contentSha256":"d377fb609c8677bce85ab8526fa302d5d27517bd374df1931a71914f20a70a8d"},{"id":"chipswiki-8266-r25926","title":"CN3110-300 SCP — ChipsWiki, revision 25926","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-scp&oldid=25926","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-300bg868-scp"],"contentSha256":"cec970ac0a7e189529135c2381b9dfc9505532e2f0766d21672f677225677f08"},{"id":"chipswiki-8267-r25927","title":"CN3110-300 NSP — ChipsWiki, revision 25927","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-nsp&oldid=25927","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-300bg868-nsp"],"contentSha256":"d781904d9dca510ecab87ba7b5e8fcb0b9aa23449663c5eaa6a7c6b390394960"},{"id":"chipswiki-8268-r25928","title":"CN3110-300 EXP — ChipsWiki, revision 25928","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-exp&oldid=25928","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-300bg868-exp"],"contentSha256":"2e659bd8e44c2a2a5cbf0d4efbd6e8bf8fa34bbb1b29d54b4cde6c5f6194b2ef"},{"id":"chipswiki-8269-r25929","title":"CN3110-300 CP — ChipsWiki, revision 25929","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-300bg868-cp&oldid=25929","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-300bg868-cp"],"contentSha256":"459c8d3748279f3d74b281f84a5dec9e30a144f49163edd5502749b7430d2f03"},{"id":"chipswiki-8274-r25934","title":"CN3010-300 SCP — ChipsWiki, revision 25934","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-scp&oldid=25934","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3010-300bg525-scp"],"contentSha256":"76f0d947492def7f707c95e5de8c6cc532af5074853000fbfc8ad35ee5a3a45a"},{"id":"chipswiki-8278-r25938","title":"CN3005-400 SCP — ChipsWiki, revision 25938","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-scp&oldid=25938","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3005-400bg350-scp"],"contentSha256":"22407e49994d2240f3b3b911b7c15884a031b9b5b87415e0f581bcaabe9922e4"},{"id":"chipswiki-8279-r25939","title":"CN3005-400 CP — ChipsWiki, revision 25939","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-400bg350-cp&oldid=25939","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3005-400bg350-cp"],"contentSha256":"5371d580250875c927adb2d28188d713f4c21d694268d93ef12164a8aa5424fb"},{"id":"chipswiki-14801-r46395","title":"cnMIPS — ChipsWiki, revision 46395","url":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fcnmips&oldid=46395","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/microarchitectures/cnmips"],"contentSha256":"48552cb16f613b4d8752f34c9c9e4afeeef66f677c46bd0707b233144b464677"},{"id":"chipswiki-8207-r25866","title":"CN3850-500 NSP — ChipsWiki, revision 25866","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-nsp&oldid=25866","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3850-500bg1521-nsp"],"contentSha256":"767c47b812b86b4cc6d86cdd4ff713f75a59521fdf5f71cc476734a87ceb4dad"},{"id":"chipswiki-31466-r92414","title":"Template:Packages/cavium/fcbga-1521 — revision 92414","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fcavium%2Ffcbga-1521"],"contentSha256":"ec52edae17c13ae0f44bd6001a2d01c438ab4a2d00022aa12ae40ea5b93acc24"},{"id":"chipswiki-8218-r25877","title":"CN3840-400 SCP — ChipsWiki, revision 25877","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-scp&oldid=25877","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3840-400bg1521-scp"],"contentSha256":"c48bf30f98cc42d2d436ec531d95d25095880deaf3715fe4e52e453ca4079f37"},{"id":"chipswiki-8221-r25880","title":"CN3830-600 SCP — ChipsWiki, revision 25880","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-scp&oldid=25880","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3830-600bg1521-scp"],"contentSha256":"6657f2d863583cf992c5e0a1ddb5f7f3c602aa56992292ee0b05de89b3ee3843"},{"id":"chipswiki-8222-r25881","title":"CN3830-600 NSP — ChipsWiki, revision 25881","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-nsp&oldid=25881","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3830-600bg1521-nsp"],"contentSha256":"097b6151a89e1e0a5bcde316743168ceef427a7c631b7125479770f792187dce"},{"id":"chipswiki-8223-r25882","title":"CN3830-600 EXP — ChipsWiki, revision 25882","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-600bg1521-exp&oldid=25882","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3830-600bg1521-exp"],"contentSha256":"db7cc446c927f38af41596b6dee1b70f671ddfe8328eddc85ee085d0c9595b39"},{"id":"chipswiki-8225-r25884","title":"CN3830-500 NSP — ChipsWiki, revision 25884","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-nsp&oldid=25884","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3830-500bg1521-nsp"],"contentSha256":"7cbb6d387e3b02ff6bb1e6028ed5e3df5e7edd161623174135109de3f07409d4"},{"id":"chipswiki-8228-r25887","title":"CN3830-400 NSP — ChipsWiki, revision 25887","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-nsp&oldid=25887","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3830-400bg1521-nsp"],"contentSha256":"f4966ecc9fae92b32ac2be4019c8ea5fd5c69a7cb56dc59f9573e5cf4d624d84"},{"id":"chipswiki-8230-r25889","title":"CN3630-600 SCP — ChipsWiki, revision 25889","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-scp&oldid=25889","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-600bg1521-scp"],"contentSha256":"4111c3d201a492f8ea7891dde060d6b9059e586f886df4eacf47b3ed0c1549b1"},{"id":"chipswiki-8231-r25890","title":"CN3630-600 NSP — ChipsWiki, revision 25890","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-nsp&oldid=25890","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-600bg1521-nsp"],"contentSha256":"a7deb3069ead9bbaaf6606d94e6aabd49fb54c46a12a5740de5eaf11e203e488"},{"id":"chipswiki-8232-r25891","title":"CN3630-600 EXP — ChipsWiki, revision 25891","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-600bg1521-exp&oldid=25891","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-600bg1521-exp"],"contentSha256":"073c90c883ca1f4453dd3c402902db40e105448b5d9157c386e46d1c2c6e166e"},{"id":"chipswiki-8233-r25892","title":"CN3630-500 SCP — ChipsWiki, revision 25892","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-scp&oldid=25892","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-500bg1521-scp"],"contentSha256":"de4385447581561b35377291eb6e01dd7ab3df3fea0f9cdacae78f87229bb6c8"},{"id":"chipswiki-8234-r25893","title":"CN3630-500 NSP — ChipsWiki, revision 25893","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-nsp&oldid=25893","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-500bg1521-nsp"],"contentSha256":"a6137f752e3c51fb1cd3183cfa3b6ef8c455970e7a5c0db6910e98dd8632360c"},{"id":"chipswiki-8236-r25895","title":"CN3630-400 SCP — ChipsWiki, revision 25895","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-scp&oldid=25895","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-400bg1521-scp"],"contentSha256":"95a566acfb723bf2ae95c3f072ddd547d2e4ed74a4093040fda2b70d345d0d78"},{"id":"chipswiki-8237-r25896","title":"CN3630-400 NSP — ChipsWiki, revision 25896","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-nsp&oldid=25896","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-400bg1521-nsp"],"contentSha256":"ab20cdff3f1e62baeee44a65c3279364cc695080c2deb243b0db9b0434fd7a40"},{"id":"chipswiki-8238-r25897","title":"CN3630-400 EXP — ChipsWiki, revision 25897","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-400bg1521-exp&oldid=25897","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3630-400bg1521-exp"],"contentSha256":"add9818f57e566e7f9d3051b4a6297ca6c9989f1c3a47b7a5f82af86b5a07b83"},{"id":"chipswiki-8239-r25899","title":"CN3120-550 NSP — ChipsWiki, revision 25899","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-nsp&oldid=25899","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3120-550bg868-nsp"],"contentSha256":"9b52218bc597fcfceed54f30b86815f247c5339ffefaa72515852920a5ca840b"},{"id":"chipswiki-8245-r25905","title":"CN3120-500 CP — ChipsWiki, revision 25905","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-cp&oldid=25905","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3120-500bg868-cp"],"contentSha256":"e8864a000e2c404784624fb5f46fb4b04fa9391c5e7d3b7c2c27e16c08c55d68"},{"id":"chipswiki-8250-r25910","title":"CN3120-300 SCP — ChipsWiki, revision 25910","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-scp&oldid=25910","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3120-300bg868-scp"],"contentSha256":"07dd32ca577e0cd21e8544276fb673c774c0771892dc483aa1e26d1373071e77"},{"id":"chipswiki-8251-r25911","title":"CN3120-300 NSP — ChipsWiki, revision 25911","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-nsp&oldid=25911","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3120-300bg868-nsp"],"contentSha256":"41192d0b9621e4a8578262af542a76fb54c61372127017d4fa43178c0169b9d9"},{"id":"chipswiki-8253-r25913","title":"CN3120-300 CP — ChipsWiki, revision 25913","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-cp&oldid=25913","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3120-300bg868-cp"],"contentSha256":"6eb19abc84161984b55d8029d7b13674ac23c21c204f9a3ded599cf97edf6204"},{"id":"chipswiki-8254-r25914","title":"CN3110-550 SCP — ChipsWiki, revision 25914","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-scp&oldid=25914","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3110-550bg868-scp"],"contentSha256":"739a065bd66530ab956d47308e93f6f49db10f3e7717c96731e2224bfff634da"},{"id":"chipswiki-8158-r25817","title":"CN5830-600 EXP — ChipsWiki, revision 25817","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-exp&oldid=25817","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5830-600bg1521-exp"],"contentSha256":"f04f29a2dd48d7ddfd1895b4e4e5937cb5df31e896df3a5f0f6f0c3d73394503"},{"id":"chipswiki-8159-r25818","title":"CN5830-1000 SCP — ChipsWiki, revision 25818","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-scp&oldid=25818","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5830-1000bg1521-scp"],"contentSha256":"fb14d94f0980cd6185486fecf24de19096de741bdcaf209ab4cd8c8f9e0097f5"},{"id":"chipswiki-8160-r25819","title":"CN5830-1000 NSP — ChipsWiki, revision 25819","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-nsp&oldid=25819","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5830-1000bg1521-nsp"],"contentSha256":"c1331fa1824173912663e930b4f168981802bdaaf0791463caa2f734539a6739"},{"id":"chipswiki-31460-r92405","title":"Template:Packages/cavium/fcbga-1217 — revision 92405","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fcavium%2Ffcbga-1217"],"contentSha256":"4ba29501eb573594d500cce9f8952d2e66b7473c16a4c0f52755ec1dc9b573b8"},{"id":"chipswiki-8163-r25822","title":"CN5750-900 SP — ChipsWiki, revision 25822","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-sp&oldid=25822","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5750-900bg1217-sp"],"contentSha256":"3301d7fd0caf95a92a1aa259cab88b861d9c3c7f4e327b1feac1a4d6200eca0e"},{"id":"chipswiki-8169-r25828","title":"CN5750-1000 SP — ChipsWiki, revision 25828","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-1000bg1217-sp&oldid=25828","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5750-1000bg1217-sp"],"contentSha256":"e3aeccdfcb67e82fdba8cad0d811e4845ba897651398ae9660d0491fcf3168e2"},{"id":"chipswiki-8170-r25829","title":"CN5745-900 SSP — ChipsWiki, revision 25829","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-ssp&oldid=25829","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-900bg1217-ssp"],"contentSha256":"b664796b164ce6e2db7e2488c1a60395757f9ddc060e0fde9694fe8f24cc5bd7"},{"id":"chipswiki-8171-r25830","title":"CN5745-900 SP — ChipsWiki, revision 25830","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-900bg1217-sp&oldid=25830","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-900bg1217-sp"],"contentSha256":"bfb374ba18a5f8bc099d1969a10f348e66173c77ce7636b2b2ebb31551b37cc2"},{"id":"chipswiki-8172-r25831","title":"CN5745-800 SSP — ChipsWiki, revision 25831","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-ssp&oldid=25831","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-800bg1217-ssp"],"contentSha256":"f1eb0ac0fe68196c4afa2b874ad7ccebdb8d45facc91684f741743c43985f94a"},{"id":"chipswiki-8174-r25833","title":"CN5745-600 SSP — ChipsWiki, revision 25833","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-ssp&oldid=25833","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-600bg1217-ssp"],"contentSha256":"3e7cb14ba326caa349caea5f8cdb8adea39020975b3378fe66ad9c26cb1580b9"},{"id":"chipswiki-8175-r25834","title":"CN5745-600 SP — ChipsWiki, revision 25834","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-600bg1217-sp&oldid=25834","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-600bg1217-sp"],"contentSha256":"a425d4185c5b0946568ae7a633503c2bc9b17ab46dd18778932606b382792f37"},{"id":"chipswiki-8178-r25837","title":"CN5740-900 SSP — ChipsWiki, revision 25837","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-ssp&oldid=25837","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-900bg1217-ssp"],"contentSha256":"d5e8465d887094f7f8df9c64ad6d20de241b3f8be974d3639b533a82a2275987"},{"id":"chipswiki-8181-r25840","title":"CN5740-800 SP — ChipsWiki, revision 25840","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-sp&oldid=25840","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-800bg1217-sp"],"contentSha256":"8837e27fc8a156b988979a386e82db67217f88ce96530bcb437977bf6e0664ab"},{"id":"chipswiki-8182-r25841","title":"CN5740-600 SSP — ChipsWiki, revision 25841","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-ssp&oldid=25841","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-600bg1217-ssp"],"contentSha256":"ee513dd26c99f37f6a4d70c53d75278f4603950f1e33c8385fc2df499e051c12"},{"id":"chipswiki-8183-r25842","title":"CN5740-600 SP — ChipsWiki, revision 25842","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-600bg1217-sp&oldid=25842","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-600bg1217-sp"],"contentSha256":"9ee6f311b275b3b9dedc64967363d6c3b3b6d5ece0440d87bb4845b0ddfdc5fa"},{"id":"chipswiki-8184-r25843","title":"CN5740-1000 SSP — ChipsWiki, revision 25843","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-ssp&oldid=25843","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-1000bg1217-ssp"],"contentSha256":"d087c7a56d164e305809ef6b7e6b1bf6ff7eaed092ededc6c344e8b60c03c21a"},{"id":"chipswiki-8185-r25844","title":"CN5740-1000 SP — ChipsWiki, revision 25844","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-1000bg1217-sp&oldid=25844","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-1000bg1217-sp"],"contentSha256":"215e538350ecefd415da96c180eae614b8428ba4c258ef853f741069be57d7f0"},{"id":"chipswiki-8187-r25846","title":"CN5734-900 SP — ChipsWiki, revision 25846","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-sp&oldid=25846","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5734-900bg1217-sp"],"contentSha256":"a7d7d1313b846d1864bc770d5694f38c3760253826a5d38ebe6a95b499ab0f3a"},{"id":"chipswiki-8191-r25850","title":"CN5734-600 SP — ChipsWiki, revision 25850","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-sp&oldid=25850","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5734-600bg1217-sp"],"contentSha256":"eb395e105d8035a0fab90dfe300ee2836fdc5e6790ee18293408d24a24c77d17"},{"id":"chipswiki-8195-r25854","title":"CN3860-600 NSP — ChipsWiki, revision 25854","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-nsp&oldid=25854","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3860-600bg1521-nsp"],"contentSha256":"64124cfa9e0add777c6902c652cd67e5192b78fc3977688c1e4351a00da8be39"},{"id":"chipswiki-8204-r25863","title":"CN3850-600 NSP — ChipsWiki, revision 25863","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-nsp&oldid=25863","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3850-600bg1521-nsp"],"contentSha256":"efbdffb7fe2236b3b2e012ec35ce831d59f2d8b2a04b046acdb7c6d4ffcf9d97"},{"id":"chipswiki-8205-r25864","title":"CN3850-600 EXP — ChipsWiki, revision 25864","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-exp&oldid=25864","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3850-600bg1521-exp"],"contentSha256":"6bcde42d5ffc1499fa8f8a8f94688c22c04e3627b46aa2854e3d406cc84468e3"},{"id":"chipswiki-3906-r12389","title":"CN8020 — ChipsWiki, revision 12389","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20tx%2Fcn8020&oldid=12389","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_tx/cn8020"],"contentSha256":"bd102d3a4df8d34a4103393825f981841a95823adc87903a77bb723c2555cd4a"},{"id":"chipswiki-4330-r13921","title":"ThunderX CN8890 — ChipsWiki, revision 13921","url":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx%2Fcn8890&oldid=13921","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/thunderx/cn8890"],"contentSha256":"7836f5e3f50606270f30680b0f30d697094657e3efa25db484cee0667904a850"},{"id":"chipswiki-4335-r13948","title":"ThunderX2 CN9960 — ChipsWiki, revision 13948","url":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9960&oldid=13948","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/thunderx2/cn9960"],"contentSha256":"195a48873eced8ca94c8111dac641cda905c2eb3a316ad0098c8a29de9109ad0"},{"id":"chipswiki-8114-r25773","title":"CN5860-900 SCP — ChipsWiki, revision 25773","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-scp&oldid=25773","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5860-900bg1521-scp"],"contentSha256":"396f8b4360fc59f18768febb65e8cf79243900b41bb8542e5641dd59cd3a1eb0"},{"id":"chipswiki-8125-r25784","title":"CN5860-1000 EXP — ChipsWiki, revision 25784","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-exp&oldid=25784","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5860-1000bg1521-exp"],"contentSha256":"56d938e30687caed73d534d5f844fe84c929892d7f308d0fc187d1ebb53bc722"},{"id":"chipswiki-8126-r25785","title":"CN5850-900 SCP — ChipsWiki, revision 25785","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-scp&oldid=25785","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-900bg1521-scp"],"contentSha256":"c91e27e76ab62eac568f7bf79ce59d708904720a7d077aca04b515aa7d9e7ba3"},{"id":"chipswiki-8130-r25789","title":"CN5850-800 NSP — ChipsWiki, revision 25789","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-nsp&oldid=25789","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-800bg1521-nsp"],"contentSha256":"775277e6e2fe1d93d4810100cc8d2d6a283225eceebe24e0a9ac372cda96c927"},{"id":"chipswiki-8132-r25791","title":"CN5850-600 SCP — ChipsWiki, revision 25791","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-scp&oldid=25791","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-600bg1521-scp"],"contentSha256":"ae5c8eb274c671b8f2e63b8fe2898eb4dde1938b81414b6199b6beef912b744d"},{"id":"chipswiki-8133-r25792","title":"CN5850-600 NSP — ChipsWiki, revision 25792","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-nsp&oldid=25792","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-600bg1521-nsp"],"contentSha256":"c089c9c2acd1e77bb5424cc53315538c481e7f74ab410169b89733eb24dcf88a"},{"id":"chipswiki-8134-r25793","title":"CN5850-600 EXP — ChipsWiki, revision 25793","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-600bg1521-exp&oldid=25793","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-600bg1521-exp"],"contentSha256":"1d93676363da8eea93da98407dc2d65684ffc06ae832c702becba698580497cb"},{"id":"chipswiki-8135-r25794","title":"CN5850-1000 SCP — ChipsWiki, revision 25794","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-scp&oldid=25794","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-1000bg1521-scp"],"contentSha256":"3dd34fd616fccaeb26b98c1ad689a4973a65260fca6b6aebe483f7decc137724"},{"id":"chipswiki-8136-r25795","title":"CN5850-1000 NSP — ChipsWiki, revision 25795","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-nsp&oldid=25795","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5850-1000bg1521-nsp"],"contentSha256":"656393208e54b56958660aef7e9c207009f1ec3de15cf1db24be4fa74d6893c3"},{"id":"chipswiki-8139-r25798","title":"CN5840-900 NSP — ChipsWiki, revision 25798","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-nsp&oldid=25798","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-900bg1521-nsp"],"contentSha256":"e2f3c7b9df8768cb6aeeb93101f42d321e5d35725f838c0dbb0e6b5d74558950"},{"id":"chipswiki-8142-r25801","title":"CN5840-800 NSP — ChipsWiki, revision 25801","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-nsp&oldid=25801","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-800bg1521-nsp"],"contentSha256":"758f5e6aadb3d492189c2bcf476022259f3146bd074476992d1c403b417eacd8"},{"id":"chipswiki-8143-r25802","title":"CN5840-800 EXP — ChipsWiki, revision 25802","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-800bg1521-exp&oldid=25802","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-800bg1521-exp"],"contentSha256":"b7d9076b7b1cf0f04bd4ba99bae078b6ac9667ad9f5b93fb0e351545b698249f"},{"id":"chipswiki-8144-r25803","title":"CN5840-600 SCP — ChipsWiki, revision 25803","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-scp&oldid=25803","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-600bg1521-scp"],"contentSha256":"6a6671d0274152e1186783394e8bc290cec3643ac6a6cb4a5f72321ef103b4f7"},{"id":"chipswiki-8146-r25805","title":"CN5840-600 EXP — ChipsWiki, revision 25805","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-exp&oldid=25805","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-600bg1521-exp"],"contentSha256":"2ba8f9fd6ec8ad3f1df72a173db81821f5238555a0cfc157c4fc6ce122fc8381"},{"id":"chipswiki-8147-r25806","title":"CN5840-1000 SCP — ChipsWiki, revision 25806","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-scp&oldid=25806","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-1000bg1521-scp"],"contentSha256":"02f3a548e4db21565a91339fbc49631929add3b17dcda25fee346c2b50d671bc"},{"id":"chipswiki-8148-r25807","title":"CN5840-1000 NSP — ChipsWiki, revision 25807","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-nsp&oldid=25807","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5840-1000bg1521-nsp"],"contentSha256":"aac95a68da977c9675ad2c4e007937623fba2b8754dfbf267f5f3cef53321898"},{"id":"chipswiki-8152-r25811","title":"CN5830-900 EXP — ChipsWiki, revision 25811","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-exp&oldid=25811","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5830-900bg1521-exp"],"contentSha256":"4b61d110d04d4f123defc47f3bc8bc143873c5f48425ba3e9c147520dfa5bd1f"},{"id":"chipswiki-8153-r25812","title":"CN5830-800 SCP — ChipsWiki, revision 25812","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-scp&oldid=25812","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5830-800bg1521-scp"],"contentSha256":"3aa63a7a912b41b89577e1d43b785e78ad0acd160b2d0beb6956cfe13838c693"},{"id":"chipswiki-180-r350","title":"CHA — ChipsWiki, revision 350","url":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fcha&oldid=350","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Centaur/microarchitectures/cha"],"contentSha256":"cc7e58527c7af981f742bd24601f2e8bbeb72be2d29a5793ef86ad10e7cb7d58"},{"id":"chipswiki-961-r2714","title":"Rosetta — ChipsWiki, revision 2714","url":"https://chipswiki.org/index.php?title=Cray%2Fmicroarchitectures%2Frosetta&oldid=2714","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cray/microarchitectures/rosetta"],"contentSha256":"0bf92944e313abc4a28c2628361bce7cd73a8db2fe3cb420ef4d4eeb69b1520e"},{"id":"chipswiki-1227-r3846","title":"TSARLET — ChipsWiki, revision 3846","url":"https://chipswiki.org/index.php?title=Cea-leti%2Fmicroarchitectures%2Ftsarlet&oldid=3846","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cea-leti/microarchitectures/tsarlet"],"contentSha256":"c089d7575bec7a7e07382629255dead7d0aed9bc5ff24ab32dfa7e4576a0f9fa"},{"id":"chipswiki-7383-r23870","title":"Samuel — ChipsWiki, revision 23870","url":"https://chipswiki.org/index.php?title=Centaur%2Fmicroarchitectures%2Fsamuel&oldid=23870","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Centaur/microarchitectures/samuel"],"contentSha256":"5b50951c381ab45fb593752d7828cf584c18959d1bfd117a0aa68c0c5f8bdea1"},{"id":"chipswiki-15452-r48576","title":"Alpha 21364 — ChipsWiki, revision 48576","url":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021364&oldid=48576","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Compaq/microarchitectures/alpha_21364"],"contentSha256":"9f958a1c98da9563b1ce401d6f9491ed00d5340c67b022d16bbd765474d577cc"},{"id":"chipswiki-1619-r5482","title":"Electronic Arrays 9002 (EA9002) — ChipsWiki, revision 5482","url":"https://chipswiki.org/index.php?title=EA9002&oldid=5482","publisher":"ChipsWiki / WikiChip contributors","published":"2019-11-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/EA9002"],"contentSha256":"1eef8402b5c72465f8d78fa6143954c4232528c8734db9f15cb3e36ada3ad684"},{"id":"chipswiki-1295-r4329","title":"ECM3532 — ChipsWiki, revision 4329","url":"https://chipswiki.org/index.php?title=Eta%20compute%2Fecm353x%2Fecm3532&oldid=4329","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Eta_compute/ecm353x/ecm3532"],"contentSha256":"6747353268e27b91bb16e80c18d15ee6950cc494b30925f881b209501474831d"},{"id":"chipswiki-7135-r22516","title":"ET-Minion — ChipsWiki, revision 22516","url":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-minion&oldid=22516","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Esperanto/microarchitectures/et-minion"],"contentSha256":"c72288c68148a9eac6c179502e6e1f6ab608f8b008a8e7246db04ac194ca16b0"},{"id":"chipswiki-7136-r22517","title":"ET-Maxion — ChipsWiki, revision 22517","url":"https://chipswiki.org/index.php?title=Esperanto%2Fmicroarchitectures%2Fet-maxion&oldid=22517","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Esperanto/microarchitectures/et-maxion"],"contentSha256":"133fcd25070ce5c74cd73da032bb34def069a0db5c4efb7ce2f3974e5a0f4e09"},{"id":"chipswiki-8109-r25768","title":"X704-533 — ChipsWiki, revision 25768","url":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F533&oldid=25768","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Exponential_technology/x704/533"],"contentSha256":"4f518835dea6e3d2b74326d61102b5edafe47597b960d21405594745b22fb903"},{"id":"chipswiki-1215-r3802","title":"QorIQ P2010 — ChipsWiki, revision 3802","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2010&oldid=3802","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p2010"],"contentSha256":"f147a7fcc5c17b64c2a1da5ff0f4f126dd04b7a597a268afb75535160783ed5f"},{"id":"chipswiki-31374-r92168","title":"Template:Packages/freescale/te-pbga-ii-689 — revision 92168","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","publisher":"ChipsWiki / WikiChip contributors","published":"2017-10-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Ffreescale%2Fte-pbga-ii-689"],"contentSha256":"c0bca5fd415b6e00ef77f78be2b90915898912b48fe9e9fbea4ea4bab59d8041"},{"id":"chipswiki-3783-r11749","title":"SPARC64 XII — ChipsWiki, revision 11749","url":"https://chipswiki.org/index.php?title=Fujitsu%2Fsparc64%2Fsparc64%20xii&oldid=11749","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Fujitsu/sparc64/sparc64_xii"],"contentSha256":"78acf8fa72eb99901d4b66cd3194a6bf0b8ef5b3be0ee577b79960b213c67b3d"},{"id":"chipswiki-5559-r17991","title":"Post-K — ChipsWiki, revision 17991","url":"https://chipswiki.org/index.php?title=Fujitsu%2Fmicroarchitectures%2Fpost-k&oldid=17991","publisher":"ChipsWiki / WikiChip contributors","published":"2018-06-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Fujitsu/microarchitectures/post-k"],"contentSha256":"bf46c54da62a25db068ca09052afa11c69f944b25de20efb6b674dfcabc50c8f"},{"id":"chipswiki-8094-r25753","title":"QorIQ P1025 — ChipsWiki, revision 25753","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1025&oldid=25753","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1025"],"contentSha256":"31222ca0522fd914729822e1c71adc63ded40b148e6f7f61db6fbcbf7ed8aeef"},{"id":"chipswiki-31376-r92171","title":"Template:Packages/freescale/te-pbga-561 — revision 92171","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-561&oldid=92171","publisher":"ChipsWiki / WikiChip contributors","published":"2017-10-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Ffreescale%2Fte-pbga-561"],"contentSha256":"b6efcdc4343df5a8f9faec0b521b50868f08254609c5321dc002b6ef2a651b45"},{"id":"chipswiki-8095-r25754","title":"QorIQ P1024 — ChipsWiki, revision 25754","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1024&oldid=25754","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1024"],"contentSha256":"79ff925c0f2e1879a3b98db63020c611854059c691c75922ae6d83eb3bcad3c8"},{"id":"chipswiki-8097-r25756","title":"QorIQ P1022 — ChipsWiki, revision 25756","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1022&oldid=25756","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1022"],"contentSha256":"0d64bfd1db68f6036d86c934bfb92e3f2a8aa3110484232cbedd4ac669354ba8"},{"id":"chipswiki-8101-r25760","title":"QorIQ P1016 — ChipsWiki, revision 25760","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1016&oldid=25760","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1016"],"contentSha256":"9c82391ef6b13e38af2be1de7866cee3f009c3fc4da25d14a5baaf0c594aac90"},{"id":"chipswiki-8102-r25761","title":"QorIQ P1015 — ChipsWiki, revision 25761","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1015&oldid=25761","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1015"],"contentSha256":"4c6c0e7877c250a71778fbbb1d372fce993d005716b7990d2da8fc33d9ab2e6f"},{"id":"chipswiki-8105-r25764","title":"QorIQ P1012 — ChipsWiki, revision 25764","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1012&oldid=25764","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1012"],"contentSha256":"bcb0a5f75892537b32d648878c2dbb14a23a4b3ead79db28d43cdb6f923c06c8"},{"id":"chipswiki-8106-r25765","title":"QorIQ P1011 — ChipsWiki, revision 25765","url":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1011&oldid=25765","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Freescale/qoriq/p1011"],"contentSha256":"abe9808f85c66df54fabef9ef9f61e248b568a5495c3b55c590d71cb4cd36032"},{"id":"chipswiki-1035-r2940","title":"Gaudi — ChipsWiki, revision 2940","url":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgaudi&oldid=2940","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Habana/microarchitectures/gaudi"],"contentSha256":"589202a2635e5f1be08899d064ad8b2656e500306dc9d38dcde564d31274f455"},{"id":"chipswiki-1291-r4315","title":"Kunpeng 920-6426 — ChipsWiki, revision 4315","url":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-6426&oldid=4315","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Hisilicon/kunpeng/920-6426"],"contentSha256":"1801eba3544d8de03b1e933c969f897690cb32c90ba3bc4d6c6387c5fdb6bf9d"},{"id":"chipswiki-1535-r4995","title":"Goya — ChipsWiki, revision 4995","url":"https://chipswiki.org/index.php?title=Habana%2Fmicroarchitectures%2Fgoya&oldid=4995","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Habana/microarchitectures/goya"],"contentSha256":"d1bdb31ce0dd1646176adff20b21f45c99586cf67de48f811ec341069fdb2cd7"},{"id":"chipswiki-2171-r7280","title":"Hi1610 — ChipsWiki, revision 7280","url":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1610&oldid=7280","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Hisilicon/kunpeng/hi1610"],"contentSha256":"18a329a2fdd78436b2f5b8ab89457b5bb5595fca1c8d684c270cb81463364839"},{"id":"chipswiki-2566-r8973","title":"Kunpeng 916 (Hi1616) — ChipsWiki, revision 8973","url":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1616&oldid=8973","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Hisilicon/kunpeng/hi1616"],"contentSha256":"2518bfbe8f9799ab5b3b5b3129f6036ae8b35665ef7237be72ac5f9a3391d6eb"},{"id":"chipswiki-5200-r17057","title":"K3V2 — ChipsWiki, revision 17057","url":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2&oldid=17057","publisher":"ChipsWiki / WikiChip contributors","published":"2018-07-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Hisilicon/k3/k3v2"],"contentSha256":"e57b96d7b8aaa4cc07d3621178129cfd077c0fa37c7cd103b5b2d1b8cd1f2310"},{"id":"chipswiki-31402-r92235","title":"Template:Packages/hisilicon/tfbga-576 — revision 92235","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-576&oldid=92235","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fhisilicon%2Ftfbga-576"],"contentSha256":"e09bfc5ae1bcbe0127d213c0d7f0cb2c0aedfcbfd960f51f179c0381cf382fbc"},{"id":"chipswiki-8093-r25747","title":"K3V2E — ChipsWiki, revision 25747","url":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v2e&oldid=25747","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Hisilicon/k3/k3v2e"],"contentSha256":"ee715f8279eec8f5bfeff76a5739ef0dfc5f9edd51b8b2b399d49799241f6614"},{"id":"chipswiki-184-r369","title":"POWER8+ — ChipsWiki, revision 369","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8%2B&oldid=369","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/power8+"],"contentSha256":"1ac783db6ceda4cd3141f65b6e86d6c11c1207545ce0ae2ae744318a1bcd4681"},{"id":"chipswiki-194-r389","title":"POWER9 02CY415 — ChipsWiki, revision 389","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy415&oldid=389","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy415"],"contentSha256":"26431fbc85c003bba8e358046f9c40c4b8323a5b60bbdfab2b3f467093fd3895"},{"id":"chipswiki-825-r2121","title":"POWER11 — ChipsWiki, revision 2121","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower11&oldid=2121","publisher":"ChipsWiki / WikiChip contributors","published":"2021-02-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/power11"],"contentSha256":"8e0868de42358d2f563ee2a09287e6e6b10f18b683c228d31ae6873fc9effcc9"},{"id":"chipswiki-1126-r3350","title":"POWER10 — ChipsWiki, revision 3350","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower10&oldid=3350","publisher":"ChipsWiki / WikiChip contributors","published":"2020-05-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/power10"],"contentSha256":"fe469ed08299279ee3e4eb83bbceae538e06983446e199173b70d3079a53dc6e"},{"id":"chipswiki-1168-r3641","title":"z15 — ChipsWiki, revision 3641","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz15&oldid=3641","publisher":"ChipsWiki / WikiChip contributors","published":"2020-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/z15"],"contentSha256":"edfd1fd230f8ea86df09c2de6b24522c645468d77db0bfd729fad964f398e76d"},{"id":"chipswiki-3939-r12563","title":"POWER9 02CY297 — ChipsWiki, revision 12563","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy297&oldid=12563","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy297"],"contentSha256":"28fef05df5263274906924c222d3fb0e098f187db37b6b0a70e9ce091015ab5f"},{"id":"chipswiki-3940-r12566","title":"POWER9 02CY771 — ChipsWiki, revision 12566","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy771&oldid=12566","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy771"],"contentSha256":"469ecca5aeae21c13820f25adc15b9eb0bbfef735116e66f7ee2952b34b626f7"},{"id":"chipswiki-3941-r12569","title":"POWER9 02CY417 — ChipsWiki, revision 12569","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy417&oldid=12569","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy417"],"contentSha256":"47fffc4be96fe2afcd5d15650140a47dbf2075a54a233024e0149e8a408ac916"},{"id":"chipswiki-3945-r12587","title":"POWER9 02AA986 — ChipsWiki, revision 12587","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02aa986&oldid=12587","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02aa986"],"contentSha256":"8656f7a15423fe816ceec1f84c5435c15f193259f429668e08d3bb5e6de496b1"},{"id":"chipswiki-3946-r12589","title":"POWER9 02CY230 — ChipsWiki, revision 12589","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy230&oldid=12589","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy230"],"contentSha256":"0db8cd54eeb6e2fbee15fc2824de410740bf2a79ddb230c1c8fc425734096425"},{"id":"chipswiki-3947-r12591","title":"POWER9 02CY489 — ChipsWiki, revision 12591","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy489&oldid=12591","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy489"],"contentSha256":"5ff90ead688d5074ade665581e2450c91fa07a99238acf7f2ea42a3834ab0dcd"},{"id":"chipswiki-3950-r12597","title":"POWER9 02CY296 — ChipsWiki, revision 12597","url":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy296&oldid=12597","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/power/02cy296"],"contentSha256":"42c7ca9a76e4b85dfb5fb4b9efca2750eb57d8b69a7078b021b521b6d98d550d"},{"id":"chipswiki-8752-r27150","title":"Cell Broadband Engine Architecture — ChipsWiki, revision 27150","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fcbea&oldid=27150","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/cbea"],"contentSha256":"c4202e37f10c1d240bd27b815023545c077d8e3b94ad780645e17ee69a48c670"},{"id":"chipswiki-9265-r28836","title":"z10 — ChipsWiki, revision 28836","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz10&oldid=28836","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/z10"],"contentSha256":"99d135371f8d48edcf7a15d024f18d8ef4c92caff1601b23404d7902ef9ed9a7"},{"id":"chipswiki-9266-r28844","title":"z990 — ChipsWiki, revision 28844","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz990&oldid=28844","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/z990"],"contentSha256":"bfe1489b812f472d326e3907b3df3318bc3049caa5b1be31bb5e02d2e84cb550"},{"id":"chipswiki-9917-r31532","title":"POWER4 — ChipsWiki, revision 31532","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower4&oldid=31532","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/power4"],"contentSha256":"dc923a1ff3708bbae756eb9cf1eee4d6153bdf16cd433d696c346b58ff44e72a"},{"id":"chipswiki-9919-r31543","title":"POWER5 — ChipsWiki, revision 31543","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower5&oldid=31543","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/power5"],"contentSha256":"8a3004ef6af590caf6164ff0d485b98c96864a58128973c39477fd9ee33263ae"},{"id":"chipswiki-13214-r38677","title":"z12 — ChipsWiki, revision 38677","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz12&oldid=38677","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/z12"],"contentSha256":"6ef11c6fd5403a58766ce306e13a23086b86530424f80b4bcde203becf94ad78"},{"id":"chipswiki-13216-r38680","title":"z9 — ChipsWiki, revision 38680","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz9&oldid=38680","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/z9"],"contentSha256":"4fe42d41a3b76ee6acc30c2b98845b285deea5af7a5ad9802a0bc52b41682a7d"},{"id":"chipswiki-15947-r52538","title":"POWER6+ — ChipsWiki, revision 52538","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6%2B&oldid=52538","publisher":"ChipsWiki / WikiChip contributors","published":"2017-02-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ibm/microarchitectures/power6+"],"contentSha256":"662b012f6a385e91590633c8c7927a89837401dfcdd6a30d666133244a0de90b"},{"id":"chipswiki-678-r1660","title":"i486DX2-66 — ChipsWiki, revision 1660","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-66&oldid=1660","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486dx2-66"],"contentSha256":"ba63d1dcd997573fb26a686ef1de8f7eb94ad8cebf7a8dc9904d1493f46441a7"},{"id":"chipswiki-31416-r92275","title":"Template:Packages/intel/fcbga-1310 — revision 92275","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","publisher":"ChipsWiki / WikiChip contributors","published":"2017-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1310"],"contentSha256":"7a402a0df1cb9a9aae4ed783e2e66221adb13000264296802fe26b3d1f800278"},{"id":"chipswiki-31502-r92564","title":"Template:Packages/intel/fcbga-437 — revision 92564","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","publisher":"ChipsWiki / WikiChip contributors","published":"2017-04-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-437"],"contentSha256":"2269dc94a2140c8fc445cafbb37c691a32608de276b229414abcee1f430e63fb"},{"id":"chipswiki-8075-r25726","title":"Atom 230 — ChipsWiki, revision 25726","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F230&oldid=25726","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/230"],"contentSha256":"0d536389cdea65e791c7c0bb2aa127f0479bfdbc1072263dcea6203f59ea12a3"},{"id":"chipswiki-8078-r25729","title":"i486SX-33 — ChipsWiki, revision 25729","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-33&oldid=25729","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486sx-33"],"contentSha256":"fd3c1c6a8ec4be522957cd76bd44fdf0bfdffa83be1afdb200e650dc360ac92b"},{"id":"chipswiki-8079-r25730","title":"i486SX-25 — ChipsWiki, revision 25730","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-25&oldid=25730","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486sx-25"],"contentSha256":"27c258efab52c3d60598e6c566dfcae4892a704e1d222404aec817da829d9312"},{"id":"chipswiki-8083-r25734","title":"i486SL-25 — ChipsWiki, revision 25734","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-25&oldid=25734","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486sl-25"],"contentSha256":"90f1d5269f54da74b7e665b3f240087aefeed6f1640e4acff9b089acdf7c61a2"},{"id":"chipswiki-8084-r25735","title":"i486SL-20 — ChipsWiki, revision 25735","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-20&oldid=25735","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486sl-20"],"contentSha256":"ec06bdd71a735f9650aa1028741cffebe96971736699aa29dcb2fefa673e652c"},{"id":"chipswiki-8087-r25738","title":"i486DX4-100 — ChipsWiki, revision 25738","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-100&oldid=25738","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486dx4-100"],"contentSha256":"002b819504a9918bbad8f29bb759c17aa4a3e34cf9086e473cb53088693692fd"},{"id":"chipswiki-8089-r25741","title":"i486DX2-40 — ChipsWiki, revision 25741","url":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-40&oldid=25741","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/80486/486dx2-40"],"contentSha256":"5c88e5aea6ab011ef7f9b814d264d844a7837ae66f5583dc9440a2db6bcb49e0"},{"id":"chipswiki-587-r1358","title":"Atom x5-Z8350 — ChipsWiki, revision 1358","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8350&oldid=1358","publisher":"ChipsWiki / WikiChip contributors","published":"2021-10-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-z8350"],"contentSha256":"47867f557f584ad6308923b0a3bcbb6e4336ba2e3e98c82b72102ee797a2b3db"},{"id":"chipswiki-1859-r6393","title":"Atom C3830 — ChipsWiki, revision 6393","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3830&oldid=6393","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3830"],"contentSha256":"5991d34ffa68e07056b54e141814ca7dfe2cbd2b11f1b101771a3c7bf797dbd5"},{"id":"chipswiki-1863-r6399","title":"Atom C3958 — ChipsWiki, revision 6399","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3958&oldid=6399","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3958"],"contentSha256":"286933146c5b48806f1bbb85e0b690ea6fcab9e7120b0373397485494f2257fe"},{"id":"chipswiki-1865-r6401","title":"Atom C3508 — ChipsWiki, revision 6401","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3508&oldid=6401","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3508"],"contentSha256":"84f4287be7fba5c23588f21d818f15734fc30d991948b74dbf576eb6b2345bef"},{"id":"chipswiki-1866-r6402","title":"Atom C3708 — ChipsWiki, revision 6402","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3708&oldid=6402","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3708"],"contentSha256":"5ac0ca62445a13e1943f77611b3b7a8a5e97d7a2ea0c64ea2737f6d2d8d936c8"},{"id":"chipswiki-1868-r6404","title":"Atom C3750 — ChipsWiki, revision 6404","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3750&oldid=6404","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3750"],"contentSha256":"43013742b06ab2c298c26a908f929ae84ea0ccb7e16abe4626ed5916ab6166b6"},{"id":"chipswiki-1870-r6406","title":"Atom C3950 — ChipsWiki, revision 6406","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3950&oldid=6406","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3950"],"contentSha256":"2c07b9bc62150f65c584197ad03acaa9c98da46f133ad2ef5c4ee20da929dafb"},{"id":"chipswiki-8044-r25677","title":"Atom x5-Z8330 — ChipsWiki, revision 25677","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8330&oldid=25677","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-z8330"],"contentSha256":"700b3966493771d29da1dca08c5946337d2f9e26c9368abf84dbfd556aa12584"},{"id":"chipswiki-8047-r25683","title":"Atom x3-C3405 — ChipsWiki, revision 25683","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3405&oldid=25683","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x3/x3-c3405"],"contentSha256":"917fc864439fa24fa2f6e06c96e8f342cf873ccbc77b6f640f7c303cf3c863f7"},{"id":"chipswiki-8049-r25685","title":"Atom x3-C3200RK — ChipsWiki, revision 25685","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3200rk&oldid=25685","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x3/x3-c3200rk"],"contentSha256":"405a719e475f00cc456ec96fd1d696653ca35bfb19e094592317846f9ce31dcd"},{"id":"chipswiki-8050-r25686","title":"Atom x3-C3130 — ChipsWiki, revision 25686","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3130&oldid=25686","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x3/x3-c3130"],"contentSha256":"f4baa4002cf4e44ca0d50d7593f1a8fad516755c5d98fb6ab41751b59cff7138"},{"id":"chipswiki-8051-r25687","title":"Atom Z670 — ChipsWiki, revision 25687","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz670&oldid=25687","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z670"],"contentSha256":"ffc657a850aff555cfd2ca4b8bce0480c5dd4fdc78ab6e95453f4a2328895134"},{"id":"chipswiki-31501-r92563","title":"Template:Packages/intel/fcbga-518 — revision 92563","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","publisher":"ChipsWiki / WikiChip contributors","published":"2017-04-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-518"],"contentSha256":"f1ffbfd4b58b072ffd1c36ac32c15aaab5237364790346fdab8c36464d181f76"},{"id":"chipswiki-8052-r25688","title":"Atom Z650 — ChipsWiki, revision 25688","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz650&oldid=25688","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z650"],"contentSha256":"33babcd60cf72010ed1dc3553daf39d18e13954c1ded72d9f7d8d8e88bf3bcf5"},{"id":"chipswiki-8053-r25689","title":"Atom Z625 — ChipsWiki, revision 25689","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz625&oldid=25689","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z625"],"contentSha256":"44d1b7659130eff4fd4509fc0f2d82f0af610127f62baee9d8b494c9851b80b2"},{"id":"chipswiki-8054-r25690","title":"Atom Z620 — ChipsWiki, revision 25690","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz620&oldid=25690","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z620"],"contentSha256":"f47b82b5540fa7e5570c16617543f1dee939378d7bce98d28cd4b57619697a08"},{"id":"chipswiki-8057-r25693","title":"Atom Z610 — ChipsWiki, revision 25693","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz610&oldid=25693","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z610"],"contentSha256":"7df9d7f13d5ae1ba0f3b54a3e9e4f5f059c2ce8fcc1c1118bb59afb6c93b5990"},{"id":"chipswiki-8059-r25695","title":"Atom Z600 — ChipsWiki, revision 25695","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz600&oldid=25695","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z600"],"contentSha256":"cd64af6d282f05d68d9e041b1475c8a7f23161201e8d9d7ba3d3f4e6b720ab9c"},{"id":"chipswiki-31513-r92656","title":"Template:Packages/intel/fcbga-441 — revision 92656","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","publisher":"ChipsWiki / WikiChip contributors","published":"2017-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-441"],"contentSha256":"d9e160971d00f77069a736b38bb5059ddcefe49a63421da8fd9fbbfec01cbf3b"},{"id":"chipswiki-8069-r25705","title":"Atom Z510P — ChipsWiki, revision 25705","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510p&oldid=25705","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z510p"],"contentSha256":"bc24c223c862bb0f67c3fe2cede35a0784bec2601cd234d42b9f5da1f7320908"},{"id":"chipswiki-8070-r25706","title":"Atom Z510 — ChipsWiki, revision 25706","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510&oldid=25706","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z510"],"contentSha256":"40f92c5807eca9b02a331f2a187226ea99e20839d39d53775d0a8677f4e6910e"},{"id":"chipswiki-8072-r25708","title":"Atom N280 — ChipsWiki, revision 25708","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn280&oldid=25708","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/n280"],"contentSha256":"ae5bbcf68e0f7928965be0b6675de744098763e167b3f01d2a9e7547a2628f13"},{"id":"chipswiki-8073-r25709","title":"Atom N270 — ChipsWiki, revision 25709","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fn270&oldid=25709","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/n270"],"contentSha256":"ccd08ae5ef7e5692bcd28c5fab277fc9b9614ab046d220caf37c77566d679009"},{"id":"chipswiki-2218-r7506","title":"Celeron B730 — ChipsWiki, revision 7506","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb730&oldid=7506","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b730"],"contentSha256":"dd665bac25b7b05508c08f0fb0bc6d15f97b328fb4ffd5da5d2517e5d4b4d4bf"},{"id":"chipswiki-31411-r92269","title":"Template:Packages/intel/pga-988b — revision 92269","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","publisher":"ChipsWiki / WikiChip contributors","published":"2017-08-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Fpga-988b"],"contentSha256":"f223b7379550db60e00e5d4fb482bf9d6729df57c7e79ec776e1157662cc8116"},{"id":"chipswiki-31339-r92076","title":"Template:Packages/intel/fcbga-1023 — revision 92076","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1023"],"contentSha256":"690c4c4c2eed384dc142080ac753f837258622d3bec7ddaf8ef90c6cf43b7ec1"},{"id":"chipswiki-3891-r12302","title":"Celeron 3865U — ChipsWiki, revision 12302","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3865u&oldid=12302","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/3865u"],"contentSha256":"d54d1e81ad0c9747a9c4fe60d200afb9666277b5d165f539539ca6d715f4ebe2"},{"id":"chipswiki-31463-r92408","title":"Template:Packages/intel/fcbga-1356 — revision 92408","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1356"],"contentSha256":"4cfd19a6e261e29b5adadd25f38364e531ab3773b9ed9a5ce082f4a306734da6"},{"id":"chipswiki-6433-r20117","title":"Celeron G3930E — ChipsWiki, revision 20117","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930e&oldid=20117","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3930e"],"contentSha256":"fb55b549499fb920328e18c41522924009b025c86291c980c9c53073673592a2"},{"id":"chipswiki-6924-r21610","title":"Celeron B840 — ChipsWiki, revision 21610","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb840&oldid=21610","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b840"],"contentSha256":"2def2d0ac659ddf7317936e88ecebf36256590d914c90b9da79e1fcb9d371d4f"},{"id":"chipswiki-6925-r21611","title":"Celeron B830 — ChipsWiki, revision 21611","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb830&oldid=21611","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b830"],"contentSha256":"1c300479ac78089d6f56cccda4c9d9116317d130832e139894b564665f7a2f61"},{"id":"chipswiki-6931-r21618","title":"Celeron B710 — ChipsWiki, revision 21618","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb710&oldid=21618","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b710"],"contentSha256":"9b9b35f6217bfaa4dcca1db9fbd1c81c5516fc9392d16959266f47968d5deaf5"},{"id":"chipswiki-6932-r21619","title":"Celeron 897 — ChipsWiki, revision 21619","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F897&oldid=21619","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/897"],"contentSha256":"f0a6c73b944e36f4e6191e91b451d6ea1f16d9447ecfc4481be92e1ee726b1dd"},{"id":"chipswiki-6934-r21621","title":"Celeron 887 — ChipsWiki, revision 21621","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887&oldid=21621","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/887"],"contentSha256":"1b3cecb026923c103da566158153328ea9480ecb420372fa91416009f87ba247"},{"id":"chipswiki-6935-r21622","title":"Celeron 877 — ChipsWiki, revision 21622","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F877&oldid=21622","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/877"],"contentSha256":"7574d6728a66108657f15dcd3dd87f1ca239bc23812aa8897f83063c6b522862"},{"id":"chipswiki-6936-r21623","title":"Celeron 867 — ChipsWiki, revision 21623","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F867&oldid=21623","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/867"],"contentSha256":"c6f1f8e64d06ae1385fc15b8340d799a2599b92cfa71110c5feefec91b26b85f"},{"id":"chipswiki-6938-r21625","title":"Celeron 847E — ChipsWiki, revision 21625","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847e&oldid=21625","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/847e"],"contentSha256":"2baac9cb0c5b017cbb3b4971b97ca2d16bc2f3f96497ae16611d70b83b2207eb"},{"id":"chipswiki-6941-r21628","title":"Celeron 827E — ChipsWiki, revision 21628","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827e&oldid=21628","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/827e"],"contentSha256":"9cc7c976ef378eca8d6e080206695629351bf8dc80244c8f5dbda9a48076ccb4"},{"id":"chipswiki-6944-r21631","title":"Celeron 807UE — ChipsWiki, revision 21631","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807ue&oldid=21631","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/807ue"],"contentSha256":"4e71d94b573bf06329c412da3d698a24c11ab79adb1666e91ac5370167179ed8"},{"id":"chipswiki-6946-r21633","title":"Celeron 797 — ChipsWiki, revision 21633","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F797&oldid=21633","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/797"],"contentSha256":"e04326bd4b441d5c26a3959b232d920799a38ea0bca81e6b8e9d615c37ba4518"},{"id":"chipswiki-6947-r21634","title":"Celeron 787 — ChipsWiki, revision 21634","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F787&oldid=21634","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/787"],"contentSha256":"b464b9466f02a8bc75b3deccce0a0e1a2353c9886c5dcd14bd79bb608c2d654a"},{"id":"chipswiki-31379-r92181","title":"Template:Packages/intel/fclga-1151 — revision 92181","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","publisher":"ChipsWiki / WikiChip contributors","published":"2017-10-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffclga-1151"],"contentSha256":"bb53e1fc289da3604b34d0cb074c908d9e9772f2d2ee1db38c7e68ea495e7642"},{"id":"chipswiki-8029-r25633","title":"Celeron G3902E — ChipsWiki, revision 25633","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3902e&oldid=25633","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3902e"],"contentSha256":"715ec5d9e3f320c81f2ecae7b38b637c6ae2eeddef79613c2bcd4721d6a5b926"},{"id":"chipswiki-31464-r92410","title":"Template:Packages/intel/fcbga-1440 — revision 92410","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1440"],"contentSha256":"bc5146b75dca42ead40430b36ba257a6a251a1882c3639a875df189e6255f98d"},{"id":"chipswiki-8031-r25635","title":"Celeron G3900T — ChipsWiki, revision 25635","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900t&oldid=25635","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3900t"],"contentSha256":"77676526c5abbd8a671664cf4ef476fa82a78aec902497e3325a1ef2a55d983c"},{"id":"chipswiki-8035-r25666","title":"Celeron 3965U — ChipsWiki, revision 25666","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965u&oldid=25666","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/3965u"],"contentSha256":"2d41d333fff3496457ff55541dfeae993dff7222b76219c657d935ca92465b25"},{"id":"chipswiki-8036-r25667","title":"Celeron 3955U — ChipsWiki, revision 25667","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3955u&oldid=25667","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/3955u"],"contentSha256":"fa4e4575d6a7a67e191994ade606ac964788aac3e3d210c88c83299d2cecd590"},{"id":"chipswiki-8039-r25671","title":"Atom x7-Z8750 — ChipsWiki, revision 25671","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8750&oldid=25671","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x7/z8750"],"contentSha256":"df1063935456ff191e0ab0b27258c1830a58fffebe25a6524f6b02ebc56ed477"},{"id":"chipswiki-8040-r25672","title":"Atom x7-Z8700 — ChipsWiki, revision 25672","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fz8700&oldid=25672","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x7/z8700"],"contentSha256":"5c2a93b0b5f7ff135468b4d693ba553230af7738659cf417ca4465cc82effbf6"},{"id":"chipswiki-8042-r25674","title":"Atom x5-Z8550 — ChipsWiki, revision 25674","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8550&oldid=25674","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-z8550"],"contentSha256":"29c30614239d4075fb5d03394dce0f66899bf2d73e076d54b0e79252822555ef"},{"id":"chipswiki-31338-r92075","title":"Template:Packages/intel/fcbga-1090 — revision 92075","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1090"],"contentSha256":"256a3b4351e3e24c418e4d059c1569c31f5e57fbe76fe3e1f46a6a6ca2495f05"},{"id":"chipswiki-917-r2516","title":"Celeron J4005 — ChipsWiki, revision 2516","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4005&oldid=2516","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/j4005"],"contentSha256":"065439f361f2f8acc46b159819625f6457b5d0e25e52f76da32a72db31114783"},{"id":"chipswiki-1016-r2874","title":"Celeron J4105 — ChipsWiki, revision 2874","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj4105&oldid=2874","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/j4105"],"contentSha256":"2c20769baec90a5515c49a49389fdd087640d75699c51e8c3a9d7a856a826f57"},{"id":"chipswiki-1238-r3947","title":"Core i3-1000G4 — ChipsWiki, revision 3947","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g4&oldid=3947","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-1000g4"],"contentSha256":"91c620a3113c019121adf8d0f42bde67e062c0277f5508e0bdeb06654ed25514"},{"id":"chipswiki-2853-r9577","title":"Celeron G4930 — ChipsWiki, revision 9577","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930&oldid=9577","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g4930"],"contentSha256":"eca3237d98f4ef8f6532302c1b7cc38d5cff68ffe83b4f887a46ea592d5aa8a8"},{"id":"chipswiki-6431-r20111","title":"Celeron G3930T — ChipsWiki, revision 20111","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930t&oldid=20111","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3930t"],"contentSha256":"94ec0ffcdec532ae50c00b73de96e7ce5fcba90ec0dfd2550e59256aeb299d94"},{"id":"chipswiki-6446-r20179","title":"Celeron G4920 — ChipsWiki, revision 20179","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4920&oldid=20179","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g4920"],"contentSha256":"2bb88473b96a87fca3ccd8771189802d11ad41b86ac8e3cdae78327b3afa49c4"},{"id":"chipswiki-6857-r21409","title":"Celeron N3000 — ChipsWiki, revision 21409","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3000&oldid=21409","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/n3000"],"contentSha256":"c438c788456ed61cfadefadd06f78ebbf50c4c6838e45fccbc06b09006305ce6"},{"id":"chipswiki-6859-r21412","title":"Celeron J3160 — ChipsWiki, revision 21412","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3160&oldid=21412","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/j3160"],"contentSha256":"87db00e6663e96a05b5074e129d85429c0c09f117433b477283d935b1d09a2b8"},{"id":"chipswiki-6865-r21424","title":"Celeron N3160 — ChipsWiki, revision 21424","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3160&oldid=21424","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/n3160"],"contentSha256":"dc96d2c83d2b71d0d4fe2699fc89d4b738cef62054aae0d076f5aec88871ad1f"},{"id":"chipswiki-8015-r25596","title":"Core i3-2328M — ChipsWiki, revision 25596","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2328m&oldid=25596","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2328m"],"contentSha256":"766b0317b5fd55e12ca0bbc6c412d4b91bcf8517e83571e8f1beaa769df75091"},{"id":"chipswiki-8016-r25597","title":"Core i3-2312M — ChipsWiki, revision 25597","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2312m&oldid=25597","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2312m"],"contentSha256":"24cb1a2ad7118869924a14c2a6aea35692776929499e8eaf44113ffa1d18ee00"},{"id":"chipswiki-8017-r25598","title":"Core i3-2310M — ChipsWiki, revision 25598","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310m&oldid=25598","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2310m"],"contentSha256":"dcf10a3d8b81fc97c4efd5e6449e4babb7d227fe989ba7177f7161cd14948cde"},{"id":"chipswiki-8020-r25602","title":"Core i3-6120T — ChipsWiki, revision 25602","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6120t&oldid=25602","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/6120t"],"contentSha256":"0aca6e60c9814357a24af5431d8e340a315ecb38c8c50956f0385458ab4a97d6"},{"id":"chipswiki-31577-r92963","title":"Template:Packages/intel/bga-1288 — revision 92963","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","publisher":"ChipsWiki / WikiChip contributors","published":"2016-12-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Fbga-1288"],"contentSha256":"d172922a320e4c7c5506e11a270eb7b27f7c2f363aa9a4286672a9e5521fab38"},{"id":"chipswiki-8024-r25606","title":"Celeron P4600 — ChipsWiki, revision 25606","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4600&oldid=25606","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/p4600"],"contentSha256":"4814a9501ad0b193023fea15a4d5912e8f9aac498f03bddba1ad23d2a92cb78d"},{"id":"chipswiki-31578-r92969","title":"Template:Packages/intel/rpga-988a — revision 92969","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","publisher":"ChipsWiki / WikiChip contributors","published":"2016-12-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Frpga-988a"],"contentSha256":"e8d6d9da975af29ad9350349cb1389a7eefeaa0559fd9057d9d1fc81d7789cc9"},{"id":"chipswiki-8025-r25607","title":"Celeron P4505 — ChipsWiki, revision 25607","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4505&oldid=25607","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/p4505"],"contentSha256":"a82137efb189e6138671fa527b5ade27565d79b1354c6a09a463413415db225a"},{"id":"chipswiki-4254-r13746","title":"Core i3-7101TE — ChipsWiki, revision 13746","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101te&oldid=13746","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7101te"],"contentSha256":"2a64a7888194e7ff256f1fac517e89abcce7d6ad738c19dbb4faed1b8469564d"},{"id":"chipswiki-4502-r14632","title":"Core i3-7100 — ChipsWiki, revision 14632","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100&oldid=14632","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7100"],"contentSha256":"21919068ff054b0c03413e2aa43396d86d01e3fffe819b2f24fa5d9ba729e73f"},{"id":"chipswiki-6362-r19754","title":"Core i3-7020U — ChipsWiki, revision 19754","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7020u&oldid=19754","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7020u"],"contentSha256":"cbd504b09e131731ebe6c1afca2c98474e432259e01ece93c458968fd38b9ab7"},{"id":"chipswiki-7974-r25548","title":"Core i3-7100U — ChipsWiki, revision 25548","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100u&oldid=25548","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7100u"],"contentSha256":"9b3aaf2c806290733f380ddca75f91dd2e345d9c9a6865fa347e39375ed61500"},{"id":"chipswiki-7976-r25553","title":"Core i3-7007U — ChipsWiki, revision 25553","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7007u&oldid=25553","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7007u"],"contentSha256":"fd3bb51a00162f7656b8ca57111dbc7cad961ba97a480413a33fe09be21ef0a9"},{"id":"chipswiki-7978-r25555","title":"Core i3-6300T — ChipsWiki, revision 25555","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300t&oldid=25555","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6300t"],"contentSha256":"aebfc25559792c12e96b6af39f8665e0ed29295c19fa788c7343b17a50d3aa6d"},{"id":"chipswiki-7980-r25557","title":"Core i3-6167U — ChipsWiki, revision 25557","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6167u&oldid=25557","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6167u"],"contentSha256":"9ee88f6e043d6a3db424be529e26b546ef13c8e01e84146a8e0a32ecb0d92669"},{"id":"chipswiki-7981-r25558","title":"Core i3-6157U — ChipsWiki, revision 25558","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6157u&oldid=25558","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6157u"],"contentSha256":"bd5a426686758ee9661811d967c03f2bfa3590e04b9c668ef277d3ce381f5997"},{"id":"chipswiki-7982-r25559","title":"Core i3-6102E — ChipsWiki, revision 25559","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6102e&oldid=25559","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6102e"],"contentSha256":"ea0354bfa22c87762b26075f61bc15cf5256d78a03d9ac9511a2ec90198adcb3"},{"id":"chipswiki-7983-r25560","title":"Core i3-6100U — ChipsWiki, revision 25560","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100u&oldid=25560","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6100u"],"contentSha256":"a48aeddad24187eed31f600909a0fb21b6639b65310051a5633122c697ce0b7c"},{"id":"chipswiki-7984-r25561","title":"Core i3-6100TE — ChipsWiki, revision 25561","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100te&oldid=25561","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6100te"],"contentSha256":"8ccd10573cea0163ed496b11432f9312cad652293fc859082d87de506668bb51"},{"id":"chipswiki-7985-r25562","title":"Core i3-6100T — ChipsWiki, revision 25562","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100t&oldid=25562","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6100t"],"contentSha256":"de00a3b91396908545e9e71e95108c505fcd066ad5fa7963a8dad166523e9a92"},{"id":"chipswiki-7986-r25564","title":"Core i3-6100E — ChipsWiki, revision 25564","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100e&oldid=25564","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6100e"],"contentSha256":"08313ef0701c8395a2a96e0b9710e250580da3afb6bdc761c861ed420d972288"},{"id":"chipswiki-7996-r25577","title":"Core i3-2395M — ChipsWiki, revision 25577","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2395m&oldid=25577","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2395m"],"contentSha256":"d672f616dd701a0bc89ccfe942dbdb62026261d506670a7dad765f7b2db71e99"},{"id":"chipswiki-7997-r25578","title":"Core i3-2394M — ChipsWiki, revision 25578","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2394m&oldid=25578","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2394m"],"contentSha256":"508cec2c494133e25e2b4667fbba481522e7ba74ef655480c3db1d36a72b44e6"},{"id":"chipswiki-7998-r25579","title":"Core i3-2393M — ChipsWiki, revision 25579","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2393m&oldid=25579","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2393m"],"contentSha256":"b4ecc8f372ea78fc596bf7b25198195fbf3cfdc12e2cf0876144c44acb203697"},{"id":"chipswiki-7999-r25580","title":"Core i3-2390M — ChipsWiki, revision 25580","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2390m&oldid=25580","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2390m"],"contentSha256":"e015578f2f204e56b7fb0c4c67e7a5070364170d6af20ebbe4f9f7f8b6b6e624"},{"id":"chipswiki-8001-r25582","title":"Core i3-2375M — ChipsWiki, revision 25582","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2375m&oldid=25582","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2375m"],"contentSha256":"518edabe25f7b0bd75d916887a03ba9aa682d2bdbdbecc1cb12d3cecd2893550"},{"id":"chipswiki-8002-r25583","title":"Core i3-2370M — ChipsWiki, revision 25583","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370m&oldid=25583","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2370m"],"contentSha256":"0204799a0589aae29f4c8e2a88b86f335c227358651d7657d2588cfd1dcbc9e5"},{"id":"chipswiki-8003-r25584","title":"Core i3-2370LM — ChipsWiki, revision 25584","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2370lm&oldid=25584","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2370lm"],"contentSha256":"14f468efa373583f9fdc45aecb82e9d829a8577095ddef16959387081884c69c"},{"id":"chipswiki-8004-r25585","title":"Core i3-2367M — ChipsWiki, revision 25585","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2367m&oldid=25585","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2367m"],"contentSha256":"aabaefcd7c04d5a1dff15f733535175720ced0364a780ad377db988a6258ee4d"},{"id":"chipswiki-8011-r25592","title":"Core i3-2340UE — ChipsWiki, revision 25592","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2340ue&oldid=25592","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2340ue"],"contentSha256":"955ac01d1e08c11454c95ed42c58b7c649a35260f4aaf01478bea9b394bb3a4b"},{"id":"chipswiki-8012-r25593","title":"Core i3-2332M — ChipsWiki, revision 25593","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2332m&oldid=25593","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2332m"],"contentSha256":"f0e1fe758e04dd92686bc2166f86490d6b1d3f93044cc17f257499b175e82bc3"},{"id":"chipswiki-796-r2001","title":"Core i3-7300 — ChipsWiki, revision 2001","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300&oldid=2001","publisher":"ChipsWiki / WikiChip contributors","published":"2021-03-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7300"],"contentSha256":"fc37175262b975f448bf57bb0ca1945987c061cd05364c1150a5fbd40aae1958"},{"id":"chipswiki-1241-r3951","title":"Core i5-1030G4 — ChipsWiki, revision 3951","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g4&oldid=3951","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-1030g4"],"contentSha256":"d3f005246f01e9ef9b3b0358b47324b62b50ba2b8e9ee18356ee392ebc171b3a"},{"id":"chipswiki-2843-r9541","title":"Core i3-9300T — ChipsWiki, revision 9541","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9300t&oldid=9541","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-9300t"],"contentSha256":"902ea2388182a15f83c05c7caacca9c332f04c10332e599d16ef2befcfa677c0"},{"id":"chipswiki-3986-r12827","title":"Core i3-8100F — ChipsWiki, revision 12827","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100f&oldid=12827","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8100f"],"contentSha256":"a02ce1eb6a89f106583862214383a65b23b4faa51fc35054e3602d7653c6d7ad"},{"id":"chipswiki-5450-r17746","title":"Core i3-8000T — ChipsWiki, revision 17746","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000t&oldid=17746","publisher":"ChipsWiki / WikiChip contributors","published":"2018-07-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8000t"],"contentSha256":"041c78ccc7e85f40431fcdfe76b98722adb0515fc1a71562e804c1bee7c7092c"},{"id":"chipswiki-5558-r17978","title":"Core i3-8120 — ChipsWiki, revision 17978","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120&oldid=17978","publisher":"ChipsWiki / WikiChip contributors","published":"2018-06-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8120"],"contentSha256":"393717638d5b23dae3089931f70be789b2bf24b2f6f51ea2f21cb612250d340f"},{"id":"chipswiki-5568-r18075","title":"Core i3-8121U — ChipsWiki, revision 18075","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8121u&oldid=18075","publisher":"ChipsWiki / WikiChip contributors","published":"2018-06-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8121u"],"contentSha256":"ae93637bf91afa802daebd22e1ea034368bc43c0357b087f072c6f54c733f127"},{"id":"chipswiki-6363-r19769","title":"Core i3-7310U — ChipsWiki, revision 19769","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310u&oldid=19769","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7310u"],"contentSha256":"8e07d0f3c44e5d211587f753f088709eefe78c258b817867931703bf22969db3"},{"id":"chipswiki-6424-r20049","title":"Core i3-8320T — ChipsWiki, revision 20049","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320t&oldid=20049","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8320t"],"contentSha256":"7a988d14fcf1600ff8b43416bb01056a7bd168e46531ab4dcf1a087cb8da9920"},{"id":"chipswiki-6425-r20052","title":"Core i3-8020T — ChipsWiki, revision 20052","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020t&oldid=20052","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8020t"],"contentSha256":"cf9954bc9cf4960b93543225991e1ccf0ed724585ac0fb9f75cb7aa4d32b3984"},{"id":"chipswiki-6452-r20191","title":"Core i3-8100T — ChipsWiki, revision 20191","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100t&oldid=20191","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8100t"],"contentSha256":"453f188d7e3326cf6978ad255a0d7848af80c330643847d98f98559cb9e61441"},{"id":"chipswiki-6453-r20193","title":"Core i3-8300T — ChipsWiki, revision 20193","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300t&oldid=20193","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8300t"],"contentSha256":"a5ec4047a4497b4a9d790862cc85b0d06f40326e9c1b7d4aee1214818ab392da"},{"id":"chipswiki-6454-r20195","title":"Core i3-8300 — ChipsWiki, revision 20195","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8300&oldid=20195","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8300"],"contentSha256":"4d607c72c7976f720ccf2cf53ec855ae12575f85cbfaa0a28b7a32a7d480ad4f"},{"id":"chipswiki-6855-r21375","title":"Core i3-8130U — ChipsWiki, revision 21375","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8130u&oldid=21375","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8130u"],"contentSha256":"a8a3314c7b66181853dc62c3a714418a9565a2f31f2e32076464e100e3879fd1"},{"id":"chipswiki-7963-r25533","title":"Core i3-7340 — ChipsWiki, revision 25533","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7340&oldid=25533","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7340"],"contentSha256":"70f3460119c0d1d01eeac44e191ba63096488a518c841d5203b3254d472a7e48"},{"id":"chipswiki-7964-r25534","title":"Core i3-7320T — ChipsWiki, revision 25534","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320t&oldid=25534","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7320t"],"contentSha256":"13f3d0cc4a165a2918143c32853bd98f2f1340934a80e8d7067b32350ebf1182"},{"id":"chipswiki-7966-r25537","title":"Core i3-7310T — ChipsWiki, revision 25537","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7310t&oldid=25537","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7310t"],"contentSha256":"4ade128a9146d02630edb7d206dbb7d8daf338c2408ecdc3e8d2542d5665dc76"},{"id":"chipswiki-7969-r25541","title":"Core i3-7130U — ChipsWiki, revision 25541","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7130u&oldid=25541","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7130u"],"contentSha256":"da5edd9b7b64df5056ea7a8d64ade92f7355de27ce72d824e6c0fd4c1e9aef41"},{"id":"chipswiki-7970-r25542","title":"Core i3-7120T — ChipsWiki, revision 25542","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120t&oldid=25542","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7120t"],"contentSha256":"38e7c0126b16688091ecb4f0a1e34b6a7bff98ae499356903601d0c80f7863a7"},{"id":"chipswiki-7972-r25544","title":"Core i3-7110U — ChipsWiki, revision 25544","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7110u&oldid=25544","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7110u"],"contentSha256":"e21581913e66d659974874f97c609a973791c0acd31265a1266c7fc7a302297a"},{"id":"chipswiki-1101-r3263","title":"Core i5-2477M — ChipsWiki, revision 3263","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2477m&oldid=3263","publisher":"ChipsWiki / WikiChip contributors","published":"2020-06-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2477m"],"contentSha256":"95687cc0165fb17dae26f318d5e023e9aad0536f72e3ffec7916351a2892afdc"},{"id":"chipswiki-1442-r4880","title":"Core i5-2415M — ChipsWiki, revision 4880","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2415m&oldid=4880","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2415m"],"contentSha256":"2801b10796a5a8fca92be22506efcfd465afdfc2ac7556f7f34394f7b30423bf"},{"id":"chipswiki-2041-r6903","title":"Core i5-560M — ChipsWiki, revision 6903","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560m&oldid=6903","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-560m"],"contentSha256":"958386f67ef3ad934a461ee7b54b676eeac38f173920a123e62ccb87b5469e4a"},{"id":"chipswiki-3787-r11778","title":"Core i5-520M — ChipsWiki, revision 11778","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520m&oldid=11778","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-520m"],"contentSha256":"6596258e96280caea4fb3c52a187b32537fe0a6e5dc8b0bd432d024bda150bdb"},{"id":"chipswiki-3958-r12645","title":"Core i5-6198DU — ChipsWiki, revision 12645","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6198du&oldid=12645","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6198du"],"contentSha256":"2abd063452a3db094f0bc17d4f4c60ae13f0025fa62c7aa32c778aa2e70c5ca2"},{"id":"chipswiki-7927-r25467","title":"Core i5-6287U — ChipsWiki, revision 25467","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6287u&oldid=25467","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6287u"],"contentSha256":"13d6bf68e24db7671af90dec7358c916e446bf13a9c00a553d2b67b006ed78bc"},{"id":"chipswiki-7931-r25473","title":"Core i5-5675R — ChipsWiki, revision 25473","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5675r&oldid=25473","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-5675r"],"contentSha256":"d5b59ad44322e6cf9fe4f556237f5b8be2e628140e3a3fc12f99cf2d426f0542"},{"id":"chipswiki-31462-r92407","title":"Template:Packages/intel/fcbga-1364 — revision 92407","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1364"],"contentSha256":"cf4a3b0b71a20a1a16a91e2e697b962e776b409f8b2f076ad4e28f56a64fba36"},{"id":"chipswiki-7933-r25477","title":"Core i5-5575R — ChipsWiki, revision 25477","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5575r&oldid=25477","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-5575r"],"contentSha256":"838432919aa5d3d79a99cbcc82e14948345bac080d54bd70cdb3379ce4df3073"},{"id":"chipswiki-7935-r25480","title":"Core i5-5350H — ChipsWiki, revision 25480","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-5350h&oldid=25480","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-5350h"],"contentSha256":"2e2ca87b664221511c519c7480896628ca58c935aa03d07d9c39ed5d1e2b665a"},{"id":"chipswiki-7936-r25481","title":"Core i5-520UM — ChipsWiki, revision 25481","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520um&oldid=25481","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-520um"],"contentSha256":"cd6a58a4164d0a81342c8232ad8630857ca093fd39a6c93c369d96aeed8acd0c"},{"id":"chipswiki-7943-r25490","title":"Core i5-430UM — ChipsWiki, revision 25490","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430um&oldid=25490","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-430um"],"contentSha256":"0e94e46e544183b70a6193102c51e63a3b1ec6739ea977abd6eb4772015d257b"},{"id":"chipswiki-7944-r25492","title":"Core i5-2580M — ChipsWiki, revision 25492","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2580m&oldid=25492","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2580m"],"contentSha256":"404b4c8b6bdb1404b5628e6e178a6cbc17c6028c52613b94782f3593a91e3b36"},{"id":"chipswiki-7947-r25495","title":"Core i5-2557M — ChipsWiki, revision 25495","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2557m&oldid=25495","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2557m"],"contentSha256":"a1db43227c7f1361259aeef94802db0327b0210bb8ac220ebeefeaa51dfbe20f"},{"id":"chipswiki-7949-r25497","title":"Core i5-2540M — ChipsWiki, revision 25497","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540m&oldid=25497","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2540m"],"contentSha256":"c2aa86f70bf9786f5cabd5680dfbf6c4a68da67e86bf98bbe304944a7c40285b"},{"id":"chipswiki-7951-r25499","title":"Core i5-2537M — ChipsWiki, revision 25499","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2537m&oldid=25499","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2537m"],"contentSha256":"102620cfa40a22efe380bc2f8aeb5418eb25479aba3ef86a5ef689db9119ffcb"},{"id":"chipswiki-7954-r25502","title":"Core i5-2510E — ChipsWiki, revision 25502","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2510e&oldid=25502","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2510e"],"contentSha256":"cd02e5d79f017d4ccc3f249e9022e35202f3915461af3d010da20163ca321ad3"},{"id":"chipswiki-7957-r25505","title":"Core i5-2487M — ChipsWiki, revision 25505","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2487m&oldid=25505","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2487m"],"contentSha256":"9c5e02a8d0e28f177297158dda9689f6e62e2727b8e394ad3c08f84317e32085"},{"id":"chipswiki-7959-r25508","title":"Core i5-2467M — ChipsWiki, revision 25508","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2467m&oldid=25508","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2467m"],"contentSha256":"396137e8aa07a366bb470947385479917fef5ac494d168fdc0513a4b49e93377"},{"id":"chipswiki-7961-r25511","title":"Core i5-2430M — ChipsWiki, revision 25511","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2430m&oldid=25511","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-2430m"],"contentSha256":"799111b74367612e74a35c7d93583f1c316f00c80e32dcd85a33a028c898807c"},{"id":"chipswiki-278-r563","title":"Core i5-7200U — ChipsWiki, revision 563","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7200u&oldid=563","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-7200u"],"contentSha256":"1b666994d48bf9f42323ce1ab2ba7c708c72b89bb51d632db3542646a02dfb29"},{"id":"chipswiki-783-r1922","title":"Core i5-8250U — ChipsWiki, revision 1922","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8250u&oldid=1922","publisher":"ChipsWiki / WikiChip contributors","published":"2021-04-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8250u"],"contentSha256":"f454d550cb8052eb796b78136f58edfc0ea2f67aff7c2761db72cc61fda1b34e"},{"id":"chipswiki-2925-r9783","title":"Core i5-8365U — ChipsWiki, revision 9783","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8365u&oldid=9783","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8365u"],"contentSha256":"c8dec16d7c37dc285ff012b716327525d6534c57f952231edd3fd60cc377fa3f"},{"id":"chipswiki-3698-r11040","title":"Core i5-8310Y — ChipsWiki, revision 11040","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8310y&oldid=11040","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8310y"],"contentSha256":"710e11de309c99f69c7094632ef88ab8eb3065f6035bb652a236cccb68b3543b"},{"id":"chipswiki-3975-r12662","title":"Core i5-6440HQ — ChipsWiki, revision 12662","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440hq&oldid=12662","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6440hq"],"contentSha256":"ff2c313120e31053f7a4bd6826656307aa344ecb2d61a86ecda7ea24aab720bf"},{"id":"chipswiki-4491-r14592","title":"Core i5-8210Y — ChipsWiki, revision 14592","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8210y&oldid=14592","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8210y"],"contentSha256":"028144c328eee950ac10d208cd46816799ecc979d5d2e90b10e46e1e3ce42291"},{"id":"chipswiki-4977-r16099","title":"Core i5-7Y54 — ChipsWiki, revision 16099","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y54&oldid=16099","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-7y54"],"contentSha256":"9a996c81a202d0becad56e883adbbd910548cf44fe45251153a8c353d8ff1684"},{"id":"chipswiki-6418-r20018","title":"Core i5-7440HQ — ChipsWiki, revision 20018","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440hq&oldid=20018","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-7440hq"],"contentSha256":"4cf712a58a2279e19b5477cd7b37f8788e25ddd08e501362841754f3d82bdbc8"},{"id":"chipswiki-6419-r20019","title":"Core i5-7440EQ — ChipsWiki, revision 20019","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7440eq&oldid=20019","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-7440eq"],"contentSha256":"8d73dcf26775dcb20d2d7827d262e477e05c07e936e146ff80c5759735c81ac5"},{"id":"chipswiki-6578-r20845","title":"Core i5-8300H — ChipsWiki, revision 20845","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8300h&oldid=20845","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8300h"],"contentSha256":"4a734507577512ab716ea933320b1b6ddc14fb83f569baaa227d033a889bf773"},{"id":"chipswiki-7911-r25449","title":"Core i5-6685R — ChipsWiki, revision 25449","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6685r&oldid=25449","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6685r"],"contentSha256":"8f3d6a4b1162116f6cfd80cbba21753db578985a3fc70e31e5f86ebb2de4a51a"},{"id":"chipswiki-7912-r25450","title":"Core i5-6600T — ChipsWiki, revision 25450","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6600t&oldid=25450","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6600t"],"contentSha256":"eedd3eece9dd84b42ff90b8995c6fc69b1c26ec47c4bd5bad65c94b966e5324b"},{"id":"chipswiki-7922-r25461","title":"Core i5-6400T — ChipsWiki, revision 25461","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6400t&oldid=25461","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6400t"],"contentSha256":"c728925a4756ef643348f7c61277ab326c0ede84aa9e346923ddf9fdf760e9ec"},{"id":"chipswiki-7924-r25463","title":"Core i5-6360U — ChipsWiki, revision 25463","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6360u&oldid=25463","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6360u"],"contentSha256":"cc40bced9b86bc2dd4ccb32aae1a9cba2a7547b5f34c92f75c7579446fd00c4b"},{"id":"chipswiki-355-r749","title":"Core i5-9300H — ChipsWiki, revision 749","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9300h&oldid=749","publisher":"ChipsWiki / WikiChip contributors","published":"2022-05-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-9300h"],"contentSha256":"eacc5ddc24506c3d4d6a1031e71349cfa03afe3d3e3f81d8abfd865b550ec9fa"},{"id":"chipswiki-836-r2183","title":"Core i7-1068G7 — ChipsWiki, revision 2183","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1068g7&oldid=2183","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-1068g7"],"contentSha256":"d9b6f748c536816482498fad926b0e4f755b8bc756ebc6930c011f64eda4a7cc"},{"id":"chipswiki-976-r2766","title":"Core i5-8500B — ChipsWiki, revision 2766","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8500b&oldid=2766","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8500b"],"contentSha256":"0fd59d1c56b901bde2e0b902b620bb0625ad8631d763efdd754f63e4e0a5cec5"},{"id":"chipswiki-989-r2831","title":"Core i7-1065G7 — ChipsWiki, revision 2831","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1065g7&oldid=2831","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-1065g7"],"contentSha256":"865c5f7ed955fd9834f6a56e00341829f807dfd0f43d1d09ab1df1b118daebb9"},{"id":"chipswiki-1239-r3949","title":"Core i7-1060G7 — ChipsWiki, revision 3949","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-1060g7&oldid=3949","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-1060g7"],"contentSha256":"c2f669753865164935cdbb88838f25cab9865c27729abb3881b6634cc37239b7"},{"id":"chipswiki-1620-r5488","title":"Core i5-9500T — ChipsWiki, revision 5488","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9500t&oldid=5488","publisher":"ChipsWiki / WikiChip contributors","published":"2019-11-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-9500t"],"contentSha256":"9f0b623b180bbe2fdc1605122c2cda61d71070fb1b99707280af988068defd42"},{"id":"chipswiki-4957-r16040","title":"Core i5-8400B — ChipsWiki, revision 16040","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400b&oldid=16040","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8400b"],"contentSha256":"d8a1da89288e8b46f5aa70929a0faeb69ba68a28642c12286eb97a8fa9d5f670"},{"id":"chipswiki-4964-r16058","title":"Core i5-8600T — ChipsWiki, revision 16058","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8600t&oldid=16058","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8600t"],"contentSha256":"4284cca5638f60c4e4bb9dece2de0166b175ce83fda7326e41a2d87388720860"},{"id":"chipswiki-6577-r20840","title":"Core i5-8400H — ChipsWiki, revision 20840","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400h&oldid=20840","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8400h"],"contentSha256":"7a0edcffadc397c3c5de029a641d1e4d1e88d99f5ac84ad90396c9c809d0cf81"},{"id":"chipswiki-7890-r25394","title":"Core i7-2655LE — ChipsWiki, revision 25394","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655le&oldid=25394","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2655le"],"contentSha256":"8897bd31e2492665a8bbd3d960a6126472d112a83e5692f196c6050884290c4b"},{"id":"chipswiki-7891-r25395","title":"Core i7-2649M — ChipsWiki, revision 25395","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2649m&oldid=25395","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2649m"],"contentSha256":"5b1af7935574d11afbd8262d225ab043c32714f0682a45c5b46cad55f7fa17f9"},{"id":"chipswiki-31408-r92251","title":"Template:Packages/intel/fcbga-1224 — revision 92251","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1224"],"contentSha256":"6c882a72b40b8ddb66e582c17b09dc73287a46af805625092c703e3a491ab32f"},{"id":"chipswiki-7895-r25399","title":"Core i7-2630QM — ChipsWiki, revision 25399","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2630qm&oldid=25399","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2630qm"],"contentSha256":"9671e4e3a65de87eefcf9bd5f6e7ed61d5f97f4f3f2753e4e2c9ae8daed4abf0"},{"id":"chipswiki-7896-r25400","title":"Core i7-2629M — ChipsWiki, revision 25400","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2629m&oldid=25400","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2629m"],"contentSha256":"435112175aa80c86351bb4cf0a5cf26269ca470942c0a0af1bcea5a3eae86309"},{"id":"chipswiki-7898-r25402","title":"Core i7-2620M — ChipsWiki, revision 25402","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2620m&oldid=25402","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2620m"],"contentSha256":"d2545c7e3d139d78f3baad01b4b3e6d815dcf29bf53f21b80be2a6cf679cb89c"},{"id":"chipswiki-7902-r25406","title":"Core i7-2535QM — ChipsWiki, revision 25406","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2535qm&oldid=25406","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2535qm"],"contentSha256":"2e1bff9fb1093e0b57584150767d8bb4e86727e27ffb05bf43350875c66be7e3"},{"id":"chipswiki-5186-r16929","title":"Core i7-2860QM — ChipsWiki, revision 16929","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2860qm&oldid=16929","publisher":"ChipsWiki / WikiChip contributors","published":"2018-07-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2860qm"],"contentSha256":"896496d45e74e23ff2bad0ba3f6349300fe26d9380e3824f4401cbad3d53efee"},{"id":"chipswiki-7563-r24569","title":"Core i7-4870HQ — ChipsWiki, revision 24569","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4870hq&oldid=24569","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-4870hq"],"contentSha256":"5beef845e0738fac5ca253b1a635439b5965dea8bda7c21630b5e38a692e128d"},{"id":"chipswiki-7848-r25346","title":"Core i7-6500U — ChipsWiki, revision 25346","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6500u&oldid=25346","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6500u"],"contentSha256":"e78450d3bdcf2a1944deb87d63d47001147d7b0fdd0cca67432a7fc0dd870bf2"},{"id":"chipswiki-7849-r25348","title":"Core i7-640UM — ChipsWiki, revision 25348","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640um&oldid=25348","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-640um"],"contentSha256":"23a3d5e5e66e5510b475a224c21c935eaf8d7fadd97f781a870f49cf7c58b37f"},{"id":"chipswiki-7853-r25352","title":"Core i7-620UE — ChipsWiki, revision 25352","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620ue&oldid=25352","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-620ue"],"contentSha256":"d615529b7e0e49362840f44462e249c9a75cb257b3d3f51048dbcc710b5d1146"},{"id":"chipswiki-7863-r25364","title":"Core i7-4980HQ — ChipsWiki, revision 25364","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4980hq&oldid=25364","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-4980hq"],"contentSha256":"49e83bd78f2d67b6977f093e763f0005fa2ca4941d9ba4b4d06edb66925e4d0f"},{"id":"chipswiki-7865-r25368","title":"Core i7-4860HQ — ChipsWiki, revision 25368","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860hq&oldid=25368","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-4860hq"],"contentSha256":"ad072723d6065dbd3a97f0db1260c99863d4d8f16c3ebad41abc2f08bea6c365"},{"id":"chipswiki-7868-r25371","title":"Core i7-4850EQ — ChipsWiki, revision 25371","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850eq&oldid=25371","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-4850eq"],"contentSha256":"bb3413ad790a7dbe39d307edfaeb090f4390af1c28f3f47a247e8390eed6783c"},{"id":"chipswiki-7872-r25375","title":"Core i7-4750HQ — ChipsWiki, revision 25375","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4750hq&oldid=25375","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-4750hq"],"contentSha256":"8c85d0c58aa94cb23605cec386eba02ee66ca2286386760b397332c7419fa331"},{"id":"chipswiki-7874-r25378","title":"Core i7-2820QM — ChipsWiki, revision 25378","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2820qm&oldid=25378","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2820qm"],"contentSha256":"0b095a0f6a7106591b57abfa36a30dc909f925769408e1bbc60ea8cc611404e1"},{"id":"chipswiki-7876-r25380","title":"Core i7-2740QM — ChipsWiki, revision 25380","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2740qm&oldid=25380","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2740qm"],"contentSha256":"f3999263f74d759168e1679c04af469b77fd62c33b49c0f7570ec6b844fea9ea"},{"id":"chipswiki-7878-r25382","title":"Core i7-2715QE — ChipsWiki, revision 25382","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2715qe&oldid=25382","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2715qe"],"contentSha256":"0c67a2a755e058a09b3d3de820a2f192edc591892390ed0ecd0dfa9c39b811be"},{"id":"chipswiki-7880-r25384","title":"Core i7-2689M — ChipsWiki, revision 25384","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2689m&oldid=25384","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2689m"],"contentSha256":"f3955c21eadfa9490103357ffe95dbe9ff8f8899b7a63a63f986cfd4cd2e9ee2"},{"id":"chipswiki-7881-r25385","title":"Core i7-2685QM — ChipsWiki, revision 25385","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2685qm&oldid=25385","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2685qm"],"contentSha256":"f0950112a4f79ae1d84175a9ea4d7b2c738ae8f127c4954e16ac2075fa6d012b"},{"id":"chipswiki-7882-r25386","title":"Core i7-2677M — ChipsWiki, revision 25386","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2677m&oldid=25386","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2677m"],"contentSha256":"ca5aeccf27a72f39f1715e2c17b3ca78ed577d1a3ae80a308e7448aa8a93d109"},{"id":"chipswiki-7883-r25387","title":"Core i7-2675QM — ChipsWiki, revision 25387","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2675qm&oldid=25387","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2675qm"],"contentSha256":"6d563f908ce848a66d8513d66f8e7afdd7b008d35322dee6b3bc5919e192a7fb"},{"id":"chipswiki-7885-r25389","title":"Core i7-2669M — ChipsWiki, revision 25389","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2669m&oldid=25389","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2669m"],"contentSha256":"be127d8514517bf9a8eab8a8d17553ea7425b29e749682aa0360679242a69690"},{"id":"chipswiki-7888-r25392","title":"Core i7-2657M — ChipsWiki, revision 25392","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2657m&oldid=25392","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2657m"],"contentSha256":"2006980efd8cfa25165e4fe9cfa49afe6ef26796a7233f96193b7fbe282233f3"},{"id":"chipswiki-841-r2211","title":"Core i7-7500U — ChipsWiki, revision 2211","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7500u&oldid=2211","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7500u"],"contentSha256":"ef073e993893ba5d319e204fb98ad7a42905f1dfb5ef26513b951fbb0d43112c"},{"id":"chipswiki-886-r2303","title":"Core i7-8565U — ChipsWiki, revision 2303","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8565u&oldid=2303","publisher":"ChipsWiki / WikiChip contributors","published":"2020-12-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8565u"],"contentSha256":"e93e9e7e9d7962bc59a90bcff099f610677930f830cfe574f3003745bca2fc6e"},{"id":"chipswiki-1579-r5228","title":"Core i7-740QM — ChipsWiki, revision 5228","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-740qm&oldid=5228","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-740qm"],"contentSha256":"60cdce6674266dfc0de73ed1fdfd48be1f2662cb2e63c4b615ff400f2ee1d5ed"},{"id":"chipswiki-2207-r7466","title":"Core i7-8550U — ChipsWiki, revision 7466","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8550u&oldid=7466","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8550u"],"contentSha256":"36400b3cde48c560362380be824d21528c4528701cd48a7b6197dac8a81043d3"},{"id":"chipswiki-3971-r12658","title":"Core i7-6920HQ — ChipsWiki, revision 12658","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6920hq&oldid=12658","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6920hq"],"contentSha256":"9f3639cd78ab08dfc335dc6a23abbb7d89d4b3ba19c6d205a653222085f4fbd8"},{"id":"chipswiki-3973-r12660","title":"Core i7-6820HK — ChipsWiki, revision 12660","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hk&oldid=12660","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6820hk"],"contentSha256":"c5964d7d80b791d283638478a123bb16dfa61b606fee408e53815297943f78a8"},{"id":"chipswiki-4978-r16100","title":"Core i7-7Y75 — ChipsWiki, revision 16100","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7y75&oldid=16100","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7y75"],"contentSha256":"82eb13e24dfed0debe356e27acfdbe2c2bbf16b35f1ecd0bfeb8f92892c975c6"},{"id":"chipswiki-7130-r22499","title":"Core i7-820QM — ChipsWiki, revision 22499","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-820qm&oldid=22499","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-820qm"],"contentSha256":"d6665e1d6c892b6604a04d55b98af05c3864e069098b7cc3063d8a40dcd69b26"},{"id":"chipswiki-7594-r24692","title":"Core i7-7600U — ChipsWiki, revision 24692","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7600u&oldid=24692","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7600u"],"contentSha256":"cbb36e1a4345602d14df67238d810338255b67017635f511c52451e43ddd3d2b"},{"id":"chipswiki-7829-r25317","title":"Core i7-7567U — ChipsWiki, revision 25317","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7567u&oldid=25317","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7567u"],"contentSha256":"e70618f7d28c03f7477909eeeb6add8615a02c0cd5eb682743518f435c8e0475"},{"id":"chipswiki-7831-r25319","title":"Core i7-7510U — ChipsWiki, revision 25319","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7510u&oldid=25319","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7510u"],"contentSha256":"2bdd470b88da32c566138c80874708f0a0b3e4c1fc1812678225b2e6a84fa70c"},{"id":"chipswiki-7832-r25322","title":"Core i7-720QM — ChipsWiki, revision 25322","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-720qm&oldid=25322","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-720qm"],"contentSha256":"7ec188b354fa5529ae15f467a274d85688a0341532d4a8cc1823e553cbeaffdf"},{"id":"chipswiki-7833-r25323","title":"Core i7-6970HQ — ChipsWiki, revision 25323","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6970hq&oldid=25323","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6970hq"],"contentSha256":"c5533ffab933eba524dc7474430d0cff37290fa515cb05e795fdad8a905bb679"},{"id":"chipswiki-7839-r25332","title":"Core i7-6770HQ — ChipsWiki, revision 25332","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6770hq&oldid=25332","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6770hq"],"contentSha256":"928742e467a30c9d91c9197c46ef22defb486f821aa4e1091f022fa22a8369ae"},{"id":"chipswiki-7841-r25338","title":"Core i7-6660U — ChipsWiki, revision 25338","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6660u&oldid=25338","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6660u"],"contentSha256":"bd1250ee73232563176238f8d1ab1fd0c30c4d3200b66f67ef9751b48f9edeca"},{"id":"chipswiki-7843-r25340","title":"Core i7-660UM — ChipsWiki, revision 25340","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660um&oldid=25340","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-660um"],"contentSha256":"9724e253d6c95f3168c9eba8cf5b6b3a003c84d44b662f1a31a22eb44f81e4b8"},{"id":"chipswiki-7846-r25344","title":"Core i7-6567U — ChipsWiki, revision 25344","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6567u&oldid=25344","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6567u"],"contentSha256":"c0a9ccc07f2fa9621972f7531e0c4a937739a85e58da2507a17acf2f7e98b71c"},{"id":"chipswiki-741-r1767","title":"Core i7-9700T — ChipsWiki, revision 1767","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9700t&oldid=1767","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-9700t"],"contentSha256":"0cb1ffa0b09185d48a24e48004e47ae9e623af301a5768155fd6171d08580adf"},{"id":"chipswiki-977-r2767","title":"Core i7-8700B — ChipsWiki, revision 2767","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8700b&oldid=2767","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8700b"],"contentSha256":"5333dbb5392c12bf09f9ffb99739d44f415959a9ec3741b049f5c0a7ed12c39d"},{"id":"chipswiki-1572-r5184","title":"Core i7-940XM Extreme Edition — ChipsWiki, revision 5184","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-940xm&oldid=5184","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7ee/i7-940xm"],"contentSha256":"15678d22acfd418ece4831cc58ef516f0a5f99c4ac6a8ddcfd03dea6faf551ac"},{"id":"chipswiki-3807-r11897","title":"Core i7-4960X Extreme Edition — ChipsWiki, revision 11897","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4960x&oldid=11897","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7ee/i7-4960x"],"contentSha256":"2d066b28d05f4c21939f3eeed4ae4f2bceb76f1861c5c3b22049a4f169756838"},{"id":"chipswiki-4367-r14119","title":"Core i7-8650U — ChipsWiki, revision 14119","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8650u&oldid=14119","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8650u"],"contentSha256":"c13a1364b1d4a216af3695faafecd1dd93b01a35cdd91c85114271ab8e639463"},{"id":"chipswiki-4726-r15149","title":"Core i7-920XM Extreme Edition — ChipsWiki, revision 15149","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-920xm&oldid=15149","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7ee/i7-920xm"],"contentSha256":"4cf04696c0e1ec98e9774930aa12bb200ff8d26048a4bc89a6960c207b3b2350"},{"id":"chipswiki-4961-r16054","title":"Core i7-8670 — ChipsWiki, revision 16054","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670&oldid=16054","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8670"],"contentSha256":"37188235e0fba9df410a4119ba46c52d9f0b4fa4042fe9edc8d1a1bacd9df6b2"},{"id":"chipswiki-5287-r17293","title":"Core i7-8709G — ChipsWiki, revision 17293","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8709g&oldid=17293","publisher":"ChipsWiki / WikiChip contributors","published":"2018-07-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8709g"],"contentSha256":"25f122d755189175015e83c34b756687ee912bd1b9730c53416c62d7708aa2d6"},{"id":"chipswiki-5570-r18114","title":"Core i7-8809G — ChipsWiki, revision 18114","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8809g&oldid=18114","publisher":"ChipsWiki / WikiChip contributors","published":"2018-06-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8809g"],"contentSha256":"fb1baab243a47919433a2514ae90fa6b75898b7274701d8f64456c59a174021b"},{"id":"chipswiki-7818-r25273","title":"Core i7-990X Extreme Edition — ChipsWiki, revision 25273","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-990x&oldid=25273","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7ee/i7-990x"],"contentSha256":"943fb5441681e73e4404efcc33595e59aa4798c32fbbb51cf8abce9ba363953b"},{"id":"chipswiki-7820-r25275","title":"Core i7-975 Extreme Edition — ChipsWiki, revision 25275","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-975&oldid=25275","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7ee/i7-975"],"contentSha256":"0fa81fa7815a4ae0269ab31ff482646b9a17db4ee4527fa032f7616bc3bebed7"},{"id":"chipswiki-7825-r25284","title":"Core i7-3970X Extreme Edition — ChipsWiki, revision 25284","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3970x&oldid=25284","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7ee/i7-3970x"],"contentSha256":"f5e1e4bd3c5ecfa0df43d864e327120f08f0d64b15ec1308e9c316fce56d30ca"},{"id":"chipswiki-1191-r3729","title":"Core M3-8114Y — ChipsWiki, revision 3729","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8114y&oldid=3729","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/m3-8114y"],"contentSha256":"eee5588d9d7d8f0e823ef046ae33d550729a3a563d3ae06fbefd75bf65c94415"},{"id":"chipswiki-1373-r4595","title":"Core i9-9900T — ChipsWiki, revision 4595","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9900t&oldid=4595","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i9/i9-9900t"],"contentSha256":"845754dafde3c0f505f53a2a2335048068924ecb91c6cf25a73a102bb2dc2bfd"},{"id":"chipswiki-4980-r16102","title":"Core m3-6Y30 — ChipsWiki, revision 16102","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-6y30&oldid=16102","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/m3-6y30"],"contentSha256":"5cefb7bb7b0a9fe8c0555b685eb5a004a5c5a8c57e5b66b228401aea449d050c"},{"id":"chipswiki-4982-r16104","title":"Core m5-6Y54 — ChipsWiki, revision 16104","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y54&oldid=16104","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/m5-6y54"],"contentSha256":"6be8d0464817cbe61db3fa8e098cf7c72b82636aa7ff57a65522df73c0d28558"},{"id":"chipswiki-4983-r16105","title":"Core m7-6Y75 — ChipsWiki, revision 16105","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm7-6y75&oldid=16105","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/m7-6y75"],"contentSha256":"e5cf6e11e01d170574052a1d30045daee5967c995b3bcd45836f47ca221ab096"},{"id":"chipswiki-7812-r25261","title":"Core M 5Y70 — ChipsWiki, revision 25261","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y70&oldid=25261","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/5y70"],"contentSha256":"4cfda3d863adfbb25a47709ac4dce46742055b1fb7e808f3f681175b182791a7"},{"id":"chipswiki-7813-r25262","title":"Core M 5Y51 — ChipsWiki, revision 25262","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y51&oldid=25262","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/5y51"],"contentSha256":"51d6c8056b19a4532b4ebe32dd94729d991c96e9ac3baa6a65786785233e3387"},{"id":"chipswiki-7816-r25265","title":"Core M 5Y10a — ChipsWiki, revision 25265","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10a&oldid=25265","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_m/5y10a"],"contentSha256":"bf3dcc2260dc63079faf845a5aa5556c2d11c874a72771f4d828953ba6ae4f2f"},{"id":"chipswiki-202-r414","title":"Comet Lake — ChipsWiki, revision 414","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcomet%20lake&oldid=414","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/comet_lake"],"contentSha256":"25f9949468589d07ccf87016cfe4ce90df9cdf962d9937529fab6fa826836386"},{"id":"chipswiki-294-r591","title":"Cooper Lake — ChipsWiki, revision 591","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcooper%20lake&oldid=591","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/cooper_lake"],"contentSha256":"8a3c91c541a5c8f0deaf520d9190bc57688e2d548ac7b22254fed4f9d1d75946"},{"id":"chipswiki-544-r1122","title":"Broadwell — ChipsWiki, revision 1122","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbroadwell%20(client)&oldid=1122","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/broadwell_(client)"],"contentSha256":"fec0d23ee8a3130dd3d04208815678a6dd6f9bb31628b748ac5ecb4c0db40be3"},{"id":"chipswiki-563-r1193","title":"4004 — ChipsWiki, revision 1193","url":"https://chipswiki.org/index.php?title=Intel%2Fmcs-4%2F4004&oldid=1193","publisher":"ChipsWiki / WikiChip contributors","published":"2021-11-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mcs-4/4004"],"contentSha256":"915901d1ce1dd2c57d8d64c650db93d326fe1ef9e1242db81f179ea616c98f8d"},{"id":"chipswiki-895-r2347","title":"Coffee Lake — ChipsWiki, revision 2347","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcoffee%20lake&oldid=2347","publisher":"ChipsWiki / WikiChip contributors","published":"2020-12-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/coffee_lake"],"contentSha256":"17da5d44712c3fab2610ed7c2f5a711eca51c057ed74282bfd457501bf74d87d"},{"id":"chipswiki-1157-r3620","title":"Gen9.5 — ChipsWiki, revision 3620","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9.5&oldid=3620","publisher":"ChipsWiki / WikiChip contributors","published":"2020-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen9.5"],"contentSha256":"72cb070cda4355f856ec67bf0cfd206098fbd3d80e019f089015c30681b5dda4"},{"id":"chipswiki-2036-r6890","title":"Cannon Lake — ChipsWiki, revision 6890","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcannon%20lake&oldid=6890","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/cannon_lake"],"contentSha256":"324a8e1162ef326b44521f9f28f1faf8d9d028965b5adbad76e4c540bb824b1e"},{"id":"chipswiki-2471-r8392","title":"Amber Lake — ChipsWiki, revision 8392","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Famber%20lake&oldid=8392","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/amber_lake"],"contentSha256":"3e3b415bf6d88f6e9770d9a50bb3dfd9bf28512a19f55d9e41c47064f950c1a5"},{"id":"chipswiki-4490-r14591","title":"Gen9 — ChipsWiki, revision 14591","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen9&oldid=14591","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen9"],"contentSha256":"883bf818748e9697c5be5d7c1b2ac319c1aac9666f55978a9f9d928a0f249d00"},{"id":"chipswiki-5102-r16631","title":"Gen11 — ChipsWiki, revision 16631","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen11&oldid=16631","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen11"],"contentSha256":"f0a8b7e1fcbe81f605aaff997e560b6e51a4e74a12cd82de50b61bfddd2a5eda"},{"id":"chipswiki-7809-r25248","title":"8080 — ChipsWiki, revision 25248","url":"https://chipswiki.org/index.php?title=Intel%2Fmcs-80%2F8080&oldid=25248","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mcs-80/8080"],"contentSha256":"fef5801ef1ee196099d179ecce14e498d747324b4f44305d4483cd2355f60146"},{"id":"chipswiki-7810-r25249","title":"8008-1 — ChipsWiki, revision 25249","url":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008-1&oldid=25249","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mcs-8/8008-1"],"contentSha256":"ee3f9161baa86ff39b0ed0f5450fefc068650b3ebfb720ce248ebe8b3f7325f9"},{"id":"chipswiki-8761-r27223","title":"Chivano — ChipsWiki, revision 27223","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fchivano&oldid=27223","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/chivano"],"contentSha256":"47e8b891a9fa05d79bc69cc016c247af6051261f8e175a38db0eb6c827529918"},{"id":"chipswiki-8768-r27240","title":"Airmont — ChipsWiki, revision 27240","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fairmont&oldid=27240","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/airmont"],"contentSha256":"ee5bd38003f59e6636551dbb6072569214a142a7e6900c3c7f4537ef2790528c"},{"id":"chipswiki-15958-r52681","title":"Gen3.5 — ChipsWiki, revision 52681","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3.5&oldid=52681","publisher":"ChipsWiki / WikiChip contributors","published":"2017-01-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen3.5"],"contentSha256":"b4ad0faeb9a17e6d1ee8b447b801e80a2dab6b83697c2d6aa16e9f1668f40d7a"},{"id":"chipswiki-15960-r52687","title":"Gen2 — ChipsWiki, revision 52687","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen2&oldid=52687","publisher":"ChipsWiki / WikiChip contributors","published":"2017-01-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen2"],"contentSha256":"404336e105f4c5e75b51db729378a0b49ab721005454d65c6515036c36ab23e3"},{"id":"chipswiki-15962-r52691","title":"Gen5.75 (Ironlake) — ChipsWiki, revision 52691","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5.75&oldid=52691","publisher":"ChipsWiki / WikiChip contributors","published":"2017-01-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen5.75"],"contentSha256":"41fbd0ae04438c4d272ce89b69fdc49ec44679a8d9baaa7d6e70ec52e3e54d65"},{"id":"chipswiki-15963-r52697","title":"Gen6 — ChipsWiki, revision 52697","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen6&oldid=52697","publisher":"ChipsWiki / WikiChip contributors","published":"2017-01-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen6"],"contentSha256":"92236c050287dde3cd138205f5d2ad327d0719a93033ccb5504be548fec36bb2"},{"id":"chipswiki-15964-r52699","title":"Gen7 — ChipsWiki, revision 52699","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7&oldid=52699","publisher":"ChipsWiki / WikiChip contributors","published":"2017-01-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen7"],"contentSha256":"d4fef92876ce8ca6f123b5a7f6150f1ae0b68bb76b756bc6e34da97a972adc4b"},{"id":"chipswiki-15965-r52700","title":"Gen7.5 — ChipsWiki, revision 52700","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen7.5&oldid=52700","publisher":"ChipsWiki / WikiChip contributors","published":"2017-01-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen7.5"],"contentSha256":"5cdb0913c5bc0ad24dc7c4f9df893cf09d39451b18548c41bdefa925437afc07"},{"id":"chipswiki-30-r96959","title":"Skylake (client) — ChipsWiki, revision 96959","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(client)&oldid=96959","publisher":"ChipsWiki / WikiChip contributors","published":"2022-11-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/skylake_(client)"],"contentSha256":"4e58c985a83de41837556f2cd8e8f9317e80565321232d3bfa1d7f3b8cb14983"},{"id":"chipswiki-297-r598","title":"Kaby Lake — ChipsWiki, revision 598","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkaby%20lake&oldid=598","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/kaby_lake"],"contentSha256":"8e836a9c7cfac9801cfb5ac46d1053f1715bf80b19b373cc60c221cecd8eea81"},{"id":"chipswiki-495-r989","title":"Meteor Lake — ChipsWiki, revision 989","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmeteor%20lake&oldid=989","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/meteor_lake"],"contentSha256":"7ab813d348940f62e6b6aeed402cdf80e906003c94040d4c5bb2e67a4880b6d2"},{"id":"chipswiki-567-r1198","title":"Rocket Lake — ChipsWiki, revision 1198","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frocket%20lake&oldid=1198","publisher":"ChipsWiki / WikiChip contributors","published":"2021-11-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/rocket_lake"],"contentSha256":"f80100d97cbef02e18f50542f7147f9b5d12b26a0cccbbf8b801fe5a309648bf"},{"id":"chipswiki-633-r1521","title":"Gracemont — ChipsWiki, revision 1521","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgracemont&oldid=1521","publisher":"ChipsWiki / WikiChip contributors","published":"2021-08-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gracemont"],"contentSha256":"f2a23f826d900f37dd45798094f8c1af1189f9089c1c9ab54447ac7b5d3bf69c"},{"id":"chipswiki-640-r1543","title":"Lakefield — ChipsWiki, revision 1543","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flakefield&oldid=1543","publisher":"ChipsWiki / WikiChip contributors","published":"2021-08-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/lakefield"],"contentSha256":"dc51f84678a61e824bd91a1b0efeef907fc9f0e353d47fd5702d118160b74353"},{"id":"chipswiki-674-r1643","title":"Tiger Lake — ChipsWiki, revision 1643","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftiger%20lake&oldid=1643","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/tiger_lake"],"contentSha256":"34be6e304121fb2abe9d5b17598e44ec7b165d774d26891f2faddd7b6b87f267"},{"id":"chipswiki-1229-r3858","title":"Spring Hill — ChipsWiki, revision 3858","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fspring%20hill&oldid=3858","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/spring_hill"],"contentSha256":"81ae7689c2b75270e62b6e603f76e618c2dd0b8f907c26d24efcb93995b69781"},{"id":"chipswiki-1233-r3879","title":"Goldmont Plus — ChipsWiki, revision 3879","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont%20plus&oldid=3879","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/goldmont_plus"],"contentSha256":"d0f090acc5350e9516bbb7aa9e7031c2e14395dba7c63e089f874499a96d287e"},{"id":"chipswiki-1234-r3880","title":"Goldmont — ChipsWiki, revision 3880","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgoldmont&oldid=3880","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/goldmont"],"contentSha256":"18273bb35bf5529a0561df76f620d8290c2830654eb16445cc429a20c4608a92"},{"id":"chipswiki-2166-r7247","title":"Snow Ridge — ChipsWiki, revision 7247","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsnow%20ridge&oldid=7247","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/snow_ridge"],"contentSha256":"b105a753e4ad77b5ab56be1565129a0bc44aa702d76f97224387ab2fd13a413d"},{"id":"chipswiki-2490-r8521","title":"Knights Mill — ChipsWiki, revision 8521","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20mill&oldid=8521","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/knights_mill"],"contentSha256":"472e08cf5ebeaa0dde073a1c9164d53e7a326a55c4358623f12f081e460e9521"},{"id":"chipswiki-2502-r8585","title":"Knights Ferry — ChipsWiki, revision 8585","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20ferry&oldid=8585","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/knights_ferry"],"contentSha256":"f23a27c86509e20017ffcddabe6bc6e0436c3d97c004c2cab3d08ba6f6e3e6b0"},{"id":"chipswiki-3750-r11649","title":"Rock Creek — ChipsWiki, revision 11649","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Frock%20creek&oldid=11649","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/rock_creek"],"contentSha256":"8722191f908149932f0465c00d36238ab3cde3dfde920273e76d0cdd05540f8d"},{"id":"chipswiki-3754-r11663","title":"Larrabee — ChipsWiki, revision 11663","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Flarrabee&oldid=11663","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/larrabee"],"contentSha256":"1fb6df55414ec3271022fdd9b4ce4805fbe6d545d187aa51f88c0f6d55db113a"},{"id":"chipswiki-3898-r12328","title":"Nehalem — ChipsWiki, revision 12328","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnehalem%20(client)&oldid=12328","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/nehalem_(client)"],"contentSha256":"67021f3efd65c3afd4729fcb7d58b247a01743e08152494af7c35cdcf8d7d649"},{"id":"chipswiki-6983-r21823","title":"Penryn — ChipsWiki, revision 21823","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpenryn%20(client)&oldid=21823","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/penryn_(client)"],"contentSha256":"d50ba0648901bf0649bb7ae0a71cc44ea2c44bc1838f7a628e676fe524eb0dbe"},{"id":"chipswiki-8758-r27220","title":"McKinley — ChipsWiki, revision 27220","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmckinley&oldid=27220","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/mckinley"],"contentSha256":"1f47a7f5de440d0138fcfc7269b3001b379ca368af3947ada41d2ee4942cad35"},{"id":"chipswiki-8766-r27228","title":"Kittson — ChipsWiki, revision 27228","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fkittson&oldid=27228","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/kittson"],"contentSha256":"53d96485b9952cb571794adfa4e17e090a1acadcf7a49df3d2d742370287f143"},{"id":"chipswiki-8774-r27271","title":"Modified Pentium M — ChipsWiki, revision 27271","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmodified%20pentium%20m&oldid=27271","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/modified_pentium_m"],"contentSha256":"6d14c96fafa00b08e1b1efd9da2ccaef94365755f71d914d2f6f25a98acf16a5"},{"id":"chipswiki-909-r2446","title":"Pentium P6100 — ChipsWiki, revision 2446","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6100&oldid=2446","publisher":"ChipsWiki / WikiChip contributors","published":"2020-11-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/p6100"],"contentSha256":"2d91d0b94d3bd75287839463df9e8f4e3735e68d122bfb2578c4b391a46ea25b"},{"id":"chipswiki-913-r2499","title":"Pentium G4400 — ChipsWiki, revision 2499","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400&oldid=2499","publisher":"ChipsWiki / WikiChip contributors","published":"2020-11-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/g4400"],"contentSha256":"f821bc1e14526d9b46e704b2a5d4928edb851f4b12bbd0bf031197ae497545e3"},{"id":"chipswiki-1393-r4690","title":"Whiskey Lake — ChipsWiki, revision 4690","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwhiskey%20lake&oldid=4690","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/whiskey_lake"],"contentSha256":"acd1fb968efd72964ddff12dd5fe1e76a13eb9a45566c0c0916e2a6c32b77bd5"},{"id":"chipswiki-3814-r11982","title":"Pentium B960 — ChipsWiki, revision 11982","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb960&oldid=11982","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/b960"],"contentSha256":"ebbea65164998b7d09a3606d3dcdaff841d9da13f8869e60891a3f9c2f7f4e2e"},{"id":"chipswiki-6860-r21413","title":"Pentium J3710 — ChipsWiki, revision 21413","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj3710&oldid=21413","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/j3710"],"contentSha256":"6e9baa79503cb54c519a1afda3ff344612746c8e33e5308028656543773c1b54"},{"id":"chipswiki-7779-r25211","title":"Pentium P6000 — ChipsWiki, revision 25211","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6000&oldid=25211","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/p6000"],"contentSha256":"3b3402af1dc93a1debc06738c382fc12ce956561ebc8daeeefa611f62a4858d6"},{"id":"chipswiki-7781-r25215","title":"Pentium J4205 — ChipsWiki, revision 25215","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fj4205&oldid=25215","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/j4205"],"contentSha256":"2cea2d352b56e7aead222c1eec181e6b6d0eb6a90546039b96b7df005e2214a2"},{"id":"chipswiki-7784-r25219","title":"Pentium G4520 — ChipsWiki, revision 25219","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4520&oldid=25219","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/g4520"],"contentSha256":"53b0cc2fb34c3bce66282e27aaee2228a8598368b8ddbbea481a408d522c88f4"},{"id":"chipswiki-7789-r25225","title":"Pentium B980 — ChipsWiki, revision 25225","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb980&oldid=25225","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/b980"],"contentSha256":"6875384e3bfba8d3ad4d94bdcb323329a45ccea94d82594d8919ec9780c3e321"},{"id":"chipswiki-7791-r25229","title":"Pentium B940 — ChipsWiki, revision 25229","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb940&oldid=25229","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/b940"],"contentSha256":"41e98ba3b4d9d2bfedd9137ac0aca59f4ac9efa577bed1b6a7f3ff755f1c8df5"},{"id":"chipswiki-7797-r25235","title":"Pentium 927 — ChipsWiki, revision 25235","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F927&oldid=25235","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/927"],"contentSha256":"b58252a794b76820a252fdca6ccda7ac9b30f0ae3e4104d609dda450b9d6907e"},{"id":"chipswiki-7799-r25237","title":"Pentium 907 — ChipsWiki, revision 25237","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F907&oldid=25237","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/907"],"contentSha256":"2023ffc7eb6ab1a2a5f68f50bf7503e6f8ea5d589423b88731e71912c4ec3546"},{"id":"chipswiki-7800-r25239","title":"Pentium 4405U — ChipsWiki, revision 25239","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405u&oldid=25239","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/4405u"],"contentSha256":"dd263a5059bb8381b29939ea08c50e9ab8ec58369f48725dde17217a21e485e6"},{"id":"chipswiki-7804-r25243","title":"Mobile Pentium II 300PE — ChipsWiki, revision 25243","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300pe&oldid=25243","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/300pe"],"contentSha256":"d51ae96ba84506083018cadd37a4cef07de71a35abe916670f67422fd64dece2"},{"id":"chipswiki-7805-r25244","title":"Mobile Pentium II 300 — ChipsWiki, revision 25244","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F300&oldid=25244","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/300"],"contentSha256":"43f2ca82ec97fd4b6a0eaf5b65fc51d2777bba8cebf86212cd4d5ac50a089e67"},{"id":"chipswiki-7806-r25245","title":"Mobile Pentium II 266PE — ChipsWiki, revision 25245","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266pe&oldid=25245","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/266pe"],"contentSha256":"84e09db8a179f66dac955bf83c82b783b4471939d0316e4a909eb8228340cf00"},{"id":"chipswiki-1532-r4988","title":"Xeon Bronze 3106 — ChipsWiki, revision 4988","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3106&oldid=4988","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_bronze/3106"],"contentSha256":"e819dc68165417d9d8395ce877a1d1cda46ff66d6b4955e65b433885b569d885"},{"id":"chipswiki-1533-r4989","title":"Xeon Bronze 3104 — ChipsWiki, revision 4989","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3104&oldid=4989","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_bronze/3104"],"contentSha256":"7faa5fc0dae33d28c3a7d5c84070ac3e445087e5055af0d3ded9a13109911ca4"},{"id":"chipswiki-1821-r6113","title":"Pentium Gold 4415U — ChipsWiki, revision 6113","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415u&oldid=6113","publisher":"ChipsWiki / WikiChip contributors","published":"2019-09-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/4415u"],"contentSha256":"fc715acb5fc248569e1162404774c41fd8d6c6229bb684675976b0a3d68973ff"},{"id":"chipswiki-2565-r8962","title":"Xeon Bronze 3204 — ChipsWiki, revision 8962","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20bronze%2F3204&oldid=8962","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_bronze/3204"],"contentSha256":"8f37f4cdc54857431a2da7d5fdf625cc916bff223ea5a3043fd996ba4a1dd5ed"},{"id":"chipswiki-2848-r9553","title":"Pentium Gold G5620 — ChipsWiki, revision 9553","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5620&oldid=9553","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/g5620"],"contentSha256":"890568c1ec18aebeb7fa3f9b4ba2090299653cb8b54852cfaa2242d81d44176b"},{"id":"chipswiki-2849-r9558","title":"Pentium Gold G5600T — ChipsWiki, revision 9558","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5600t&oldid=9558","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/g5600t"],"contentSha256":"05dee24339f4e7bcdb675bc5c0771a3d767af89702130484d9055fe890798396"},{"id":"chipswiki-2850-r9563","title":"Pentium Gold G5420T — ChipsWiki, revision 9563","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420t&oldid=9563","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/g5420t"],"contentSha256":"26600a867d41fed562a14d08975ed3eaa60d2fb14bfe7fb41ddd88da8704206f"},{"id":"chipswiki-4976-r16098","title":"Pentium Gold 4410Y — ChipsWiki, revision 16098","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4410y&oldid=16098","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/4410y"],"contentSha256":"b0c4618be602da4061f1c38030200b1c6c2d67272ecc13f978398912cef98e09"},{"id":"chipswiki-7585-r24644","title":"Pentium Gold G4620 — ChipsWiki, revision 24644","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4620&oldid=24644","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/g4620"],"contentSha256":"f763a3cb16a5114931edd9d2de073c60acabeb4917f10db9cd90f3f15b0c6f87"},{"id":"chipswiki-7586-r24645","title":"Pentium Gold G4560 — ChipsWiki, revision 24645","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4560&oldid=24645","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_gold/g4560"],"contentSha256":"50861bde0a911b50f0e52e469625577672d23355f2fa7d7d30f61ddfe1a4c48c"},{"id":"chipswiki-7776-r25207","title":"Pentium U5400 — ChipsWiki, revision 25207","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5400&oldid=25207","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/u5400"],"contentSha256":"39c83fcb244333b8cbbf341e554ad29d6eb37bbb3bebd9214f2b4d9ca934dd37"},{"id":"chipswiki-2526-r8664","title":"Xeon E-2104G — ChipsWiki, revision 8664","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2104g&oldid=8664","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2104g"],"contentSha256":"a69ad23dc2385f0040ef07d8f2226d649a414d19d68347b7e297da951553c4a5"},{"id":"chipswiki-3667-r10992","title":"Xeon D-1581 — ChipsWiki, revision 10992","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1581&oldid=10992","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1581"],"contentSha256":"02ccb7fe1ae80065ac0809e77f5ebc2c38650c20934d4cce650f0540d404ef0c"},{"id":"chipswiki-3682-r11010","title":"Xeon D-1627 — ChipsWiki, revision 11010","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1627&oldid=11010","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1627"],"contentSha256":"8c57b996c8f2091fea7558b07f22fe1f1fa51e791d01c86f5c9b63782e8c116b"},{"id":"chipswiki-3683-r11011","title":"Xeon D-1633N — ChipsWiki, revision 11011","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1633n&oldid=11011","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1633n"],"contentSha256":"3374cedf2897ef1c42676baa9532a3f235076d85f73229b673cad58e5039cc16"},{"id":"chipswiki-3684-r11012","title":"Xeon D-1649N — ChipsWiki, revision 11012","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1649n&oldid=11012","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1649n"],"contentSha256":"c81006800d99e5964605a68a4a38afc74e239e05ab7edf466791838021478de2"},{"id":"chipswiki-3685-r11013","title":"Xeon D-1622 — ChipsWiki, revision 11013","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1622&oldid=11013","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1622"],"contentSha256":"016cba7e3a7b107bcbc473cad58068491aab613a7fde5e8ffbee68abef62c1bf"},{"id":"chipswiki-3687-r11016","title":"Xeon D-1632 — ChipsWiki, revision 11016","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1632&oldid=11016","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1632"],"contentSha256":"c8d001247a565a96ac3b91f21d75fa052b107e72cbdfcad52d972fa0b5d4f241"},{"id":"chipswiki-3722-r11412","title":"Xeon D-1513N — ChipsWiki, revision 11412","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1513n&oldid=11412","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1513n"],"contentSha256":"5dda9efeca642c1a015edddf0bf6a115f4b38052620b8081ad20779b9b715b8c"},{"id":"chipswiki-3724-r11417","title":"Xeon D-1533N — ChipsWiki, revision 11417","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1533n&oldid=11417","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1533n"],"contentSha256":"bdcdd7bf2782d06f92d12011976c602424e05897286a445685b309831b43c98e"},{"id":"chipswiki-3725-r11420","title":"Xeon D-1543N — ChipsWiki, revision 11420","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1543n&oldid=11420","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1543n"],"contentSha256":"69a2c764ac255edc05c369a96a2fa21cde8d99ed0d439f600215f298e908edb7"},{"id":"chipswiki-3726-r11423","title":"Xeon D-1553N — ChipsWiki, revision 11423","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1553n&oldid=11423","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1553n"],"contentSha256":"bff59f835154796ac211cf44e5a5c921affbea913e5ab62bd6488b0dde3f8997"},{"id":"chipswiki-3732-r11437","title":"Xeon D-1531 — ChipsWiki, revision 11437","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1531&oldid=11437","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1531"],"contentSha256":"7434f83a0a31ab8ec772fe56d83862c9a1ae3c1928351f44928a26be8628e944"},{"id":"chipswiki-3737-r11446","title":"Xeon D-1571 — ChipsWiki, revision 11446","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1571&oldid=11446","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1571"],"contentSha256":"767e0971f7d8e241e3ca1c9fae1d29ad61b0699daf9b012ae908f11377fa8fdf"},{"id":"chipswiki-7147-r22561","title":"Xeon D-2187NT — ChipsWiki, revision 22561","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2187nt&oldid=22561","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2187nt"],"contentSha256":"ea2c52cbf65a5a93622024a6e3fd2212e21153ddd77fb7a37b35bf11d36455df"},{"id":"chipswiki-31304-r92006","title":"Template:Packages/intel/fcbga-2518 — revision 92006","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-2518"],"contentSha256":"13ba5e401091e4c702e84b8273b4abd2daa8a9dc8d883bc0bb7d7b70727e6d2c"},{"id":"chipswiki-7155-r22586","title":"Xeon D-2143IT — ChipsWiki, revision 22586","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2143it&oldid=22586","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2143it"],"contentSha256":"d3d8e3e3d24943c3a3ef08a64548a7bdef48259f835a3e41998fa185532903f2"},{"id":"chipswiki-7156-r22589","title":"Xeon D-2142IT — ChipsWiki, revision 22589","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2142it&oldid=22589","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2142it"],"contentSha256":"23e27f8740aab2a192f4c8383623bb6d64df5bd7aea95f2009b5d3b69ebcaff6"},{"id":"chipswiki-7159-r22597","title":"Xeon D-2141I — ChipsWiki, revision 22597","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2141i&oldid=22597","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2141i"],"contentSha256":"c63aa362b583e7197b0e1017d388dc708e841cd4079ca7e8338789424860fe79"},{"id":"chipswiki-7160-r22599","title":"Xeon D-2191 — ChipsWiki, revision 22599","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2191&oldid=22599","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2191"],"contentSha256":"38000f4e0431031921b21b4137d1b8db7de9f3378a0a4d9d5fbb493138a4b054"},{"id":"chipswiki-1697-r5910","title":"Xeon E-2124 — ChipsWiki, revision 5910","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2124&oldid=5910","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2124"],"contentSha256":"30019ed54d38a7c78beadb3b7c9faf89b02db0558f1c7382812129bedc7004ba"},{"id":"chipswiki-2402-r8025","title":"Xeon E-2286M — ChipsWiki, revision 8025","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286m&oldid=8025","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2286m"],"contentSha256":"b9cdaa0ee348a913aa28210ccb6bf0c8116bbff2bd0ab0c7b8217077bc2afb0b"},{"id":"chipswiki-2404-r8034","title":"Xeon E-2288G — ChipsWiki, revision 8034","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2288g&oldid=8034","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2288g"],"contentSha256":"f4365edf40ab58ebc0f3dd4c9e7fa95499935ba9a37bf20055368fa3c68bbb1e"},{"id":"chipswiki-2405-r8036","title":"Xeon E-2286G — ChipsWiki, revision 8036","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2286g&oldid=8036","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2286g"],"contentSha256":"ebf24c01640d04ecbdc0335d7253bd6dd7e5717cc8da93c4cdb471efbfd1875c"},{"id":"chipswiki-2407-r8040","title":"Xeon E-2276G — ChipsWiki, revision 8040","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276g&oldid=8040","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2276g"],"contentSha256":"3065cf120ea0e4fb4618e8aa46a3b59427300b080fb88d57366b866a781fce0d"},{"id":"chipswiki-2409-r8044","title":"Xeon E-2246G — ChipsWiki, revision 8044","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2246g&oldid=8044","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2246g"],"contentSha256":"aadbbd557bb8a81b8817b5be692a6c8d7b81ffef3091b5a5e246da923ab4f9f8"},{"id":"chipswiki-2410-r8046","title":"Xeon E-2244G — ChipsWiki, revision 8046","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2244g&oldid=8046","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2244g"],"contentSha256":"b22457c58f076e75656bf0e43bdef01cc2199c68e27e9c3111c4a76ef6c71de7"},{"id":"chipswiki-2412-r8056","title":"Xeon E-2224 — ChipsWiki, revision 8056","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224&oldid=8056","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2224"],"contentSha256":"19e34847a8e46a21f0a47f255c671126116b5aae294ff31f5bd932dac20cfe48"},{"id":"chipswiki-2413-r8072","title":"Xeon E-2224G — ChipsWiki, revision 8072","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2224g&oldid=8072","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2224g"],"contentSha256":"88b5289de3535c6cb7d51b7cfae8dd267306e350ed6bd11067da90b2dd1241b0"},{"id":"chipswiki-3033-r10101","title":"Xeon E-2126G — ChipsWiki, revision 10101","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2126g&oldid=10101","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2126g"],"contentSha256":"6aa9851337a962f1eff8be03a26f2cb5ef3d4272491f2ecac7dbc26dfef888aa"},{"id":"chipswiki-4958-r16042","title":"Xeon E-2176M — ChipsWiki, revision 16042","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2176m&oldid=16042","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2176m"],"contentSha256":"c8f1cd1c931c6fd42e39904150485c71fa59158e535febfa7fe043d231d501b5"},{"id":"chipswiki-6412-r20011","title":"Xeon E3-1501L v6 — ChipsWiki, revision 20011","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501l%20v6&oldid=20011","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1501l_v6"],"contentSha256":"2987fdaa7832e55e85bdbbabc69ac160d0093a7d3c2886da97ab54fc2bc38c65"},{"id":"chipswiki-6442-r20140","title":"Xeon E3-1268L v5 — ChipsWiki, revision 20140","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1268l%20v5&oldid=20140","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1268l_v5"],"contentSha256":"0ff6a5be541ba52380dfe7cbe5e1e613f3b17516ae7256dfa1cdb01366587fc2"},{"id":"chipswiki-6443-r20141","title":"Xeon E3-1275 v5 — ChipsWiki, revision 20141","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1275%20v5&oldid=20141","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1275_v5"],"contentSha256":"900468b887c0f50ef820fa5f114ed55a110582636ddf75a60cc1f41410933bb5"},{"id":"chipswiki-7763-r25151","title":"Xeon E3-1280 v6 — ChipsWiki, revision 25151","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v6&oldid=25151","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1280_v6"],"contentSha256":"e7cd333a6bdc58c6d78bc66ae4a2d5a922ba1cf07fc7e344f0bc34b203dbbd89"},{"id":"chipswiki-7766-r25158","title":"Xeon E3-1260L v5 — ChipsWiki, revision 25158","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1260l%20v5&oldid=25158","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1260l_v5"],"contentSha256":"4549cfed3aa2bfb0c553432842cb473198a78271a0d240ee4bc9c7a46e7a4053"},{"id":"chipswiki-7768-r25161","title":"Xeon E3-1240L v5 — ChipsWiki, revision 25161","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240l%20v5&oldid=25161","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1240l_v5"],"contentSha256":"7db51a37c853d2087ee5678dd6242fa821d36a6156d56b9b11c1cfbdb6a3c8d6"},{"id":"chipswiki-6411-r20010","title":"Xeon E3-1501M v6 — ChipsWiki, revision 20010","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1501m%20v6&oldid=20010","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1501m_v6"],"contentSha256":"4fd94b42a31ace0647a2540fba78cea6858f2015f3bab0b9c3ca12bc7711495d"},{"id":"chipswiki-7589-r24673","title":"Xeon E5-1660 v4 — ChipsWiki, revision 24673","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1660%20v4&oldid=24673","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-1660_v4"],"contentSha256":"df472e946d3c8ab4d759c0128f9a5923dbcce58e0c615839183bff53abad0df6"},{"id":"chipswiki-7592-r24676","title":"Xeon E5-1620 v4 — ChipsWiki, revision 24676","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1620%20v4&oldid=24676","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-1620_v4"],"contentSha256":"0f5672b0d3e28d92e5aa3a5d47fae152319907c348ee9e4ee38ed6d0fa6a0d1b"},{"id":"chipswiki-7730-r25105","title":"Xeon E5-2679 v4 — ChipsWiki, revision 25105","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2679%20v4&oldid=25105","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-2679_v4"],"contentSha256":"75f0f98c4d5eacfe528fd831672ed7782d63778fd8952ec1d80bab1974860bd5"},{"id":"chipswiki-7743-r25120","title":"Xeon E5-2623 v4 — ChipsWiki, revision 25120","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2623%20v4&oldid=25120","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-2623_v4"],"contentSha256":"3e4d80917d0a9a4f2b9a6ea82ca76d8d6308f6b58bf0769f9205aa8435d6fd40"},{"id":"chipswiki-7747-r25124","title":"Xeon E5-2608L v4 — ChipsWiki, revision 25124","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2608l%20v4&oldid=25124","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-2608l_v4"],"contentSha256":"14abfe2bd82343405b00323d73d83c70443aef4d83c48469e803935fe29eea4f"},{"id":"chipswiki-7749-r25131","title":"Xeon E5-1607 v4 — ChipsWiki, revision 25131","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1607%20v4&oldid=25131","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-1607_v4"],"contentSha256":"0edbb49f1c349090ef2fb1471d7c47556db1d0f81909428be6d7e6a316bba663"},{"id":"chipswiki-7750-r25132","title":"Xeon E5-1603 v4 — ChipsWiki, revision 25132","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1603%20v4&oldid=25132","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-1603_v4"],"contentSha256":"97c99f76598e0a9d77e1e4d40961d98cd0488eb6bb6f0aeaa78c8103551797aa"},{"id":"chipswiki-7757-r25139","title":"Xeon E3-1545M v5 — ChipsWiki, revision 25139","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1545m%20v5&oldid=25139","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1545m_v5"],"contentSha256":"665736f660e64c674c716b277007254d3209fb0b15dedefa2d12e9e52ad4f339"},{"id":"chipswiki-7758-r25141","title":"Xeon E3-1535M V5 — ChipsWiki, revision 25141","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v5&oldid=25141","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1535m_v5"],"contentSha256":"7d755e735a0657fe791a4edf4ef1cbbbbce7300bab1ece2f40b11b2f6cf9a778"},{"id":"chipswiki-7760-r25146","title":"Xeon E3-1505L v5 — ChipsWiki, revision 25146","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v5&oldid=25146","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1505l_v5"],"contentSha256":"9e86fc167262056991ab9237d846ad91c71f6be9b9d8e9fee9dd768b6842d966"},{"id":"chipswiki-268-r543","title":"Xeon Gold 5119T — ChipsWiki, revision 543","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5119t&oldid=543","publisher":"ChipsWiki / WikiChip contributors","published":"2022-08-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5119t"],"contentSha256":"c0fb23da2446d229bbc6fd4d7600e9003610745289a8bf4c788dbbeaf5274173"},{"id":"chipswiki-269-r544","title":"Xeon Gold 5117F — ChipsWiki, revision 544","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117f&oldid=544","publisher":"ChipsWiki / WikiChip contributors","published":"2022-08-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5117f"],"contentSha256":"3ab0da25725bc692fd328eb53e8ae302ceb185622868cef7b839b39e4e10d1b5"},{"id":"chipswiki-270-r545","title":"Xeon Gold 5117 — ChipsWiki, revision 545","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5117&oldid=545","publisher":"ChipsWiki / WikiChip contributors","published":"2022-08-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5117"],"contentSha256":"7c1da07ddc7fe9155217b181c9d8b0c1fb83576d12b93d12a9fb8c69db7554dc"},{"id":"chipswiki-1280-r4246","title":"Xeon E7-2820 — ChipsWiki, revision 4246","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2820&oldid=4246","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-2820"],"contentSha256":"38f95ccd2bf23640ecb2950ce729cc4d98da8ba0958229d4634e52559f5aadb4"},{"id":"chipswiki-31576-r92962","title":"Template:Packages/intel/lga-1567 — revision 92962","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","publisher":"ChipsWiki / WikiChip contributors","published":"2016-12-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Flga-1567"],"contentSha256":"37847471df9828d9a9acc3da7829780dab24bfb649f43ef7908dc9ff0bcc9e94"},{"id":"chipswiki-1525-r4977","title":"Xeon Gold 5120 — ChipsWiki, revision 4977","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120&oldid=4977","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5120"],"contentSha256":"533271beea22fa8cfb425390fa58c511c3ec61022befdf6728017fbf1b53cab9"},{"id":"chipswiki-1530-r4985","title":"Xeon Gold 5118 — ChipsWiki, revision 4985","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5118&oldid=4985","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5118"],"contentSha256":"0717fc9c690744e3091151eeb0cb6179ee56ba6e01fd5c19e8439914c3e467f5"},{"id":"chipswiki-1531-r4987","title":"Xeon Gold 5115 — ChipsWiki, revision 4987","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5115&oldid=4987","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5115"],"contentSha256":"0d55ea0b2682a22c583e35afbc225c5f5e64af9a5e38df5c1ea3e050aa6b2e5e"},{"id":"chipswiki-3955-r12634","title":"Xeon E7-8894 v4 — ChipsWiki, revision 12634","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8894%20v4&oldid=12634","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-8894_v4"],"contentSha256":"74350b5a58029b8656b92b431fe1e1d9902d59812d64f9753db5a15d50e4bab4"},{"id":"chipswiki-4468-r14395","title":"Xeon E5-4640 v4 — ChipsWiki, revision 14395","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4640%20v4&oldid=14395","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4640_v4"],"contentSha256":"24d8d9989a86d93f247d5a012c771f2bbc61c6d9970f3c7a1745416197873038"},{"id":"chipswiki-7691-r25061","title":"Xeon E7-8870 — ChipsWiki, revision 25061","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8870&oldid=25061","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-8870"],"contentSha256":"a1141731cfa66b731119710d270f8d01507f66538d349e961deb1e8f41c1d122"},{"id":"chipswiki-7694-r25064","title":"Xeon E7-8850 — ChipsWiki, revision 25064","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8850&oldid=25064","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-8850"],"contentSha256":"b7f080ce57d41b02caf547a034f3fe2dbc32a2a582f97160ab57baecd0ce1f2a"},{"id":"chipswiki-7695-r25065","title":"Xeon E7-8837 — ChipsWiki, revision 25065","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8837&oldid=25065","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-8837"],"contentSha256":"dec20e69e30677d1837bcbb6d5d034c538ab06fe5f1c8b7d02937fb092acf6b3"},{"id":"chipswiki-7701-r25071","title":"Xeon E7-4820 — ChipsWiki, revision 25071","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4820&oldid=25071","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-4820"],"contentSha256":"165d15d53946df9f56fc6efa0e95ac172703d4080ac11e111821b7bcd720d72e"},{"id":"chipswiki-7703-r25073","title":"Xeon E7-2870 — ChipsWiki, revision 25073","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2870&oldid=25073","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-2870"],"contentSha256":"4ac0c0e55ce62ad524f76a77fc0992151408655961b81334a6f652d828682618"},{"id":"chipswiki-7704-r25074","title":"Xeon E7-2860 — ChipsWiki, revision 25074","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2860&oldid=25074","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-2860"],"contentSha256":"23eac066a0f4d5bfffc9adcf37bb36d045583529403ece93bafb7f1a7f3d293a"},{"id":"chipswiki-7705-r25075","title":"Xeon E7-2850 — ChipsWiki, revision 25075","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2850&oldid=25075","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-2850"],"contentSha256":"371aaae109d9cc6329f7e1cf1c3543650194d7affc97204bcc9684e94caa7f24"},{"id":"chipswiki-7707-r25078","title":"Xeon E7-2803 — ChipsWiki, revision 25078","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2803&oldid=25078","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e7/e7-2803"],"contentSha256":"754c0fafdc10c6f31012aa8c7b1367db3ebee6f3956c0102584c05f74c33eac8"},{"id":"chipswiki-7708-r25079","title":"Xeon E5-4669 v4 — ChipsWiki, revision 25079","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4669%20v4&oldid=25079","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4669_v4"],"contentSha256":"5722d721acfd583771208e8fa7a10e08ab9291e0a2f5b0fd1a13a94e3a36fdb9"},{"id":"chipswiki-7709-r25080","title":"Xeon E5-4667 v4 — ChipsWiki, revision 25080","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4667%20v4&oldid=25080","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4667_v4"],"contentSha256":"f0c99955d763f222d4819445ab97bda55ce1d9ea15a5bce021ffd4cb8160367d"},{"id":"chipswiki-7710-r25081","title":"Xeon E5-4660 v4 — ChipsWiki, revision 25081","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4660%20v4&oldid=25081","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4660_v4"],"contentSha256":"22caf3119ad110e112e9b3d779ac1100a7e02571d97c65c7d8b04cb76530f1c3"},{"id":"chipswiki-7711-r25082","title":"Xeon E5-4655 v4 — ChipsWiki, revision 25082","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4655%20v4&oldid=25082","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4655_v4"],"contentSha256":"6f4bde55a14b3015ec5ad659d01a40acc07805ba28d3c2a775be691b18200225"},{"id":"chipswiki-7712-r25083","title":"Xeon E5-4650 v4 — ChipsWiki, revision 25083","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4650%20v4&oldid=25083","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4650_v4"],"contentSha256":"4a57a43ca13e3d775a577372eb65159890aed8612bc0b73c346a8d2635b7b71b"},{"id":"chipswiki-7714-r25086","title":"Xeon E5-4627 v4 — ChipsWiki, revision 25086","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4627%20v4&oldid=25086","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4627_v4"],"contentSha256":"f1fbdc3b6cd1818f6706c51ff5fa909ba7f8629b0951a31c2bcfd26691b912d6"},{"id":"chipswiki-7715-r25087","title":"Xeon E5-4620 v4 — ChipsWiki, revision 25087","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4620%20v4&oldid=25087","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-4620_v4"],"contentSha256":"250d4f1fd4cd3dde191a7270e2e194cd3fa60fa01d5ff522535a62351873064b"},{"id":"chipswiki-7717-r25089","title":"Xeon E5-2699R v4 — ChipsWiki, revision 25089","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699r%20v4&oldid=25089","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-2699r_v4"],"contentSha256":"54862da5f198723185dfd9f614957e9b7425e27410b8b4ce40e4c225a249cada"},{"id":"chipswiki-7718-r25092","title":"Xeon E5-2698 v4 — ChipsWiki, revision 25092","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2698%20v4&oldid=25092","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-2698_v4"],"contentSha256":"ff5c3f86a25095178e40ce996c3d5bedf4c1e15c0150f61c3f6457c2e686c5cf"},{"id":"chipswiki-7724-r25099","title":"Xeon E5-2689 v4 — ChipsWiki, revision 25099","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689%20v4&oldid=25099","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e5/e5-2689_v4"],"contentSha256":"2ab22897a3fab64010a1050ae03a56418f83f8a49e86f9f69e116d87802b9836"},{"id":"chipswiki-90-r97047","title":"Xeon Gold 5215 — ChipsWiki, revision 97047","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215&oldid=97047","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5215"],"contentSha256":"6e11abeeabde3fac01229f823c916e65d6701983b7dce2e5354261cfd19e98b1"},{"id":"chipswiki-594-r1388","title":"Xeon Gold 6212U — ChipsWiki, revision 1388","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6212u&oldid=1388","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6212u"],"contentSha256":"0f7b30a0cb4050df585734a855681a8cc6c19633bf5a0f9e7cd876d651628b67"},{"id":"chipswiki-1263-r4097","title":"Xeon Gold 6226R — ChipsWiki, revision 4097","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226r&oldid=4097","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6226r"],"contentSha256":"04902885c62f3f4320d83de74dad585582715061b23439e9131f01ea4396f668"},{"id":"chipswiki-1388-r4672","title":"Xeon Gold 5122 — ChipsWiki, revision 4672","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5122&oldid=4672","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5122"],"contentSha256":"89a3c234861dc91805a1b213bc1203db4b263b1d8f7ad10cff5b9e14fd472870"},{"id":"chipswiki-1491-r4943","title":"Xeon Gold 6226 — ChipsWiki, revision 4943","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6226&oldid=4943","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6226"],"contentSha256":"98269027581e7d86dc4114a3a8141b2ef4fca38f3a9ef431ad7fd30b8331d06d"},{"id":"chipswiki-1494-r4946","title":"Xeon Gold 6152 — ChipsWiki, revision 4946","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6152&oldid=4946","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6152"],"contentSha256":"14878a24d7daecdef532f5fddcc2f372264403922c1cf588cbf2d2892eb910b5"},{"id":"chipswiki-1504-r4956","title":"Xeon Gold 6140M — ChipsWiki, revision 4956","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140m&oldid=4956","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6140m"],"contentSha256":"7c4cc38059a0bd329a0531aa3689ec7c5738fd772bdc7eb5ef0fbfe0ee06cca1"},{"id":"chipswiki-1508-r4960","title":"Xeon Gold 6136 — ChipsWiki, revision 4960","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6136&oldid=4960","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6136"],"contentSha256":"fb075d8e0359dfa84805eeac8e78a2dfdbd89fc5e0ca5a24a06e2a3670e2ff05"},{"id":"chipswiki-1509-r4961","title":"Xeon Gold 6134 — ChipsWiki, revision 4961","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134&oldid=4961","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6134"],"contentSha256":"7c0f510a62c43e4220be5d40d98807a5d6eb606c046d9bc53aacdc041abed034"},{"id":"chipswiki-1510-r4962","title":"Xeon Gold 6132 — ChipsWiki, revision 4962","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6132&oldid=4962","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6132"],"contentSha256":"87320cf0a41b0aca4ca613bd106b37515a5f726ab0d2dc2dfa085ca22df7266d"},{"id":"chipswiki-1512-r4964","title":"Xeon Gold 6130F — ChipsWiki, revision 4964","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130f&oldid=4964","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6130f"],"contentSha256":"337f16b0bc16ac8c397208bd95c934117a9cadf489cd9af327670fa9a1a0d6ba"},{"id":"chipswiki-1513-r4965","title":"Xeon Gold 6130 — ChipsWiki, revision 4965","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130&oldid=4965","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6130"],"contentSha256":"6106661fa4e6e91de4e1805f9f8a6a820fb3855258c9808b18fc21e9ff97eb74"},{"id":"chipswiki-1514-r4966","title":"Xeon Gold 6128 — ChipsWiki, revision 4966","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6128&oldid=4966","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6128"],"contentSha256":"749e28a06184eab237ff9bd16a860e6fc86b358d92cd08d73e7c7c098d0a933e"},{"id":"chipswiki-1515-r4967","title":"Xeon Gold 6126T — ChipsWiki, revision 4967","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126t&oldid=4967","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6126t"],"contentSha256":"d088dba6c465c826cb4987c317c63a42ff5a90a0d84ed4dcb4a5e53a7ed81520"},{"id":"chipswiki-1517-r4969","title":"Xeon Gold 6126F — ChipsWiki, revision 4969","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126f&oldid=4969","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6126f"],"contentSha256":"a0a900a3ab2948a248de3eba49700dd8136693f4687e7949b16617fe7ca980c1"},{"id":"chipswiki-1521-r4973","title":"Xeon Gold 5218T — ChipsWiki, revision 4973","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218t&oldid=4973","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5218t"],"contentSha256":"76637d09643496e2f975141d64e21284ea1532f30ede15be97b2bbe2909e158b"},{"id":"chipswiki-1523-r4975","title":"Xeon Gold 5218 — ChipsWiki, revision 4975","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218&oldid=4975","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5218"],"contentSha256":"426cd7822cb54b06543e342f8bb5ea4822177070aa9c6413551dc05eccd4e1f0"},{"id":"chipswiki-1524-r4976","title":"Xeon Gold 5218B — ChipsWiki, revision 4976","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218b&oldid=4976","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5218b"],"contentSha256":"f63fd22a7d1e28a1825afeffee3cc3efcf8a150a08fa527fc0d920ed21668f5a"},{"id":"chipswiki-1527-r4981","title":"Xeon Gold 5217 — ChipsWiki, revision 4981","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5217&oldid=4981","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5217"],"contentSha256":"48994352498507fd276d328bdb21b0cc1a562c2ccd41b4a451986b525e635d70"},{"id":"chipswiki-189-r379","title":"Xeon Platinum 8175M — ChipsWiki, revision 379","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175m&oldid=379","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8175m"],"contentSha256":"8b488000fe58c691c8c807060ff2ed67cf6bbd993db740f9737873d2dff80338"},{"id":"chipswiki-218-r445","title":"Xeon Platinum 8160 — ChipsWiki, revision 445","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160&oldid=445","publisher":"ChipsWiki / WikiChip contributors","published":"2022-08-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8160"],"contentSha256":"a2ddab2ba7179de0c3709230425d46d2b9dd3a41381a0766a416a10101057be0"},{"id":"chipswiki-517-r1050","title":"Xeon Gold 6238 — ChipsWiki, revision 1050","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238&oldid=1050","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6238"],"contentSha256":"bb14f3ed6a6eedf7be392b5785a58adee501bcb1bd0b5bcf5d036a73cfdd7e47"},{"id":"chipswiki-972-r2740","title":"Xeon Gold 6248R — ChipsWiki, revision 2740","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248r&oldid=2740","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6248r"],"contentSha256":"9681bf4dadd4504ae5e8486cff545e9988edfcfaf64455de23b906895ddcd95e"},{"id":"chipswiki-1264-r4098","title":"Xeon Gold 6242R — ChipsWiki, revision 4098","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242r&oldid=4098","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6242r"],"contentSha256":"0347a29d56e8460ac719f2129d779a1382fe5d199a5b21c5d855b1b182e830d5"},{"id":"chipswiki-1266-r4101","title":"Xeon Gold 6230R — ChipsWiki, revision 4101","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230r&oldid=4101","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6230r"],"contentSha256":"09b3ed67559873186b0731a71a1c329930dd52717a4653477e14f33b5890af4c"},{"id":"chipswiki-1268-r4107","title":"Xeon Gold 6238R — ChipsWiki, revision 4107","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238r&oldid=4107","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6238r"],"contentSha256":"ad3a43002c2e3178c12e22637baccb4cf4aaac5fdbf55ccd2613d303669ea51c"},{"id":"chipswiki-1467-r4914","title":"Xeon Platinum 8176 — ChipsWiki, revision 4914","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176&oldid=4914","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8176"],"contentSha256":"55b89859f03acf604e6e16863f6173167d1da1b03bb944d7f38b2affa9ec4899"},{"id":"chipswiki-1473-r4920","title":"Xeon Platinum 8160T — ChipsWiki, revision 4920","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160t&oldid=4920","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8160t"],"contentSha256":"aecdc91ff907002cf5920ad93ce1f5ba3270b89e52028cb1b46766db8b7d8a53"},{"id":"chipswiki-1476-r4924","title":"Xeon Gold 6254 — ChipsWiki, revision 4924","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6254&oldid=4924","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6254"],"contentSha256":"ee8f3d0bdec39f4f617d38a92e0fee55f13d8924e93ef58a1396d8c35e850ed2"},{"id":"chipswiki-1478-r4926","title":"Xeon Gold 6252 — ChipsWiki, revision 4926","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252&oldid=4926","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6252"],"contentSha256":"f45814b901d20300105a448325da89ca0ae9e3b6dd5f2a5bdcd4b2b978d210ac"},{"id":"chipswiki-1481-r4929","title":"Xeon Gold 6244 — ChipsWiki, revision 4929","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6244&oldid=4929","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6244"],"contentSha256":"9ac9009d20a0e8e1d23b2048cd999af2179fd3afbc6841e67fa4fa433fc55603"},{"id":"chipswiki-2547-r8773","title":"Xeon Phi 7285 — ChipsWiki, revision 8773","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7285&oldid=8773","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_phi/7285"],"contentSha256":"d75227dcbc3f28e99e8417fa15c7486797ee3ad842ed1665bab681a2903f5936"},{"id":"chipswiki-2548-r8774","title":"Xeon Phi 7295 — ChipsWiki, revision 8774","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7295&oldid=8774","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_phi/7295"],"contentSha256":"90acfc07a319394361d9dbbecd0fca9da6d879ce9263a78f9e6d0fce0961ed1b"},{"id":"chipswiki-2558-r8824","title":"Xeon Platinum 8163 — ChipsWiki, revision 8824","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8163&oldid=8824","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8163"],"contentSha256":"1b2e124a8087c23ee0a4a5b529bbcc69a481b4d586331d4d2f8335233430c6cd"},{"id":"chipswiki-2559-r8826","title":"Xeon Platinum 8160M — ChipsWiki, revision 8826","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160m&oldid=8826","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8160m"],"contentSha256":"bfcec6a69cdf47bc163ccdc8e549f6551a376f76d51c37056b59cff835bb3152"},{"id":"chipswiki-2560-r8827","title":"Xeon Platinum 8160F — ChipsWiki, revision 8827","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8160f&oldid=8827","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8160f"],"contentSha256":"e47e8549639a19dcfb482c5c715b174b156a92ffb41d9e0c02bf4bc0b772de63"},{"id":"chipswiki-2562-r8830","title":"Xeon Platinum 8156 — ChipsWiki, revision 8830","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8156&oldid=8830","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8156"],"contentSha256":"916368ce4d68e6818a9831541175d2fb1e62052f56358c99c55429361de3cedb"},{"id":"chipswiki-274-r552","title":"Xeon Platinum 9282 — ChipsWiki, revision 552","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9282&oldid=552","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/9282"],"contentSha256":"927be8fd5ef9a69f3d9b89410ec8621d06d18f0665ada1e3b3933a70da6efaee"},{"id":"chipswiki-1248-r4019","title":"Xeon Platinum 8280M — ChipsWiki, revision 4019","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280m&oldid=4019","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8280m"],"contentSha256":"5909ace1757a281030eb07eeeb4e5d45ad260ca6fe4188078cf3fe3a4edeab0e"},{"id":"chipswiki-1446-r4886","title":"Xeon Silver 4214Y — ChipsWiki, revision 4886","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214y&oldid=4886","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_silver/4214y"],"contentSha256":"12239e27c51cdec4e57520c326f38d41b81af7810e8d783bc07cbd1d9413eab2"},{"id":"chipswiki-1448-r4889","title":"Xeon Silver 4209T — ChipsWiki, revision 4889","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4209t&oldid=4889","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_silver/4209t"],"contentSha256":"732261f5f7de77d8d09ccac2e36f31d2ef13ff548ae36567b52b6f3160c9db93"},{"id":"chipswiki-1451-r4895","title":"Xeon Silver 4110 — ChipsWiki, revision 4895","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4110&oldid=4895","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_silver/4110"],"contentSha256":"44bd7b8b86ee6894df5bb2dd37a146c09f76cc45405bd9b93da4650f51153bc0"},{"id":"chipswiki-1453-r4897","title":"Xeon Silver 4108 — ChipsWiki, revision 4897","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4108&oldid=4897","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_silver/4108"],"contentSha256":"bbe57f1452eaa1f96dfc602e0c3d8d66c7ee515625b911f21e7c6183d7c5db79"},{"id":"chipswiki-1454-r4901","title":"Xeon Platinum 8280L — ChipsWiki, revision 4901","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280l&oldid=4901","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8280l"],"contentSha256":"9ae122d37d430ca31329d8c43844c11193601f2419e70017e945eee9c02d01ff"},{"id":"chipswiki-1457-r4904","title":"Xeon Platinum 8276L — ChipsWiki, revision 4904","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276l&oldid=4904","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8276l"],"contentSha256":"a829f741744b723efa0f55cb2e43405b1945a4faa13400129a19c399da262d52"},{"id":"chipswiki-1461-r4908","title":"Xeon Platinum 8260M — ChipsWiki, revision 4908","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260m&oldid=4908","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8260m"],"contentSha256":"c8a26e5e01c0b410025e1211540ee83abf611ab60420f9bbfe2b7c424ee395c0"},{"id":"chipswiki-1462-r4909","title":"Xeon Platinum 8260Y — ChipsWiki, revision 4909","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260y&oldid=4909","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8260y"],"contentSha256":"2ee364d8777d45ed5b0a561bb500b0e4c108fa5e63bc27a3a58052ba14fe3d13"},{"id":"chipswiki-1463-r4910","title":"Xeon Platinum 8260L — ChipsWiki, revision 4910","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260l&oldid=4910","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8260l"],"contentSha256":"195fa533ca2694f6b0ee6e10b4387f2ceb6e89cabcdba7c31cb6707474ec4037"},{"id":"chipswiki-1464-r4911","title":"Xeon Platinum 8256 — ChipsWiki, revision 4911","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8256&oldid=4911","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8256"],"contentSha256":"499ca6855832584e1eeb9d439f5f9ca8d4736abe3aa916444135b40cd541fcf8"},{"id":"chipswiki-1837-r6199","title":"Xeon Platinum 8284 — ChipsWiki, revision 6199","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8284&oldid=6199","publisher":"ChipsWiki / WikiChip contributors","published":"2019-09-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8284"],"contentSha256":"1f396ee968f91e6ded19f029f41bebc4c7c45793ab7d117a3da58502da6fb9e1"},{"id":"chipswiki-2234-r7703","title":"Xeon Platinum 9221 — ChipsWiki, revision 7703","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9221&oldid=7703","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/9221"],"contentSha256":"18d34e35d6144d452b376525af8662a74baa1dffc8a2f71ada231e28bdebfded"},{"id":"chipswiki-2555-r8811","title":"Xeon Platinum 8180M — ChipsWiki, revision 8811","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180m&oldid=8811","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8180m"],"contentSha256":"5218e98900cc78cbfafb50596db810e0c905d2c0dd655712a72f8cde5d334099"},{"id":"chipswiki-4518-r14682","title":"Xeon W-2102 — ChipsWiki, revision 14682","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2102&oldid=14682","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2102"],"contentSha256":"ff8d03e9120f5759fad335e8497d75a91125005d31613c4675a7acd7252cc7cb"},{"id":"chipswiki-203-r416","title":"Xeon W-2150B — ChipsWiki, revision 416","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2150b&oldid=416","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2150b"],"contentSha256":"1aa9f0291fbdc2569dc9ee664729fa51105bb1b4921b657b16ffc67d25b1d3fd"},{"id":"chipswiki-761-r1856","title":"Xeon W-3175X — ChipsWiki, revision 1856","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3175x&oldid=1856","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3175x"],"contentSha256":"c2f727fb2314414241f702e70234ac4705069f4c1681fd2c7084f4a0403e7ea4"},{"id":"chipswiki-815-r2097","title":"Xeon W-2191B — ChipsWiki, revision 2097","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2191b&oldid=2097","publisher":"ChipsWiki / WikiChip contributors","published":"2021-02-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2191b"],"contentSha256":"31b585ca4ad40869006ec1be5a44ffad34ca9459b2c96e891831048aa1af08c2"},{"id":"chipswiki-1644-r5686","title":"Xeon W-3265 — ChipsWiki, revision 5686","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265&oldid=5686","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3265"],"contentSha256":"e615fde38dcd7dbf0c9b35ff7b3e83c2aca8cf6232f7a5f577df774f45dae32e"},{"id":"chipswiki-1703-r5935","title":"Xeon W-3275 — ChipsWiki, revision 5935","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275&oldid=5935","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3275"],"contentSha256":"93756b66679ee7da8294c369755c86e084aaef7449819f539943dd78f042a2f2"},{"id":"chipswiki-1704-r5936","title":"Xeon W-3265M — ChipsWiki, revision 5936","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3265m&oldid=5936","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3265m"],"contentSha256":"d10f98606bae5aea8c1eea7d438f3d9ea6f2258f4bbf14218338e61900cb0689"},{"id":"chipswiki-1706-r5939","title":"Xeon W-3245 — ChipsWiki, revision 5939","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245&oldid=5939","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3245"],"contentSha256":"a03640f27044d3bb1a87934927f12f99eeb883749ddaf20fd756658e3706f544"},{"id":"chipswiki-1707-r5941","title":"Xeon W-3235 — ChipsWiki, revision 5941","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3235&oldid=5941","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3235"],"contentSha256":"c896df4447049b75d58fdabb14e606a4409ff17da4d5aa44181746446dfc7ef9"},{"id":"chipswiki-1708-r5942","title":"Xeon W-3225 — ChipsWiki, revision 5942","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3225&oldid=5942","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3225"],"contentSha256":"622c47877a42d7c08e8041f595f131f6fe047f253c4c033eee4a1c26cb275a4f"},{"id":"chipswiki-2527-r8672","title":"Xeon W-2195 — ChipsWiki, revision 8672","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2195&oldid=8672","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2195"],"contentSha256":"e2e49867c114a9406f9ac4ecf55cb1840db4e8a8380bcf941428a67db9773d52"},{"id":"chipswiki-2529-r8685","title":"Xeon W-2145 — ChipsWiki, revision 8685","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2145&oldid=8685","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2145"],"contentSha256":"ef0f3e58016ba162603c06c33a818311ecd3ccded3b9a5dee09583a2d4b29c62"},{"id":"chipswiki-7688-r24983","title":"FastMATH 3 GHz — ChipsWiki, revision 24983","url":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-3&oldid=24983","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intrinsity/fastmath/fastmath-3"],"contentSha256":"2f9b2c70bd0f01f3d7b38f3b5a50d3179e9ed03656673eaa4e632dc63802fe2a"},{"id":"chipswiki-7689-r24984","title":"FastMATH 2 GHz — ChipsWiki, revision 24984","url":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-2&oldid=24984","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intrinsity/fastmath/fastmath-2"],"contentSha256":"53b61452d6d2ea8eaccfed8dff49e32fb5104d8ecc627ce25a57d178660ce3c0"},{"id":"chipswiki-7678-r24973","title":"Godson-2G — ChipsWiki, revision 24973","url":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2g&oldid=24973","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Loongson/godson_2/2g"],"contentSha256":"f9768868f9b3810184c895dc4844fec1ac779784de0234670fab18fe88ecb785"},{"id":"chipswiki-7679-r24974","title":"Godson-2F — ChipsWiki, revision 24974","url":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2f&oldid=24974","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Loongson/godson_2/2f"],"contentSha256":"a3ac2dfc97a38954fcbbcc91cdcaeb9fc988fd88a709fe9c0ed723e48cc29849"},{"id":"chipswiki-7684-r24979","title":"Godson-2B1 — ChipsWiki, revision 24979","url":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b1&oldid=24979","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Loongson/godson_2/2b1"],"contentSha256":"a3a9c2a6bae98550ec9691aed6869bdffaefaa4af854565dde5215217bc0fb91"},{"id":"chipswiki-7685-r24980","title":"Godson-2B — ChipsWiki, revision 24980","url":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2b&oldid=24980","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Loongson/godson_2/2b"],"contentSha256":"58514f8a0d39274998eaf175bc3889f1a6d8c9b1d6998a0154f49374c55c3804"},{"id":"chipswiki-7686-r24981","title":"Godson-2A — ChipsWiki, revision 24981","url":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2a&oldid=24981","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Loongson/godson_2/2a"],"contentSha256":"b87984d3f9f5e6af5d71a0fbaac3f5c36e153b3b9de1499dc91aa82b4ac956b1"},{"id":"chipswiki-9-r96925","title":"Helio A22 (MT6762M) — ChipsWiki, revision 96925","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6762m&oldid=96925","publisher":"ChipsWiki / WikiChip contributors","published":"2022-11-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6762m"],"contentSha256":"c9f4483575aec3c039ecee8b1db86eb237d2b8a1f5be2105c0f501a178de6ce0"},{"id":"chipswiki-43-r96983","title":"Helio P23 (MT6763V/MT6763T) — ChipsWiki, revision 96983","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6763t&oldid=96983","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6763t"],"contentSha256":"79f2172060b5a1b3eab84e1ea7fa8729775bc03f986dbca38002f40de934c257"},{"id":"chipswiki-91-r97049","title":"Helio P60 (MT6771) — ChipsWiki, revision 97049","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6771&oldid=97049","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6771"],"contentSha256":"a5d9bc6c5ce86ba76f644e5a034b6ae55a49e45e8e71db8978b1cbb11b9ffb2a"},{"id":"chipswiki-769-r1884","title":"Helio X20 (MT6797) — ChipsWiki, revision 1884","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797&oldid=1884","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6797"],"contentSha256":"56fd79a822f2950da4151ca42839d00cd1a1ddd8c19e5a9b4bed0d87a7eb968a"},{"id":"chipswiki-982-r2784","title":"Helio P10 (MT6755) — ChipsWiki, revision 2784","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755&oldid=2784","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6755"],"contentSha256":"c15f6e103dc7aab54969280b56c8ed0e2a9b4cff3c64ab7567248466fc955e3f"},{"id":"chipswiki-986-r2806","title":"Helio X10 (MT6795) — ChipsWiki, revision 2806","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795&oldid=2806","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6795"],"contentSha256":"3a26003b9f79795e9d1787ca6de6ea8bbedee050c49cdb75d754f1be6ee6f034"},{"id":"chipswiki-1100-r3258","title":"Dimensity 1000L — ChipsWiki, revision 3258","url":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000l&oldid=3258","publisher":"ChipsWiki / WikiChip contributors","published":"2020-06-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/dimensity/1000l"],"contentSha256":"a00b8085bd20e079ea035c2007f545e60630d7ab40e6dcdd32827ac36a39f1e8"},{"id":"chipswiki-1294-r4328","title":"Helio P10 M (MT6755M) — ChipsWiki, revision 4328","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755m&oldid=4328","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6755m"],"contentSha256":"60d3f6aa47d121c1cdae83d3d343c29c7de4d2f8989132531eb20b0d22c3de21"},{"id":"chipswiki-1636-r5644","title":"Helio P15 (MT6755T) — ChipsWiki, revision 5644","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6755t&oldid=5644","publisher":"ChipsWiki / WikiChip contributors","published":"2019-11-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6755t"],"contentSha256":"51c7f876ae724c22e7fa95add6cd65b8ef0942d7912c65e7ab287f238ffe7523"},{"id":"chipswiki-1849-r6279","title":"Helio X25 (MT6797T) — ChipsWiki, revision 6279","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797t&oldid=6279","publisher":"ChipsWiki / WikiChip contributors","published":"2019-09-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6797t"],"contentSha256":"a3562eb1599218a151b059ee23a01fed55f067b3d11218770a9ced39311328f1"},{"id":"chipswiki-2212-r7485","title":"Helio X23 (MT6797D) — ChipsWiki, revision 7485","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797d&oldid=7485","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6797d"],"contentSha256":"2c2dd36af110b538d49022ec67dd1d4cbc738999eba7f93cf3c830dd36f01912"},{"id":"chipswiki-4995-r16200","title":"Helio X10 T (MT6795T) — ChipsWiki, revision 16200","url":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795t&oldid=16200","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mediatek/helio/mt6795t"],"contentSha256":"6882186cb1318887affc47af2a4df67affba9473d8c0a3a571d14554d7175e45"},{"id":"chipswiki-7675-r24970","title":"ARMADA 618 — ChipsWiki, revision 24970","url":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F618&oldid=24970","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Marvell/armada/618"],"contentSha256":"f5b880995a934c7673105957ed08f0737f1ce5c76ccaa093dc138dd6c17dc5ef"},{"id":"chipswiki-2182-r7359","title":"Scorpio Engine — ChipsWiki, revision 7359","url":"https://chipswiki.org/index.php?title=Microsoft%2Fscorpio%20engine&oldid=7359","publisher":"ChipsWiki / WikiChip contributors","published":"2019-07-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Microsoft/scorpio_engine"],"contentSha256":"58b3cb5a4933e3da5e3b9331f8151345bc25744294bf9f9a563cbc7355533850"},{"id":"chipswiki-838-r2189","title":"SHAVE v2.0 — ChipsWiki, revision 2189","url":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v2.0&oldid=2189","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Movidius/microarchitectures/shave_v2.0"],"contentSha256":"d8c77e9ee238d76cc947a44a53160c0f3e4a92281aeb9d00c9509734533b8ce2"},{"id":"chipswiki-2939-r9839","title":"EyeQ3 — ChipsWiki, revision 9839","url":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq3&oldid=9839","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Mobileye/eyeq/eyeq3"],"contentSha256":"835f96fe05d5e133c07740e6cfaf6ac8eadec6eb9b66ff977ef90ea65ddae63b"},{"id":"chipswiki-6954-r21696","title":"Myriad 1 MA1101 — ChipsWiki, revision 21696","url":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1101&oldid=21696","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Movidius/myriad/ma1101"],"contentSha256":"18d9613f575d652601c81339308029e2787fc51b8d75e1fc670bfd68508be0a2"},{"id":"chipswiki-6971-r21758","title":"Myriad 1 MA1100 — ChipsWiki, revision 21758","url":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1100&oldid=21758","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Movidius/myriad/ma1100"],"contentSha256":"61d50615ea4ff1f1a6fb9611447598db5e72d39bcab2908035ab0f20f79eb3f0"},{"id":"chipswiki-6975-r21791","title":"SABRE — ChipsWiki, revision 21791","url":"https://chipswiki.org/index.php?title=Movidius%2Fsabre&oldid=21791","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Movidius/sabre"],"contentSha256":"c560da62ffd57d8499b23e9934ed47474868c9fd765403ebb9bd1d720a6a732e"},{"id":"chipswiki-1136-r3403","title":"SX-Aurora — ChipsWiki, revision 3403","url":"https://chipswiki.org/index.php?title=Nec%2Fmicroarchitectures%2Fsx-aurora&oldid=3403","publisher":"ChipsWiki / WikiChip contributors","published":"2020-05-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nec/microarchitectures/sx-aurora"],"contentSha256":"2349625b34a190ebf9a740b7ed1142cce6f39ef070ec17ab1453ff8fe5f98851"},{"id":"chipswiki-1590-r5320","title":"Vector Engine Type 10CE — ChipsWiki, revision 5320","url":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ce&oldid=5320","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nec/vector_engine/type_10ce"],"contentSha256":"b715bb4405689c66a1a03baf4dd24e1d6bd724fa965d0a055bea564ec5e103a7"},{"id":"chipswiki-1594-r5332","title":"Vector Engine Type 10B — ChipsWiki, revision 5332","url":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010b&oldid=5332","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nec/vector_engine/type_10b"],"contentSha256":"48123264bf637bf395fef826a4150cd69fee4ab3a8986465e22ba616cb004f65"},{"id":"chipswiki-1595-r5336","title":"Vector Engine Type 10A — ChipsWiki, revision 5336","url":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010a&oldid=5336","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nec/vector_engine/type_10a"],"contentSha256":"923389e15257b1262015b87d2dc0fce0771f5819e40be7ff745a7d07d90d21a2"},{"id":"chipswiki-1181-r3688","title":"Spring Crest — ChipsWiki, revision 3688","url":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Fspring%20crest&oldid=3688","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nervana/microarchitectures/spring_crest"],"contentSha256":"ac438407a307667d7f4cece929909888d91b9e8d666642df1bbd9af1c670f424"},{"id":"chipswiki-1300-r4341","title":"Denver — ChipsWiki, revision 4341","url":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fdenver&oldid=4341","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nvidia/microarchitectures/denver"],"contentSha256":"2f0a2c78b33d680073da367776b39885fed1a93cba1c1d4d733207684c7ab4a0"},{"id":"chipswiki-2930-r9794","title":"Carmel — ChipsWiki, revision 9794","url":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fcarmel&oldid=9794","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nvidia/microarchitectures/carmel"],"contentSha256":"9cae8fc12827bbbcd7e897ff81287bfaffbf5bed18adb88dbb7ce5a21e5e9941"},{"id":"chipswiki-4988-r16134","title":"NVSwitch — ChipsWiki, revision 16134","url":"https://chipswiki.org/index.php?title=Nvidia%2Fnvswitch&oldid=16134","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Nvidia/nvswitch"],"contentSha256":"60262bedb11cf8d531a17fdcc9e8e3b439beaf6c9dc0e551d796a528e43979b5"},{"id":"chipswiki-1603-r5376","title":"MN-Core — ChipsWiki, revision 5376","url":"https://chipswiki.org/index.php?title=Preferred%20networks%2Fmicroarchitectures%2Fmn-core&oldid=5376","publisher":"ChipsWiki / WikiChip contributors","published":"2019-11-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Preferred_networks/microarchitectures/mn-core"],"contentSha256":"118449d9d72f1c2a8ad3e5c4a2e924b6ab5609e0daf7a27fd9365406e3cd5e6b"},{"id":"chipswiki-1822-r6121","title":"PEZY-SC3 — ChipsWiki, revision 6121","url":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc3&oldid=6121","publisher":"ChipsWiki / WikiChip contributors","published":"2019-09-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Pezy/pezy-scx/pezy-sc3"],"contentSha256":"bd564a8eb82ad505e6461127d764c8f1d7a42f72602755477e3b80286fe488a4"},{"id":"chipswiki-3766-r11689","title":"FT-1500A/16 — ChipsWiki, revision 11689","url":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-16&oldid=11689","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Phytium/feiteng/ft-1500a-16"],"contentSha256":"f51af5e11d7a00e211bae3811701cab9a728bd4f1bfad3a9a0ae8c928ff3bb97"},{"id":"chipswiki-3770-r11697","title":"FT-2000+/64 — ChipsWiki, revision 11697","url":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000%2B-64&oldid=11697","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Phytium/feiteng/ft-2000+-64"],"contentSha256":"392a4188f7989435a0b0c3a41f52941e7298d6ee0416dd43d40e0e89097228bc"},{"id":"chipswiki-4785-r15454","title":"PEZY-SC — ChipsWiki, revision 15454","url":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc&oldid=15454","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Pezy/pezy-scx/pezy-sc"],"contentSha256":"970669e5ca4388c9767c9a0cd55d51937d92c04b988aa50d7acdb7759e1fb42c"},{"id":"chipswiki-31352-r92105","title":"Template:Packages/pezy/fcbga-2112 — revision 92105","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2112&oldid=92105","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fpezy%2Ffcbga-2112"],"contentSha256":"2618b41e4b06f26b0a5bb50e48a3393ce2623467a38e345c7328e6129868f0b9"},{"id":"chipswiki-6357-r19743","title":"PEZY-SC4 — ChipsWiki, revision 19743","url":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc4&oldid=19743","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Pezy/pezy-scx/pezy-sc4"],"contentSha256":"122d76fa39aad7366428c92a231c105b6703be1b12f5feb5e5237835ca33d72f"},{"id":"chipswiki-553-r1149","title":"MSM6000 — ChipsWiki, revision 1149","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6000&oldid=1149","publisher":"ChipsWiki / WikiChip contributors","published":"2021-12-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6000"],"contentSha256":"cd20d68278071a07258c98ff8812738124e7cc728b15d944e37b81ebc18692f8"},{"id":"chipswiki-605-r1411","title":"Cloud AI 100 — ChipsWiki, revision 1411","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fcloud%20ai%20100&oldid=1411","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/microarchitectures/cloud_ai_100"],"contentSha256":"88e98e576edb93779f46cf6feab43b42abf1ad6e37498eccd347a6c905fb946f"},{"id":"chipswiki-743-r1781","title":"Falkor — ChipsWiki, revision 1781","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Ffalkor&oldid=1781","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/microarchitectures/falkor"],"contentSha256":"e45295b515b775105e3b1acb3ea5c36b6f0d5feafb79f4ef1307decf91dc4a2f"},{"id":"chipswiki-1696-r5908","title":"Saphira — ChipsWiki, revision 5908","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fsaphira&oldid=5908","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/microarchitectures/saphira"],"contentSha256":"43e5b0cadd31e9d4e6e805648422c30a0e559baabfb722a5cfa39ebfc20af2c7"},{"id":"chipswiki-1858-r6392","title":"MSM6250A — ChipsWiki, revision 6392","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250a&oldid=6392","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6250a"],"contentSha256":"d5636903533728fe8da7eab1c4254ae6806053b776775eb6a7813f597d6b03a6"},{"id":"chipswiki-7660-r24923","title":"MSM6275 — ChipsWiki, revision 24923","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6275&oldid=24923","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6275"],"contentSha256":"ed482242ba7a75f3609e88fa46e60f59021bfebc3c947264375d5314931b0ac8"},{"id":"chipswiki-7661-r24924","title":"MSM6260 — ChipsWiki, revision 24924","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6260&oldid=24924","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6260"],"contentSha256":"296a7081d6b6aae9245045b236550c0ad3fc1b6291d2aaaa2e6efa6a38e2c306"},{"id":"chipswiki-7662-r24925","title":"MSM6255A — ChipsWiki, revision 24925","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6255a&oldid=24925","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6255a"],"contentSha256":"f91216e4d7eb83f9889cf379ec8aca55b19b9e6dc4bccfb7bdf7d1a350d8bbb3"},{"id":"chipswiki-7664-r24930","title":"MSM6200 — ChipsWiki, revision 24930","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6200&oldid=24930","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6200"],"contentSha256":"8694d7d68df6d9b5b84273fbc818013dfc9cda292c3b81d2c21aaea78584cfd3"},{"id":"chipswiki-7665-r24931","title":"MSM6150 — ChipsWiki, revision 24931","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6150&oldid=24931","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6150"],"contentSha256":"b853a7a5614129b0353cd5c11736340b9ded785c598a9210a0deabf55c6c9690"},{"id":"chipswiki-7670-r24937","title":"Centriq 2460 — ChipsWiki, revision 24937","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2460&oldid=24937","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/centriq/2460"],"contentSha256":"ec9f1887d60523d8f086a9357f1564d16aaf6ee1e89119ce99467f896d752169"},{"id":"chipswiki-31367-r92153","title":"Template:Packages/qualcomm/fclga-2808 — revision 92153","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fqualcomm%2Ffclga-2808"],"contentSha256":"3bf4f1d644c5d13f20ab44ec5fb85b1725b94bc00bacfa98995924209ce8ed77"},{"id":"chipswiki-7671-r24938","title":"Centriq 2452 — ChipsWiki, revision 24938","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2452&oldid=24938","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/centriq/2452"],"contentSha256":"93046de5a784a50047d988ccf9441740b7db49bf02e6f4f9c754f30e42ae18dc"},{"id":"chipswiki-41-r96981","title":"Snapdragon 855 — ChipsWiki, revision 96981","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855&oldid=96981","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_800/855"],"contentSha256":"270b6faed4bb29877f6c5cf37dc77a1851e696882937beec19b09f58d4ee2b9a"},{"id":"chipswiki-326-r648","title":"Snapdragon 660 — ChipsWiki, revision 648","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F660&oldid=648","publisher":"ChipsWiki / WikiChip contributors","published":"2022-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_600/660"],"contentSha256":"dcd079bb150392b50321c70ebf0b4e1f40e4b9c4b091bfc77da367417e117e75"},{"id":"chipswiki-331-r673","title":"Snapdragon 845 — ChipsWiki, revision 673","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F845&oldid=673","publisher":"ChipsWiki / WikiChip contributors","published":"2022-06-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_800/845"],"contentSha256":"e281bc585d7c0915c16e9397c7392b20ab658678a37c66d2edd861dfe38123b1"},{"id":"chipswiki-557-r1160","title":"Snapdragon 675 — ChipsWiki, revision 1160","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F675&oldid=1160","publisher":"ChipsWiki / WikiChip contributors","published":"2021-12-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_600/675"],"contentSha256":"0e9844294555dbe25edc968e3364077b5f24a97a708167d024d8e5b943567e19"},{"id":"chipswiki-588-r1359","title":"Snapdragon 665 — ChipsWiki, revision 1359","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F665&oldid=1359","publisher":"ChipsWiki / WikiChip contributors","published":"2021-10-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_600/665"],"contentSha256":"df5f0c141e13d824f6119eee7df26d62746cb6b423d07cea13dc7daf846a7dbc"},{"id":"chipswiki-682-r1673","title":"Snapdragon 460 — ChipsWiki, revision 1673","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F460&oldid=1673","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_400/460"],"contentSha256":"00a6b8b2dfd18f63c4872f56edc9f733976299c6be22c50d65cf48640371c261"},{"id":"chipswiki-950-r2686","title":"Snapdragon 712 — ChipsWiki, revision 2686","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F712&oldid=2686","publisher":"ChipsWiki / WikiChip contributors","published":"2020-09-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/snapdragon_700/712"],"contentSha256":"cd4913240b886df86583d9214bacc6f339df8be1a8f3ebf632fed576ea4aec6b"},{"id":"chipswiki-6393-r19871","title":"QCS603 — ChipsWiki, revision 19871","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs603&oldid=19871","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/vision_intelligence/qcs603"],"contentSha256":"2957436d98eff14749c174c2c02bf84425c5105d3d808f95eae69503912d5e7a"},{"id":"chipswiki-6394-r19877","title":"QCS605 — ChipsWiki, revision 19877","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fvision%20intelligence%2Fqcs605&oldid=19877","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/vision_intelligence/qcs605"],"contentSha256":"3e3063ff609a58671b35f8fb0b3d36f19944079a2bd492a05d958cd9b048cf96"},{"id":"chipswiki-7655-r24916","title":"MSM6700 — ChipsWiki, revision 24916","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6700&oldid=24916","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6700"],"contentSha256":"ce97b24962fd4f0e6a1b41c4da6e2dd3d6bf5ae9a1feab33ff1521b5c15f5fbd"},{"id":"chipswiki-7657-r24918","title":"MSM6575 — ChipsWiki, revision 24918","url":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6575&oldid=24918","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Qualcomm/msm6xxx/msm6575"],"contentSha256":"b6f1b3e4d8680e3c8ec73f5c3c8f24a51d94fbc618e6a48e99f5def14dc254df"},{"id":"chipswiki-286-r574","title":"PPS-4 (10660) — ChipsWiki, revision 574","url":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F10660&oldid=574","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Rockwell_international/pps-4/10660"],"contentSha256":"0c1e2c5cfd80c95bd964b865e168db8a8ff98bf6b07f3988c04974d6d6c37b09"},{"id":"chipswiki-4178-r13355","title":"R-Car H3 — ChipsWiki, revision 13355","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3&oldid=13355","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/h3"],"contentSha256":"81f202dcee78bae0f4497af9ac1781828e61baeef8eb38730046f1cf1a93205c"},{"id":"chipswiki-31422-r92286","title":"Template:Packages/renesas/fcbga-1384 — revision 92286","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1384&oldid=92286","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Frenesas%2Ffcbga-1384"],"contentSha256":"acdaad5d286d568153d520fe8421e018d5118e70882fdb1efc50772abe44775f"},{"id":"chipswiki-7641-r24900","title":"PPS-4/2 (11660) — ChipsWiki, revision 24900","url":"https://chipswiki.org/index.php?title=Rockwell%20international%2Fpps-4%2F11660&oldid=24900","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Rockwell_international/pps-4/11660"],"contentSha256":"7de43422c4d202117b50e9a1f51f838b1e023d813e22b1a9e7939e89041e3c4f"},{"id":"chipswiki-7643-r24903","title":"R-Car M3 (SiP) — ChipsWiki, revision 24903","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3%20(sip)&oldid=24903","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/m3_(sip)"],"contentSha256":"0fddb20920c0e0a7f56a9b46c5a12a7ecdce40ab0dff4b122a7f42cab1b0c58c"},{"id":"chipswiki-31420-r92284","title":"Template:Packages/renesas/fcbga-1255 — revision 92284","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Frenesas%2Ffcbga-1255"],"contentSha256":"bff460d091406e6737b6a5a688888f333a0da537066ab5495780e0a404498864"},{"id":"chipswiki-31425-r92293","title":"Template:Packages/renesas/fcbga-831 — revision 92293","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Frenesas%2Ffcbga-831"],"contentSha256":"a2ebf029c99e2b6ae849d31502e8d6f4d6f747a115d9449ebcd77ebed3cc959f"},{"id":"chipswiki-31427-r92297","title":"Template:Packages/renesas/fcbga-472 — revision 92297","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Frenesas%2Ffcbga-472"],"contentSha256":"675796b0adc28984f76faa8df326650d8f34ea823a16686a96aba603368092c7"},{"id":"chipswiki-7647-r24907","title":"R-Car M1A — ChipsWiki, revision 24907","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1a&oldid=24907","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/m1a"],"contentSha256":"1d93b8702f7d67e1d3e06bc56d800d824e0f4ad6af4b45d5ff8709ad69445781"},{"id":"chipswiki-7648-r24908","title":"R-Car L1 — ChipsWiki, revision 24908","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fl1&oldid=24908","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/l1"],"contentSha256":"fc78f71f894f34f8bab43cc53eed2ad49009918526f498829cefe92f2dc34aae"},{"id":"chipswiki-31426-r92295","title":"Template:Packages/renesas/fcbga-429 — revision 92295","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-429&oldid=92295","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Frenesas%2Ffcbga-429"],"contentSha256":"5777d5827e4098d1eab35c2afe76fb1349ea9da34d77de173ac32dda365236e9"},{"id":"chipswiki-7650-r24911","title":"R-Car H2 — ChipsWiki, revision 24911","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh2&oldid=24911","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/h2"],"contentSha256":"4fe32bb61ff6269e838ba1af30c744c5325244ddbabd62ee90079cff614baa84"},{"id":"chipswiki-7652-r24913","title":"R-Car E2 — ChipsWiki, revision 24913","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe2&oldid=24913","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/e2"],"contentSha256":"fd2bc3f54021ac15e1784bf789171e91a9b74ae75f161406eac00b1df23605cd"},{"id":"chipswiki-31424-r92292","title":"Template:Packages/renesas/fcbga-501 — revision 92292","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-501&oldid=92292","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Frenesas%2Ffcbga-501"],"contentSha256":"eab364c888dfd47d7a11072115ebe99be4a7b06c4aa976d1f35338a0c9b4e62f"},{"id":"chipswiki-7653-r24914","title":"R-Car E1 — ChipsWiki, revision 24914","url":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fe1&oldid=24914","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Renesas/r-car/e1"],"contentSha256":"395bb598e437826ee22bd8a95dc9b060e45f8a5cb1d0a4572e62208c0c2bb5e2"},{"id":"chipswiki-288-r579","title":"Exynos 9810 — ChipsWiki, revision 579","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9810&oldid=579","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/9810"],"contentSha256":"1e9686391a10d2eefc904b0a51c98c539dea6a3181ebb3ef9faf3cfa8371d769"},{"id":"chipswiki-551-r1140","title":"Exynos 990 — ChipsWiki, revision 1140","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F990&oldid=1140","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/990"],"contentSha256":"bfab85ae71ecd554f7f3fbc02436f8db4983c4402cb117524736f0934ec4c597"},{"id":"chipswiki-839-r2200","title":"Exynos 7885 — ChipsWiki, revision 2200","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7885&oldid=2200","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7885"],"contentSha256":"eefe371acae9ca79cc8724d062d29f77989c7c960d2101a42ec07cb8f7b4279b"},{"id":"chipswiki-984-r2794","title":"Exynos M4 — ChipsWiki, revision 2794","url":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm4&oldid=2794","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/microarchitectures/m4"],"contentSha256":"5c65b60b83ca6162445d3a6f4a0f23402175474c6b4c099d56ea6c433110c360"},{"id":"chipswiki-1290-r4302","title":"Exynos M3 — ChipsWiki, revision 4302","url":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm3&oldid=4302","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/microarchitectures/m3"],"contentSha256":"335d5580966d5feea6f0bb43f5518b5c1c2c97721003a351308f63148c55ddda"},{"id":"chipswiki-3826-r12084","title":"Exynos M1 — ChipsWiki, revision 12084","url":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm1&oldid=12084","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/microarchitectures/m1"],"contentSha256":"c96bd5f1c35ce0f8ef4efeb49faeb4456061bd137b9b9f792de5aa252b255641"},{"id":"chipswiki-6839-r21313","title":"Exynos 3470 — ChipsWiki, revision 21313","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3470&oldid=21313","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/3470"],"contentSha256":"ae19cd7f07de39a00dc65de6f145b2ef7e87feb13a94d5f5939406f1e5f2728b"},{"id":"chipswiki-6840-r21322","title":"Exynos 7880 — ChipsWiki, revision 21322","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7880&oldid=21322","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7880"],"contentSha256":"74a58f2abbf9700c41cb65d3a17cd54e8f12a8883c323d31a1083bfb00962748"},{"id":"chipswiki-6842-r21325","title":"Exynos 7870 — ChipsWiki, revision 21325","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7870&oldid=21325","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7870"],"contentSha256":"de8d98f2069e0878d40b3966dcc1ac697272dc300bf0b2c9d33af5ae06cbe3a9"},{"id":"chipswiki-6843-r21327","title":"Exynos 7580 — ChipsWiki, revision 21327","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7580&oldid=21327","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7580"],"contentSha256":"02fdb6860c17967fba5896ccb77ea7d9732496d3f4331a0d380ea130e1db870c"},{"id":"chipswiki-6851-r21347","title":"Exynos 5260 — ChipsWiki, revision 21347","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5260&oldid=21347","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/5260"],"contentSha256":"1a6308277a0d976cdfa60730af3462a8d75543da6565b24bc04aaa4b31a712f0"},{"id":"chipswiki-6852-r21350","title":"Exynos 5250 — ChipsWiki, revision 21350","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5250&oldid=21350","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/5250"],"contentSha256":"d9fee323228dc4f5121f08b2a0916a4ef1aafaa7ba64543fb9c359921e73558e"},{"id":"chipswiki-6856-r21392","title":"Exynos 3110 — ChipsWiki, revision 21392","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F3110&oldid=21392","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/3110"],"contentSha256":"c23b345289e210c93bf3f79bf314edb7871e014ac5a64ac291ce72e4a0b103e2"},{"id":"chipswiki-3888-r12290","title":"SC2A11 — ChipsWiki, revision 12290","url":"https://chipswiki.org/index.php?title=Socionext%2Fsc2a11&oldid=12290","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Socionext/sc2a11"],"contentSha256":"75485d1867d62945f66a6aa63d6fc95c29600c6c17ac387b99c9f1cf326caff6"},{"id":"chipswiki-4352-r14046","title":"7 Series — ChipsWiki, revision 14046","url":"https://chipswiki.org/index.php?title=Sifive%2Fmicroarchitectures%2F7%20series&oldid=14046","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Sifive/microarchitectures/7_series"],"contentSha256":"9e2ea0dc68b9a30cfd77a26b481d817dbe1a83079ed95b866e6da4e4c59e6775"},{"id":"chipswiki-7637-r24894","title":"UltraSPARC-I 200MHz — ChipsWiki, revision 24894","url":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-200&oldid=24894","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Sun_microsystems/ultrasparc/stp1030bga-200"],"contentSha256":"6ff2543f4ff4ed0851e7f44433bc65b247513863969202c17d50d6f086f966b5"},{"id":"chipswiki-31351-r92104","title":"Template:Packages/sun microsystems/bga-521 — revision 92104","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fsun_microsystems%2Fbga-521"],"contentSha256":"90b140a8ce1fc768c9105fb15bd7efe559a53695d45d24301fe232e5f04c3adb"},{"id":"chipswiki-597-r1394","title":"FSD Chip — ChipsWiki, revision 1394","url":"https://chipswiki.org/index.php?title=Tesla%20(car%20company)%2Ffsd%20chip&oldid=1394","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Tesla_(car_company)/fsd_chip"],"contentSha256":"0b69b7ae2b1a751998af1dc8d5c792aa82898e2876626326ff0dafef78a034f0"},{"id":"chipswiki-31332-r92062","title":"Template:Packages/pdip-64 — revision 92062","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fpdip-64"],"contentSha256":"9dfa6e5fe7387cbf3e1eb1114f7bd82f7cb90531e8d329862ddf25e1ab5d94e9"},{"id":"chipswiki-31333-r92063","title":"Template:Packages/cdip-64 — revision 92063","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fcdip-64"],"contentSha256":"2a0efed6b5a27e03f05c7b400e13abdacd885078edb4db227602db0e3d5fd701"},{"id":"chipswiki-1380-r4623","title":"Vanilla-5 — ChipsWiki, revision 4623","url":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fvanilla-5&oldid=4623","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Umich/microarchitectures/vanilla-5"],"contentSha256":"d0d020fc9085c24a5a6661dad02c2c2a5a678ab4d41010fa43927828c3abc008"},{"id":"chipswiki-1695-r5907","title":"Hanguang 800 — ChipsWiki, revision 5907","url":"https://chipswiki.org/index.php?title=T-head%2Fhanguang%20800&oldid=5907","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/T-head/hanguang_800"],"contentSha256":"a8ef61d7df5f6764eb7317d208a1acd22c4806c384fccac8c2e51f6077b57fef"},{"id":"chipswiki-2541-r8759","title":"KiloCore — ChipsWiki, revision 8759","url":"https://chipswiki.org/index.php?title=Uc%20davis%2Fkilocore&oldid=8759","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Uc_davis/kilocore"],"contentSha256":"273af2b33ed5642d9ac3d6637cb4213f0813c1ec40256868d1115885f4435937"},{"id":"chipswiki-7636-r24893","title":"TMX1795 — ChipsWiki, revision 24893","url":"https://chipswiki.org/index.php?title=Ti%2Ftmx1795&oldid=24893","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ti/tmx1795"],"contentSha256":"284822557ff3a5c75b6d77efcfd27278296162b15ee230bae0f1a839acd0fa02"},{"id":"chipswiki-8670-r26885","title":"TMS1099 — ChipsWiki, revision 26885","url":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099&oldid=26885","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ti/tms1000/tms1099"],"contentSha256":"c99232398db31099c6c583b1eba14a04401de5be2dc8fb4d8c55a6f587f604da"},{"id":"chipswiki-7378-r23864","title":"Esther — ChipsWiki, revision 23864","url":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Festher&oldid=23864","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Via_technologies/microarchitectures/esther"],"contentSha256":"d01d9828b3723c685c6715f33331c1e72244d9e40ec1216061660ae71ff7db6b"},{"id":"chipswiki-7379-r23865","title":"Nehemiah — ChipsWiki, revision 23865","url":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fnehemiah&oldid=23865","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Via_technologies/microarchitectures/nehemiah"],"contentSha256":"0ba6dd7ce80fb5225bd36aa89a4bb04c21523ca6d696e5e164f1cb245d047541"},{"id":"chipswiki-7381-r23867","title":"Samuel 2 — ChipsWiki, revision 23867","url":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fsamuel%202&oldid=23867","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Via_technologies/microarchitectures/samuel_2"],"contentSha256":"1fc41c596807dfbe627134018837ad7d9b20790c921e86854103010382732e4b"},{"id":"chipswiki-7622-r24877","title":"VY86C810 — ChipsWiki, revision 24877","url":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c810&oldid=24877","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Vti/vl86cx/vy86c810"],"contentSha256":"59e9bf8f2f902cd31c6ff51c32588dfb32942ef5309f572c13433d92d3f71d89"},{"id":"chipswiki-31401-r92231","title":"Template:Packages/vti/tqfp-144 — revision 92231","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fvti%2Ftqfp-144"],"contentSha256":"d2bace9f0c81a2f47cae4a6f5b4ce14a23a41da6d18d28b52ac89fa3fc853f9e"},{"id":"chipswiki-7629-r24884","title":"VY86C060A — ChipsWiki, revision 24884","url":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060a&oldid=24884","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Vti/vl86cx/vy86c060a"],"contentSha256":"7603ef49412777147908fb188dcddd0054f0a02387c9b87dd092f05a018673cd"},{"id":"chipswiki-7630-r24885","title":"VY86C06040 — ChipsWiki, revision 24885","url":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06040&oldid=24885","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Vti/vl86cx/vy86c06040"],"contentSha256":"a95f3b59b3d220984e72d0dc3d50e42d1d2abd596adf14951aaae16c0a7ea9fc"},{"id":"chipswiki-31437-r92358","title":"Template:Packages/vti/tqfp-100 — revision 92358","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-100&oldid=92358","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fvti%2Ftqfp-100"],"contentSha256":"edd478cb398fe65352476a0ca9fc6cb62f3481b7e7838b2e78cb57de2f6da53d"},{"id":"chipswiki-399-r866","title":"Surge S1 — ChipsWiki, revision 866","url":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs1&oldid=866","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Xiaomi/surge/s1"],"contentSha256":"ba777a7e746235750fb2b5a6176e71755ab49c19e14733eef116385d5f1d3e54"},{"id":"chipswiki-1575-r5202","title":"LuJiaZui — ChipsWiki, revision 5202","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Flujiazui&oldid=5202","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/microarchitectures/lujiazui"],"contentSha256":"f31237eeee883d5e2d53c80452095565c8702dc7ca025e29c33a74f7466445cf"},{"id":"chipswiki-4515-r14675","title":"KaiXian KX-U6880 — ChipsWiki, revision 14675","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u6880&oldid=14675","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaixian/kx-u6880"],"contentSha256":"fc4c8aaed933cedc80303f8ddc9c8fe6d1ee585ca20999d0de916463b8967979"},{"id":"chipswiki-5648-r18546","title":"KaiXian KX-U5680 — ChipsWiki, revision 18546","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5680&oldid=18546","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaixian/kx-u5680"],"contentSha256":"b95dac91c949592572babc076f48ad57b3e1b9e8cd8d18432f0345ac4bf13dce"},{"id":"chipswiki-5650-r18548","title":"KaiXian KX-U5580 — ChipsWiki, revision 18548","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580&oldid=18548","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaixian/kx-u5580"],"contentSha256":"de6c38e911c5bf5c2088c28ceb7d49dac22b8335ff853cd4126cd36a481acf8c"},{"id":"chipswiki-7265-r23218","title":"KaisHeng KH-26800 — ChipsWiki, revision 23218","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-26800&oldid=23218","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaisheng/kh-26800"],"contentSha256":"8f9d5a2480054b08b6418a41759d5ae317e379d8f6b21d180703d48b9def0757"}]}